diff options
author | Stephen Hemminger <shemminger@osdl.org> | 2005-07-22 19:26:07 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-07-31 00:40:53 -0400 |
commit | 2c66851460c9438823e39b76887376d1511fb67c (patch) | |
tree | 5a1028f8abb4ef03772f9f09c7e77cc7c110ca2b /drivers/net/skge.h | |
parent | 382317138b3ade02c9c319531ab0619e95dbc672 (diff) |
[PATCH] skge: whitespace fixes
Minor whitespace cleanups.
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/skge.h')
-rw-r--r-- | drivers/net/skge.h | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/net/skge.h b/drivers/net/skge.h index fced3d2bc072..2086809f4b03 100644 --- a/drivers/net/skge.h +++ b/drivers/net/skge.h | |||
@@ -1509,7 +1509,7 @@ enum { | |||
1509 | PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ | 1509 | PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */ |
1510 | }; | 1510 | }; |
1511 | 1511 | ||
1512 | #define PHY_M_LED_PULS_DUR(x) ( ((x)<<12) & PHY_M_LEDC_PULS_MSK) | 1512 | #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK) |
1513 | 1513 | ||
1514 | enum { | 1514 | enum { |
1515 | PULS_NO_STR = 0,/* no pulse stretching */ | 1515 | PULS_NO_STR = 0,/* no pulse stretching */ |
@@ -1522,7 +1522,7 @@ enum { | |||
1522 | PULS_1300MS = 7,/* 1.3 s to 2.7 s */ | 1522 | PULS_1300MS = 7,/* 1.3 s to 2.7 s */ |
1523 | }; | 1523 | }; |
1524 | 1524 | ||
1525 | #define PHY_M_LED_BLINK_RT(x) ( ((x)<<8) & PHY_M_LEDC_BL_R_MSK) | 1525 | #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK) |
1526 | 1526 | ||
1527 | enum { | 1527 | enum { |
1528 | BLINK_42MS = 0,/* 42 ms */ | 1528 | BLINK_42MS = 0,/* 42 ms */ |
@@ -1602,9 +1602,9 @@ enum { | |||
1602 | PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ | 1602 | PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */ |
1603 | }; | 1603 | }; |
1604 | 1604 | ||
1605 | #define PHY_M_FELP_LED2_CTRL(x) ( ((x)<<8) & PHY_M_FELP_LED2_MSK) | 1605 | #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK) |
1606 | #define PHY_M_FELP_LED1_CTRL(x) ( ((x)<<4) & PHY_M_FELP_LED1_MSK) | 1606 | #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK) |
1607 | #define PHY_M_FELP_LED0_CTRL(x) ( ((x)<<0) & PHY_M_FELP_LED0_MSK) | 1607 | #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK) |
1608 | 1608 | ||
1609 | enum { | 1609 | enum { |
1610 | LED_PAR_CTRL_COLX = 0x00, | 1610 | LED_PAR_CTRL_COLX = 0x00, |
@@ -1640,7 +1640,7 @@ enum { | |||
1640 | PHY_M_MAC_MD_COPPER = 5,/* Copper only */ | 1640 | PHY_M_MAC_MD_COPPER = 5,/* Copper only */ |
1641 | PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ | 1641 | PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */ |
1642 | }; | 1642 | }; |
1643 | #define PHY_M_MAC_MODE_SEL(x) ( ((x)<<7) & PHY_M_MAC_MD_MSK) | 1643 | #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK) |
1644 | 1644 | ||
1645 | /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ | 1645 | /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ |
1646 | enum { | 1646 | enum { |
@@ -1650,10 +1650,10 @@ enum { | |||
1650 | PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ | 1650 | PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ |
1651 | }; | 1651 | }; |
1652 | 1652 | ||
1653 | #define PHY_M_LEDC_LOS_CTRL(x) ( ((x)<<12) & PHY_M_LEDC_LOS_MSK) | 1653 | #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK) |
1654 | #define PHY_M_LEDC_INIT_CTRL(x) ( ((x)<<8) & PHY_M_LEDC_INIT_MSK) | 1654 | #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK) |
1655 | #define PHY_M_LEDC_STA1_CTRL(x) ( ((x)<<4) & PHY_M_LEDC_STA1_MSK) | 1655 | #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK) |
1656 | #define PHY_M_LEDC_STA0_CTRL(x) ( ((x)<<0) & PHY_M_LEDC_STA0_MSK) | 1656 | #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK) |
1657 | 1657 | ||
1658 | /* GMAC registers */ | 1658 | /* GMAC registers */ |
1659 | /* Port Registers */ | 1659 | /* Port Registers */ |