diff options
author | Stephen Hemminger <shemminger@osdl.org> | 2005-06-27 14:33:12 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-06-27 18:05:06 -0400 |
commit | 45bada65c2a0bcc00729646071e66042ced64998 (patch) | |
tree | 91cc168686042f41149ea782ae91e8f8276b4402 /drivers/net/skge.h | |
parent | 31b619c5abaa5512e7b41f190f9b7903b902f29a (diff) |
[PATCH] skge: make Genesis/Broadcom code work
Rewrite the code for handling the Broadcom PHY to something that
works. Remove link polling because Broadcom and Yukon don't need it.
When I wrote initial code, didn't have a genesis chipset based
board to test, so it was a non-working guess.
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Diffstat (limited to 'drivers/net/skge.h')
-rw-r--r-- | drivers/net/skge.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/net/skge.h b/drivers/net/skge.h index 6f3a4b56a671..6b9a2ebbab28 100644 --- a/drivers/net/skge.h +++ b/drivers/net/skge.h | |||
@@ -1225,6 +1225,16 @@ enum { | |||
1225 | PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */ | 1225 | PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */ |
1226 | }; | 1226 | }; |
1227 | 1227 | ||
1228 | /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ | ||
1229 | /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/ | ||
1230 | enum { | ||
1231 | PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */ | ||
1232 | |||
1233 | PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */ | ||
1234 | PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */ | ||
1235 | }; | ||
1236 | |||
1237 | |||
1228 | /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ | 1238 | /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/ |
1229 | enum { | 1239 | enum { |
1230 | PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */ | 1240 | PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */ |
@@ -1285,7 +1295,9 @@ enum { | |||
1285 | PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */ | 1295 | PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */ |
1286 | PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */ | 1296 | PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */ |
1287 | }; | 1297 | }; |
1288 | #define PHY_B_DEF_MSK (~(PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) | 1298 | #define PHY_B_DEF_MSK \ |
1299 | (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \ | ||
1300 | PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE)) | ||
1289 | 1301 | ||
1290 | /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ | 1302 | /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */ |
1291 | enum { | 1303 | enum { |
@@ -2489,7 +2501,6 @@ struct skge_port { | |||
2489 | dma_addr_t dma; | 2501 | dma_addr_t dma; |
2490 | unsigned long mem_size; | 2502 | unsigned long mem_size; |
2491 | 2503 | ||
2492 | struct timer_list link_check; | ||
2493 | struct timer_list led_blink; | 2504 | struct timer_list led_blink; |
2494 | }; | 2505 | }; |
2495 | 2506 | ||