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authorStephen Hemminger <shemminger@osdl.org>2005-11-08 13:33:45 -0500
committerJeff Garzik <jgarzik@pobox.com>2005-11-08 23:58:08 -0500
commit8f3f8193a49e1eb0d2e01309fdef2ad4fb33293c (patch)
tree147067f2b6973643483472c3c09eb05ee0973fbf /drivers/net/skge.c
parent1631aef15193ef8a199982fa3d45db4d07786d7f (diff)
[PATCH] skge: spelling fixes
Fix some of my bad spelling. Signed-off-by: Stephen Hemminger <shemminger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/skge.c')
-rw-r--r--drivers/net/skge.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 389d0be35865..df30274aad11 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -130,7 +130,7 @@ static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
130 regs->len - B3_RI_WTO_R1); 130 regs->len - B3_RI_WTO_R1);
131} 131}
132 132
133/* Wake on Lan only supported on Yukon chps with rev 1 or above */ 133/* Wake on Lan only supported on Yukon chips with rev 1 or above */
134static int wol_supported(const struct skge_hw *hw) 134static int wol_supported(const struct skge_hw *hw)
135{ 135{
136 return !((hw->chip_id == CHIP_ID_GENESIS || 136 return !((hw->chip_id == CHIP_ID_GENESIS ||
@@ -170,8 +170,8 @@ static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
170 return 0; 170 return 0;
171} 171}
172 172
173/* Determine supported/adverised modes based on hardware. 173/* Determine supported/advertised modes based on hardware.
174 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx 174 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
175 */ 175 */
176static u32 skge_supported_modes(const struct skge_hw *hw) 176static u32 skge_supported_modes(const struct skge_hw *hw)
177{ 177{
@@ -532,13 +532,13 @@ static inline u32 hwkhz(const struct skge_hw *hw)
532 return 78215; /* or: 78.125 MHz */ 532 return 78215; /* or: 78.125 MHz */
533} 533}
534 534
535/* Chip hz to microseconds */ 535/* Chip HZ to microseconds */
536static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) 536static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
537{ 537{
538 return (ticks * 1000) / hwkhz(hw); 538 return (ticks * 1000) / hwkhz(hw);
539} 539}
540 540
541/* Microseconds to chip hz */ 541/* Microseconds to chip HZ */
542static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) 542static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
543{ 543{
544 return hwkhz(hw) * usec / 1000; 544 return hwkhz(hw) * usec / 1000;
@@ -1163,7 +1163,7 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo)
1163 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); 1163 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1164 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); 1164 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1165 1165
1166 /* Use link status change interrrupt */ 1166 /* Use link status change interrupt */
1167 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); 1167 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1168 1168
1169 bcom_check_link(hw, port); 1169 bcom_check_link(hw, port);
@@ -1203,7 +1203,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1203 skge_write32(hw, B2_GP_IO, r); 1203 skge_write32(hw, B2_GP_IO, r);
1204 skge_read32(hw, B2_GP_IO); 1204 skge_read32(hw, B2_GP_IO);
1205 1205
1206 /* Enable GMII interfac */ 1206 /* Enable GMII interface */
1207 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); 1207 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1208 1208
1209 bcom_phy_init(skge, jumbo); 1209 bcom_phy_init(skge, jumbo);
@@ -1254,7 +1254,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
1254 * that jumbo frames larger than 8192 bytes will be 1254 * that jumbo frames larger than 8192 bytes will be
1255 * truncated. Disabling all bad frame filtering causes 1255 * truncated. Disabling all bad frame filtering causes
1256 * the RX FIFO to operate in streaming mode, in which 1256 * the RX FIFO to operate in streaming mode, in which
1257 * case the XMAC will start transfering frames out of the 1257 * case the XMAC will start transferring frames out of the
1258 * RX FIFO as soon as the FIFO threshold is reached. 1258 * RX FIFO as soon as the FIFO threshold is reached.
1259 */ 1259 */
1260 xm_write32(hw, port, XM_MODE, XM_DEF_MODE); 1260 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
@@ -1321,7 +1321,7 @@ static void genesis_stop(struct skge_port *skge)
1321 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); 1321 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1322 1322
1323 /* 1323 /*
1324 * If the transfer stucks at the MAC the STOP command will not 1324 * If the transfer sticks at the MAC the STOP command will not
1325 * terminate if we don't flush the XMAC's transmit FIFO ! 1325 * terminate if we don't flush the XMAC's transmit FIFO !
1326 */ 1326 */
1327 xm_write32(hw, port, XM_MODE, 1327 xm_write32(hw, port, XM_MODE,
@@ -1559,7 +1559,7 @@ static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1559 return v; 1559 return v;
1560} 1560}
1561 1561
1562/* Marvell Phy Initailization */ 1562/* Marvell Phy Initialization */
1563static void yukon_init(struct skge_hw *hw, int port) 1563static void yukon_init(struct skge_hw *hw, int port)
1564{ 1564{
1565 struct skge_port *skge = netdev_priv(hw->dev[port]); 1565 struct skge_port *skge = netdev_priv(hw->dev[port]);
@@ -2156,7 +2156,7 @@ static int skge_up(struct net_device *dev)
2156 hw->intr_mask |= portirqmask[port]; 2156 hw->intr_mask |= portirqmask[port];
2157 skge_write32(hw, B0_IMSK, hw->intr_mask); 2157 skge_write32(hw, B0_IMSK, hw->intr_mask);
2158 2158
2159 /* Initialze MAC */ 2159 /* Initialize MAC */
2160 spin_lock_bh(&hw->phy_lock); 2160 spin_lock_bh(&hw->phy_lock);
2161 if (hw->chip_id == CHIP_ID_GENESIS) 2161 if (hw->chip_id == CHIP_ID_GENESIS)
2162 genesis_mac_init(hw, port); 2162 genesis_mac_init(hw, port);
@@ -2476,7 +2476,7 @@ static void yukon_set_multicast(struct net_device *dev)
2476 reg = gma_read16(hw, port, GM_RX_CTRL); 2476 reg = gma_read16(hw, port, GM_RX_CTRL);
2477 reg |= GM_RXCR_UCF_ENA; 2477 reg |= GM_RXCR_UCF_ENA;
2478 2478
2479 if (dev->flags & IFF_PROMISC) /* promiscious */ 2479 if (dev->flags & IFF_PROMISC) /* promiscuous */
2480 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 2480 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2481 else if (dev->flags & IFF_ALLMULTI) /* all multicast */ 2481 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2482 memset(filter, 0xff, sizeof(filter)); 2482 memset(filter, 0xff, sizeof(filter));
@@ -2799,7 +2799,7 @@ static void skge_error_irq(struct skge_hw *hw)
2799} 2799}
2800 2800
2801/* 2801/*
2802 * Interrrupt from PHY are handled in tasklet (soft irq) 2802 * Interrupt from PHY are handled in tasklet (soft irq)
2803 * because accessing phy registers requires spin wait which might 2803 * because accessing phy registers requires spin wait which might
2804 * cause excess interrupt latency. 2804 * cause excess interrupt latency.
2805 */ 2805 */
@@ -3233,7 +3233,7 @@ static int __devinit skge_probe(struct pci_dev *pdev,
3233 } 3233 }
3234 3234
3235#ifdef __BIG_ENDIAN 3235#ifdef __BIG_ENDIAN
3236 /* byte swap decriptors in hardware */ 3236 /* byte swap descriptors in hardware */
3237 { 3237 {
3238 u32 reg; 3238 u32 reg;
3239 3239