diff options
author | Jeff Garzik <jgarzik@pobox.com> | 2005-09-21 22:34:08 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-09-21 22:34:08 -0400 |
commit | a3536c839f04682ed06c84a7f75968c27c6108c8 (patch) | |
tree | 92c26ea74c0ffb9b83a2285ad2539cc271b09856 /drivers/net/skge.c | |
parent | a33a1982012e9070736e3717231714dc9892303b (diff) | |
parent | efb0372bbaf5b829ff8c39db372779928af542a7 (diff) |
Merge /spare/repo/linux-2.6/
Diffstat (limited to 'drivers/net/skge.c')
-rw-r--r-- | drivers/net/skge.c | 98 |
1 files changed, 54 insertions, 44 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c index 757c83387a29..7ce734ec6ba8 100644 --- a/drivers/net/skge.c +++ b/drivers/net/skge.c | |||
@@ -42,7 +42,7 @@ | |||
42 | #include "skge.h" | 42 | #include "skge.h" |
43 | 43 | ||
44 | #define DRV_NAME "skge" | 44 | #define DRV_NAME "skge" |
45 | #define DRV_VERSION "0.9" | 45 | #define DRV_VERSION "1.0" |
46 | #define PFX DRV_NAME " " | 46 | #define PFX DRV_NAME " " |
47 | 47 | ||
48 | #define DEFAULT_TX_RING_SIZE 128 | 48 | #define DEFAULT_TX_RING_SIZE 128 |
@@ -669,7 +669,7 @@ static void skge_led(struct skge_port *skge, enum led_mode mode) | |||
669 | PHY_M_LED_BLINK_RT(BLINK_84MS) | | 669 | PHY_M_LED_BLINK_RT(BLINK_84MS) | |
670 | PHY_M_LEDC_TX_CTRL | | 670 | PHY_M_LEDC_TX_CTRL | |
671 | PHY_M_LEDC_DP_CTRL); | 671 | PHY_M_LEDC_DP_CTRL); |
672 | 672 | ||
673 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | 673 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
674 | PHY_M_LED_MO_RX(MO_LED_OFF) | | 674 | PHY_M_LED_MO_RX(MO_LED_OFF) | |
675 | (skge->speed == SPEED_100 ? | 675 | (skge->speed == SPEED_100 ? |
@@ -877,7 +877,7 @@ static int skge_rx_fill(struct skge_port *skge) | |||
877 | 877 | ||
878 | static void skge_link_up(struct skge_port *skge) | 878 | static void skge_link_up(struct skge_port *skge) |
879 | { | 879 | { |
880 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), | 880 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), |
881 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); | 881 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); |
882 | 882 | ||
883 | netif_carrier_on(skge->netdev); | 883 | netif_carrier_on(skge->netdev); |
@@ -988,6 +988,8 @@ static void genesis_reset(struct skge_hw *hw, int port) | |||
988 | { | 988 | { |
989 | const u8 zero[8] = { 0 }; | 989 | const u8 zero[8] = { 0 }; |
990 | 990 | ||
991 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | ||
992 | |||
991 | /* reset the statistics module */ | 993 | /* reset the statistics module */ |
992 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); | 994 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); |
993 | xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ | 995 | xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ |
@@ -1022,8 +1024,6 @@ static void bcom_check_link(struct skge_hw *hw, int port) | |||
1022 | (void) xm_phy_read(hw, port, PHY_BCOM_STAT); | 1024 | (void) xm_phy_read(hw, port, PHY_BCOM_STAT); |
1023 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); | 1025 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); |
1024 | 1026 | ||
1025 | pr_debug("bcom_check_link status=0x%x\n", status); | ||
1026 | |||
1027 | if ((status & PHY_ST_LSYNC) == 0) { | 1027 | if ((status & PHY_ST_LSYNC) == 0) { |
1028 | u16 cmd = xm_read16(hw, port, XM_MMU_CMD); | 1028 | u16 cmd = xm_read16(hw, port, XM_MMU_CMD); |
1029 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); | 1029 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); |
@@ -1107,8 +1107,6 @@ static void bcom_phy_init(struct skge_port *skge, int jumbo) | |||
1107 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, | 1107 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, |
1108 | }; | 1108 | }; |
1109 | 1109 | ||
1110 | pr_debug("bcom_phy_init\n"); | ||
1111 | |||
1112 | /* read Id from external PHY (all have the same address) */ | 1110 | /* read Id from external PHY (all have the same address) */ |
1113 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); | 1111 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); |
1114 | 1112 | ||
@@ -1341,6 +1339,8 @@ static void genesis_stop(struct skge_port *skge) | |||
1341 | int port = skge->port; | 1339 | int port = skge->port; |
1342 | u32 reg; | 1340 | u32 reg; |
1343 | 1341 | ||
1342 | genesis_reset(hw, port); | ||
1343 | |||
1344 | /* Clear Tx packet arbiter timeout IRQ */ | 1344 | /* Clear Tx packet arbiter timeout IRQ */ |
1345 | skge_write16(hw, B3_PA_CTRL, | 1345 | skge_write16(hw, B3_PA_CTRL, |
1346 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); | 1346 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); |
@@ -1466,7 +1466,6 @@ static void genesis_link_up(struct skge_port *skge) | |||
1466 | u16 cmd; | 1466 | u16 cmd; |
1467 | u32 mode, msk; | 1467 | u32 mode, msk; |
1468 | 1468 | ||
1469 | pr_debug("genesis_link_up\n"); | ||
1470 | cmd = xm_read16(hw, port, XM_MMU_CMD); | 1469 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
1471 | 1470 | ||
1472 | /* | 1471 | /* |
@@ -1579,7 +1578,6 @@ static void yukon_init(struct skge_hw *hw, int port) | |||
1579 | struct skge_port *skge = netdev_priv(hw->dev[port]); | 1578 | struct skge_port *skge = netdev_priv(hw->dev[port]); |
1580 | u16 ctrl, ct1000, adv; | 1579 | u16 ctrl, ct1000, adv; |
1581 | 1580 | ||
1582 | pr_debug("yukon_init\n"); | ||
1583 | if (skge->autoneg == AUTONEG_ENABLE) { | 1581 | if (skge->autoneg == AUTONEG_ENABLE) { |
1584 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); | 1582 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
1585 | 1583 | ||
@@ -1678,9 +1676,11 @@ static void yukon_mac_init(struct skge_hw *hw, int port) | |||
1678 | 1676 | ||
1679 | /* WA code for COMA mode -- set PHY reset */ | 1677 | /* WA code for COMA mode -- set PHY reset */ |
1680 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | 1678 | if (hw->chip_id == CHIP_ID_YUKON_LITE && |
1681 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) | 1679 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1682 | skge_write32(hw, B2_GP_IO, | 1680 | reg = skge_read32(hw, B2_GP_IO); |
1683 | (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9)); | 1681 | reg |= GP_DIR_9 | GP_IO_9; |
1682 | skge_write32(hw, B2_GP_IO, reg); | ||
1683 | } | ||
1684 | 1684 | ||
1685 | /* hard reset */ | 1685 | /* hard reset */ |
1686 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | 1686 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
@@ -1688,10 +1688,12 @@ static void yukon_mac_init(struct skge_hw *hw, int port) | |||
1688 | 1688 | ||
1689 | /* WA code for COMA mode -- clear PHY reset */ | 1689 | /* WA code for COMA mode -- clear PHY reset */ |
1690 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | 1690 | if (hw->chip_id == CHIP_ID_YUKON_LITE && |
1691 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) | 1691 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1692 | skge_write32(hw, B2_GP_IO, | 1692 | reg = skge_read32(hw, B2_GP_IO); |
1693 | (skge_read32(hw, B2_GP_IO) | GP_DIR_9) | 1693 | reg |= GP_DIR_9; |
1694 | & ~GP_IO_9); | 1694 | reg &= ~GP_IO_9; |
1695 | skge_write32(hw, B2_GP_IO, reg); | ||
1696 | } | ||
1695 | 1697 | ||
1696 | /* Set hardware config mode */ | 1698 | /* Set hardware config mode */ |
1697 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | | 1699 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | |
@@ -1730,7 +1732,7 @@ static void yukon_mac_init(struct skge_hw *hw, int port) | |||
1730 | } | 1732 | } |
1731 | 1733 | ||
1732 | gma_write16(hw, port, GM_GP_CTRL, reg); | 1734 | gma_write16(hw, port, GM_GP_CTRL, reg); |
1733 | skge_read16(hw, GMAC_IRQ_SRC); | 1735 | skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
1734 | 1736 | ||
1735 | yukon_init(hw, port); | 1737 | yukon_init(hw, port); |
1736 | 1738 | ||
@@ -1802,20 +1804,26 @@ static void yukon_stop(struct skge_port *skge) | |||
1802 | struct skge_hw *hw = skge->hw; | 1804 | struct skge_hw *hw = skge->hw; |
1803 | int port = skge->port; | 1805 | int port = skge->port; |
1804 | 1806 | ||
1805 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | 1807 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
1806 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { | 1808 | yukon_reset(hw, port); |
1807 | skge_write32(hw, B2_GP_IO, | ||
1808 | skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9); | ||
1809 | } | ||
1810 | 1809 | ||
1811 | gma_write16(hw, port, GM_GP_CTRL, | 1810 | gma_write16(hw, port, GM_GP_CTRL, |
1812 | gma_read16(hw, port, GM_GP_CTRL) | 1811 | gma_read16(hw, port, GM_GP_CTRL) |
1813 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); | 1812 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
1814 | gma_read16(hw, port, GM_GP_CTRL); | 1813 | gma_read16(hw, port, GM_GP_CTRL); |
1815 | 1814 | ||
1815 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | ||
1816 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { | ||
1817 | u32 io = skge_read32(hw, B2_GP_IO); | ||
1818 | |||
1819 | io |= GP_DIR_9 | GP_IO_9; | ||
1820 | skge_write32(hw, B2_GP_IO, io); | ||
1821 | skge_read32(hw, B2_GP_IO); | ||
1822 | } | ||
1823 | |||
1816 | /* set GPHY Control reset */ | 1824 | /* set GPHY Control reset */ |
1817 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | 1825 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1818 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | 1826 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1819 | } | 1827 | } |
1820 | 1828 | ||
1821 | static void yukon_get_stats(struct skge_port *skge, u64 *data) | 1829 | static void yukon_get_stats(struct skge_port *skge, u64 *data) |
@@ -1874,10 +1882,8 @@ static void yukon_link_up(struct skge_port *skge) | |||
1874 | int port = skge->port; | 1882 | int port = skge->port; |
1875 | u16 reg; | 1883 | u16 reg; |
1876 | 1884 | ||
1877 | pr_debug("yukon_link_up\n"); | ||
1878 | |||
1879 | /* Enable Transmit FIFO Underrun */ | 1885 | /* Enable Transmit FIFO Underrun */ |
1880 | skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK); | 1886 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
1881 | 1887 | ||
1882 | reg = gma_read16(hw, port, GM_GP_CTRL); | 1888 | reg = gma_read16(hw, port, GM_GP_CTRL); |
1883 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) | 1889 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) |
@@ -1897,7 +1903,6 @@ static void yukon_link_down(struct skge_port *skge) | |||
1897 | int port = skge->port; | 1903 | int port = skge->port; |
1898 | u16 ctrl; | 1904 | u16 ctrl; |
1899 | 1905 | ||
1900 | pr_debug("yukon_link_down\n"); | ||
1901 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | 1906 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); |
1902 | 1907 | ||
1903 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | 1908 | ctrl = gma_read16(hw, port, GM_GP_CTRL); |
@@ -2113,7 +2118,6 @@ static int skge_up(struct net_device *dev) | |||
2113 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); | 2118 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); |
2114 | skge_led(skge, LED_MODE_ON); | 2119 | skge_led(skge, LED_MODE_ON); |
2115 | 2120 | ||
2116 | pr_debug("skge_up completed\n"); | ||
2117 | return 0; | 2121 | return 0; |
2118 | 2122 | ||
2119 | free_rx_ring: | 2123 | free_rx_ring: |
@@ -2136,15 +2140,20 @@ static int skge_down(struct net_device *dev) | |||
2136 | 2140 | ||
2137 | netif_stop_queue(dev); | 2141 | netif_stop_queue(dev); |
2138 | 2142 | ||
2143 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); | ||
2144 | if (hw->chip_id == CHIP_ID_GENESIS) | ||
2145 | genesis_stop(skge); | ||
2146 | else | ||
2147 | yukon_stop(skge); | ||
2148 | |||
2149 | hw->intr_mask &= ~portirqmask[skge->port]; | ||
2150 | skge_write32(hw, B0_IMSK, hw->intr_mask); | ||
2151 | |||
2139 | /* Stop transmitter */ | 2152 | /* Stop transmitter */ |
2140 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); | 2153 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); |
2141 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | 2154 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), |
2142 | RB_RST_SET|RB_DIS_OP_MD); | 2155 | RB_RST_SET|RB_DIS_OP_MD); |
2143 | 2156 | ||
2144 | if (hw->chip_id == CHIP_ID_GENESIS) | ||
2145 | genesis_stop(skge); | ||
2146 | else | ||
2147 | yukon_stop(skge); | ||
2148 | 2157 | ||
2149 | /* Disable Force Sync bit and Enable Alloc bit */ | 2158 | /* Disable Force Sync bit and Enable Alloc bit */ |
2150 | skge_write8(hw, SK_REG(port, TXA_CTRL), | 2159 | skge_write8(hw, SK_REG(port, TXA_CTRL), |
@@ -2368,8 +2377,6 @@ static void genesis_set_multicast(struct net_device *dev) | |||
2368 | u32 mode; | 2377 | u32 mode; |
2369 | u8 filter[8]; | 2378 | u8 filter[8]; |
2370 | 2379 | ||
2371 | pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count); | ||
2372 | |||
2373 | mode = xm_read32(hw, port, XM_MODE); | 2380 | mode = xm_read32(hw, port, XM_MODE); |
2374 | mode |= XM_MD_ENA_HASH; | 2381 | mode |= XM_MD_ENA_HASH; |
2375 | if (dev->flags & IFF_PROMISC) | 2382 | if (dev->flags & IFF_PROMISC) |
@@ -2531,8 +2538,6 @@ static int skge_poll(struct net_device *dev, int *budget) | |||
2531 | unsigned int to_do = min(dev->quota, *budget); | 2538 | unsigned int to_do = min(dev->quota, *budget); |
2532 | unsigned int work_done = 0; | 2539 | unsigned int work_done = 0; |
2533 | 2540 | ||
2534 | pr_debug("skge_poll\n"); | ||
2535 | |||
2536 | for (e = ring->to_clean; work_done < to_do; e = e->next) { | 2541 | for (e = ring->to_clean; work_done < to_do; e = e->next) { |
2537 | struct skge_rx_desc *rd = e->desc; | 2542 | struct skge_rx_desc *rd = e->desc; |
2538 | struct sk_buff *skb; | 2543 | struct sk_buff *skb; |
@@ -2673,9 +2678,9 @@ static void skge_error_irq(struct skge_hw *hw) | |||
2673 | if (hw->chip_id == CHIP_ID_GENESIS) { | 2678 | if (hw->chip_id == CHIP_ID_GENESIS) { |
2674 | /* clear xmac errors */ | 2679 | /* clear xmac errors */ |
2675 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) | 2680 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) |
2676 | skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT); | 2681 | skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); |
2677 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) | 2682 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) |
2678 | skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT); | 2683 | skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); |
2679 | } else { | 2684 | } else { |
2680 | /* Timestamp (unused) overflow */ | 2685 | /* Timestamp (unused) overflow */ |
2681 | if (hwstatus & IS_IRQ_TIST_OV) | 2686 | if (hwstatus & IS_IRQ_TIST_OV) |
@@ -3001,9 +3006,6 @@ static int skge_reset(struct skge_hw *hw) | |||
3001 | 3006 | ||
3002 | skge_write32(hw, B0_IMSK, hw->intr_mask); | 3007 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
3003 | 3008 | ||
3004 | if (hw->chip_id != CHIP_ID_GENESIS) | ||
3005 | skge_write8(hw, GMAC_IRQ_MSK, 0); | ||
3006 | |||
3007 | spin_lock_bh(&hw->phy_lock); | 3009 | spin_lock_bh(&hw->phy_lock); |
3008 | for (i = 0; i < hw->ports; i++) { | 3010 | for (i = 0; i < hw->ports; i++) { |
3009 | if (hw->chip_id == CHIP_ID_GENESIS) | 3011 | if (hw->chip_id == CHIP_ID_GENESIS) |
@@ -3232,6 +3234,11 @@ static void __devexit skge_remove(struct pci_dev *pdev) | |||
3232 | dev0 = hw->dev[0]; | 3234 | dev0 = hw->dev[0]; |
3233 | unregister_netdev(dev0); | 3235 | unregister_netdev(dev0); |
3234 | 3236 | ||
3237 | skge_write32(hw, B0_IMSK, 0); | ||
3238 | skge_write16(hw, B0_LED, LED_STAT_OFF); | ||
3239 | skge_pci_clear(hw); | ||
3240 | skge_write8(hw, B0_CTST, CS_RST_SET); | ||
3241 | |||
3235 | tasklet_kill(&hw->ext_tasklet); | 3242 | tasklet_kill(&hw->ext_tasklet); |
3236 | 3243 | ||
3237 | free_irq(pdev->irq, hw); | 3244 | free_irq(pdev->irq, hw); |
@@ -3240,7 +3247,7 @@ static void __devexit skge_remove(struct pci_dev *pdev) | |||
3240 | if (dev1) | 3247 | if (dev1) |
3241 | free_netdev(dev1); | 3248 | free_netdev(dev1); |
3242 | free_netdev(dev0); | 3249 | free_netdev(dev0); |
3243 | skge_write16(hw, B0_LED, LED_STAT_OFF); | 3250 | |
3244 | iounmap(hw->regs); | 3251 | iounmap(hw->regs); |
3245 | kfree(hw); | 3252 | kfree(hw); |
3246 | pci_set_drvdata(pdev, NULL); | 3253 | pci_set_drvdata(pdev, NULL); |
@@ -3259,7 +3266,10 @@ static int skge_suspend(struct pci_dev *pdev, pm_message_t state) | |||
3259 | struct skge_port *skge = netdev_priv(dev); | 3266 | struct skge_port *skge = netdev_priv(dev); |
3260 | if (netif_running(dev)) { | 3267 | if (netif_running(dev)) { |
3261 | netif_carrier_off(dev); | 3268 | netif_carrier_off(dev); |
3262 | skge_down(dev); | 3269 | if (skge->wol) |
3270 | netif_stop_queue(dev); | ||
3271 | else | ||
3272 | skge_down(dev); | ||
3263 | } | 3273 | } |
3264 | netif_device_detach(dev); | 3274 | netif_device_detach(dev); |
3265 | wol |= skge->wol; | 3275 | wol |= skge->wol; |