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authorstephen hemminger <shemminger@vyatta.com>2011-07-06 15:00:07 -0400
committerDavid S. Miller <davem@davemloft.net>2011-07-07 03:30:04 -0400
commit57d6fa37f56ca594a1becaf5b8774382ddb7d720 (patch)
tree9cde9afc3a478357a1f356b2f22751c588a06a4b /drivers/net/skge.c
parentc074304c2bcf4b45e2b7ff86011beaa035ee52fd (diff)
skge: make support for old Genesis chips optional
The GENESIS boards are really old PCI-X boards that are rare. Marvell has dropped support for this hardware and there is no reason for most users to have to have this code. Rather than riddling code with ifdef's make one macro and let the compiler do the dead code elimination. This saves about 15% of the text size. Signed-off-by: Stephen Hemminger <shemminger@vyatta.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/skge.c')
-rw-r--r--drivers/net/skge.c79
1 files changed, 47 insertions, 32 deletions
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index e53e6a4e08a2..4495e2491495 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -85,6 +85,9 @@ MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
85static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = { 85static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */ 86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */ 87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
88#ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
90#endif
88 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */ 91 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
89 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */ 92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
90 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */ 93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
@@ -119,6 +122,15 @@ static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
119static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; 122static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
120static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 }; 123static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
121 124
125static inline bool is_genesis(const struct skge_hw *hw)
126{
127#ifdef CONFIG_SKGE_GENESIS
128 return hw->chip_id == CHIP_ID_GENESIS;
129#else
130 return false;
131#endif
132}
133
122static int skge_get_regs_len(struct net_device *dev) 134static int skge_get_regs_len(struct net_device *dev)
123{ 135{
124 return 0x4000; 136 return 0x4000;
@@ -146,7 +158,7 @@ static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
146/* Wake on Lan only supported on Yukon chips with rev 1 or above */ 158/* Wake on Lan only supported on Yukon chips with rev 1 or above */
147static u32 wol_supported(const struct skge_hw *hw) 159static u32 wol_supported(const struct skge_hw *hw)
148{ 160{
149 if (hw->chip_id == CHIP_ID_GENESIS) 161 if (is_genesis(hw))
150 return 0; 162 return 0;
151 163
152 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) 164 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
@@ -270,7 +282,7 @@ static u32 skge_supported_modes(const struct skge_hw *hw)
270 SUPPORTED_Autoneg | 282 SUPPORTED_Autoneg |
271 SUPPORTED_TP); 283 SUPPORTED_TP);
272 284
273 if (hw->chip_id == CHIP_ID_GENESIS) 285 if (is_genesis(hw))
274 supported &= ~(SUPPORTED_10baseT_Half | 286 supported &= ~(SUPPORTED_10baseT_Half |
275 SUPPORTED_10baseT_Full | 287 SUPPORTED_10baseT_Full |
276 SUPPORTED_100baseT_Half | 288 SUPPORTED_100baseT_Half |
@@ -433,7 +445,7 @@ static void skge_get_ethtool_stats(struct net_device *dev,
433{ 445{
434 struct skge_port *skge = netdev_priv(dev); 446 struct skge_port *skge = netdev_priv(dev);
435 447
436 if (skge->hw->chip_id == CHIP_ID_GENESIS) 448 if (is_genesis(skge->hw))
437 genesis_get_stats(skge, data); 449 genesis_get_stats(skge, data);
438 else 450 else
439 yukon_get_stats(skge, data); 451 yukon_get_stats(skge, data);
@@ -448,7 +460,7 @@ static struct net_device_stats *skge_get_stats(struct net_device *dev)
448 struct skge_port *skge = netdev_priv(dev); 460 struct skge_port *skge = netdev_priv(dev);
449 u64 data[ARRAY_SIZE(skge_stats)]; 461 u64 data[ARRAY_SIZE(skge_stats)];
450 462
451 if (skge->hw->chip_id == CHIP_ID_GENESIS) 463 if (is_genesis(skge->hw))
452 genesis_get_stats(skge, data); 464 genesis_get_stats(skge, data);
453 else 465 else
454 yukon_get_stats(skge, data); 466 yukon_get_stats(skge, data);
@@ -589,7 +601,7 @@ static int skge_set_pauseparam(struct net_device *dev,
589/* Chip internal frequency for clock calculations */ 601/* Chip internal frequency for clock calculations */
590static inline u32 hwkhz(const struct skge_hw *hw) 602static inline u32 hwkhz(const struct skge_hw *hw)
591{ 603{
592 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125; 604 return is_genesis(hw) ? 53125 : 78125;
593} 605}
594 606
595/* Chip HZ to microseconds */ 607/* Chip HZ to microseconds */
@@ -674,7 +686,7 @@ static void skge_led(struct skge_port *skge, enum led_mode mode)
674 int port = skge->port; 686 int port = skge->port;
675 687
676 spin_lock_bh(&hw->phy_lock); 688 spin_lock_bh(&hw->phy_lock);
677 if (hw->chip_id == CHIP_ID_GENESIS) { 689 if (is_genesis(hw)) {
678 switch (mode) { 690 switch (mode) {
679 case LED_MODE_OFF: 691 case LED_MODE_OFF:
680 if (hw->phy_type == SK_PHY_BCOM) 692 if (hw->phy_type == SK_PHY_BCOM)
@@ -1053,7 +1065,6 @@ static void skge_link_down(struct skge_port *skge)
1053 netif_info(skge, link, skge->netdev, "Link is down\n"); 1065 netif_info(skge, link, skge->netdev, "Link is down\n");
1054} 1066}
1055 1067
1056
1057static void xm_link_down(struct skge_hw *hw, int port) 1068static void xm_link_down(struct skge_hw *hw, int port)
1058{ 1069{
1059 struct net_device *dev = hw->dev[port]; 1070 struct net_device *dev = hw->dev[port];
@@ -1172,7 +1183,6 @@ static void genesis_reset(struct skge_hw *hw, int port)
1172 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF); 1183 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1173} 1184}
1174 1185
1175
1176/* Convert mode to MII values */ 1186/* Convert mode to MII values */
1177static const u16 phy_pause_map[] = { 1187static const u16 phy_pause_map[] = {
1178 [FLOW_MODE_NONE] = 0, 1188 [FLOW_MODE_NONE] = 0,
@@ -2405,7 +2415,7 @@ static void skge_phy_reset(struct skge_port *skge)
2405 netif_carrier_off(skge->netdev); 2415 netif_carrier_off(skge->netdev);
2406 2416
2407 spin_lock_bh(&hw->phy_lock); 2417 spin_lock_bh(&hw->phy_lock);
2408 if (hw->chip_id == CHIP_ID_GENESIS) { 2418 if (is_genesis(hw)) {
2409 genesis_reset(hw, port); 2419 genesis_reset(hw, port);
2410 genesis_mac_init(hw, port); 2420 genesis_mac_init(hw, port);
2411 } else { 2421 } else {
@@ -2436,7 +2446,8 @@ static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2436 case SIOCGMIIREG: { 2446 case SIOCGMIIREG: {
2437 u16 val = 0; 2447 u16 val = 0;
2438 spin_lock_bh(&hw->phy_lock); 2448 spin_lock_bh(&hw->phy_lock);
2439 if (hw->chip_id == CHIP_ID_GENESIS) 2449
2450 if (is_genesis(hw))
2440 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2451 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2441 else 2452 else
2442 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); 2453 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
@@ -2447,7 +2458,7 @@ static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2447 2458
2448 case SIOCSMIIREG: 2459 case SIOCSMIIREG:
2449 spin_lock_bh(&hw->phy_lock); 2460 spin_lock_bh(&hw->phy_lock);
2450 if (hw->chip_id == CHIP_ID_GENESIS) 2461 if (is_genesis(hw))
2451 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, 2462 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2452 data->val_in); 2463 data->val_in);
2453 else 2464 else
@@ -2559,7 +2570,7 @@ static int skge_up(struct net_device *dev)
2559 2570
2560 /* Initialize MAC */ 2571 /* Initialize MAC */
2561 spin_lock_bh(&hw->phy_lock); 2572 spin_lock_bh(&hw->phy_lock);
2562 if (hw->chip_id == CHIP_ID_GENESIS) 2573 if (is_genesis(hw))
2563 genesis_mac_init(hw, port); 2574 genesis_mac_init(hw, port);
2564 else 2575 else
2565 yukon_mac_init(hw, port); 2576 yukon_mac_init(hw, port);
@@ -2621,7 +2632,7 @@ static int skge_down(struct net_device *dev)
2621 2632
2622 netif_tx_disable(dev); 2633 netif_tx_disable(dev);
2623 2634
2624 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC) 2635 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2625 del_timer_sync(&skge->link_timer); 2636 del_timer_sync(&skge->link_timer);
2626 2637
2627 napi_disable(&skge->napi); 2638 napi_disable(&skge->napi);
@@ -2633,7 +2644,7 @@ static int skge_down(struct net_device *dev)
2633 spin_unlock_irq(&hw->hw_lock); 2644 spin_unlock_irq(&hw->hw_lock);
2634 2645
2635 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); 2646 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2636 if (hw->chip_id == CHIP_ID_GENESIS) 2647 if (is_genesis(hw))
2637 genesis_stop(skge); 2648 genesis_stop(skge);
2638 else 2649 else
2639 yukon_stop(skge); 2650 yukon_stop(skge);
@@ -2661,7 +2672,7 @@ static int skge_down(struct net_device *dev)
2661 2672
2662 skge_rx_stop(hw, port); 2673 skge_rx_stop(hw, port);
2663 2674
2664 if (hw->chip_id == CHIP_ID_GENESIS) { 2675 if (is_genesis(hw)) {
2665 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); 2676 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2666 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); 2677 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2667 } else { 2678 } else {
@@ -2957,7 +2968,7 @@ static void yukon_set_multicast(struct net_device *dev)
2957 2968
2958static inline u16 phy_length(const struct skge_hw *hw, u32 status) 2969static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2959{ 2970{
2960 if (hw->chip_id == CHIP_ID_GENESIS) 2971 if (is_genesis(hw))
2961 return status >> XMR_FS_LEN_SHIFT; 2972 return status >> XMR_FS_LEN_SHIFT;
2962 else 2973 else
2963 return status >> GMR_FS_LEN_SHIFT; 2974 return status >> GMR_FS_LEN_SHIFT;
@@ -2965,7 +2976,7 @@ static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2965 2976
2966static inline int bad_phy_status(const struct skge_hw *hw, u32 status) 2977static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2967{ 2978{
2968 if (hw->chip_id == CHIP_ID_GENESIS) 2979 if (is_genesis(hw))
2969 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; 2980 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2970 else 2981 else
2971 return (status & GMR_FS_ANY_ERR) || 2982 return (status & GMR_FS_ANY_ERR) ||
@@ -2975,9 +2986,8 @@ static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2975static void skge_set_multicast(struct net_device *dev) 2986static void skge_set_multicast(struct net_device *dev)
2976{ 2987{
2977 struct skge_port *skge = netdev_priv(dev); 2988 struct skge_port *skge = netdev_priv(dev);
2978 struct skge_hw *hw = skge->hw;
2979 2989
2980 if (hw->chip_id == CHIP_ID_GENESIS) 2990 if (is_genesis(skge->hw))
2981 genesis_set_multicast(dev); 2991 genesis_set_multicast(dev);
2982 else 2992 else
2983 yukon_set_multicast(dev); 2993 yukon_set_multicast(dev);
@@ -3057,7 +3067,7 @@ error:
3057 "rx err, slot %td control 0x%x status 0x%x\n", 3067 "rx err, slot %td control 0x%x status 0x%x\n",
3058 e - skge->rx_ring.start, control, status); 3068 e - skge->rx_ring.start, control, status);
3059 3069
3060 if (skge->hw->chip_id == CHIP_ID_GENESIS) { 3070 if (is_genesis(skge->hw)) {
3061 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) 3071 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3062 dev->stats.rx_length_errors++; 3072 dev->stats.rx_length_errors++;
3063 if (status & XMR_FS_FRA_ERR) 3073 if (status & XMR_FS_FRA_ERR)
@@ -3171,7 +3181,7 @@ static void skge_mac_parity(struct skge_hw *hw, int port)
3171 3181
3172 ++dev->stats.tx_heartbeat_errors; 3182 ++dev->stats.tx_heartbeat_errors;
3173 3183
3174 if (hw->chip_id == CHIP_ID_GENESIS) 3184 if (is_genesis(hw))
3175 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), 3185 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3176 MFF_CLR_PERR); 3186 MFF_CLR_PERR);
3177 else 3187 else
@@ -3183,7 +3193,7 @@ static void skge_mac_parity(struct skge_hw *hw, int port)
3183 3193
3184static void skge_mac_intr(struct skge_hw *hw, int port) 3194static void skge_mac_intr(struct skge_hw *hw, int port)
3185{ 3195{
3186 if (hw->chip_id == CHIP_ID_GENESIS) 3196 if (is_genesis(hw))
3187 genesis_mac_intr(hw, port); 3197 genesis_mac_intr(hw, port);
3188 else 3198 else
3189 yukon_mac_intr(hw, port); 3199 yukon_mac_intr(hw, port);
@@ -3195,7 +3205,7 @@ static void skge_error_irq(struct skge_hw *hw)
3195 struct pci_dev *pdev = hw->pdev; 3205 struct pci_dev *pdev = hw->pdev;
3196 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); 3206 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3197 3207
3198 if (hw->chip_id == CHIP_ID_GENESIS) { 3208 if (is_genesis(hw)) {
3199 /* clear xmac errors */ 3209 /* clear xmac errors */
3200 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) 3210 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3201 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); 3211 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
@@ -3278,7 +3288,7 @@ static void skge_extirq(unsigned long arg)
3278 struct skge_port *skge = netdev_priv(dev); 3288 struct skge_port *skge = netdev_priv(dev);
3279 3289
3280 spin_lock(&hw->phy_lock); 3290 spin_lock(&hw->phy_lock);
3281 if (hw->chip_id != CHIP_ID_GENESIS) 3291 if (!is_genesis(hw))
3282 yukon_phy_intr(skge); 3292 yukon_phy_intr(skge);
3283 else if (hw->phy_type == SK_PHY_BCOM) 3293 else if (hw->phy_type == SK_PHY_BCOM)
3284 bcom_phy_intr(skge); 3294 bcom_phy_intr(skge);
@@ -3397,7 +3407,7 @@ static int skge_set_mac_address(struct net_device *dev, void *p)
3397 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN); 3407 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3398 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN); 3408 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3399 3409
3400 if (hw->chip_id == CHIP_ID_GENESIS) 3410 if (is_genesis(hw))
3401 xm_outaddr(hw, port, XM_SA, dev->dev_addr); 3411 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3402 else { 3412 else {
3403 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); 3413 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
@@ -3473,6 +3483,7 @@ static int skge_reset(struct skge_hw *hw)
3473 3483
3474 switch (hw->chip_id) { 3484 switch (hw->chip_id) {
3475 case CHIP_ID_GENESIS: 3485 case CHIP_ID_GENESIS:
3486#ifdef CONFIG_SKGE_GENESIS
3476 switch (hw->phy_type) { 3487 switch (hw->phy_type) {
3477 case SK_PHY_XMAC: 3488 case SK_PHY_XMAC:
3478 hw->phy_addr = PHY_ADDR_XMAC; 3489 hw->phy_addr = PHY_ADDR_XMAC;
@@ -3486,6 +3497,10 @@ static int skge_reset(struct skge_hw *hw)
3486 return -EOPNOTSUPP; 3497 return -EOPNOTSUPP;
3487 } 3498 }
3488 break; 3499 break;
3500#else
3501 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3502 return -EOPNOTSUPP;
3503#endif
3489 3504
3490 case CHIP_ID_YUKON: 3505 case CHIP_ID_YUKON:
3491 case CHIP_ID_YUKON_LITE: 3506 case CHIP_ID_YUKON_LITE:
@@ -3508,7 +3523,7 @@ static int skge_reset(struct skge_hw *hw)
3508 3523
3509 /* read the adapters RAM size */ 3524 /* read the adapters RAM size */
3510 t8 = skge_read8(hw, B2_E_0); 3525 t8 = skge_read8(hw, B2_E_0);
3511 if (hw->chip_id == CHIP_ID_GENESIS) { 3526 if (is_genesis(hw)) {
3512 if (t8 == 3) { 3527 if (t8 == 3) {
3513 /* special case: 4 x 64k x 36, offset = 0x80000 */ 3528 /* special case: 4 x 64k x 36, offset = 0x80000 */
3514 hw->ram_size = 0x100000; 3529 hw->ram_size = 0x100000;
@@ -3523,10 +3538,10 @@ static int skge_reset(struct skge_hw *hw)
3523 hw->intr_mask = IS_HW_ERR; 3538 hw->intr_mask = IS_HW_ERR;
3524 3539
3525 /* Use PHY IRQ for all but fiber based Genesis board */ 3540 /* Use PHY IRQ for all but fiber based Genesis board */
3526 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)) 3541 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3527 hw->intr_mask |= IS_EXT_REG; 3542 hw->intr_mask |= IS_EXT_REG;
3528 3543
3529 if (hw->chip_id == CHIP_ID_GENESIS) 3544 if (is_genesis(hw))
3530 genesis_init(hw); 3545 genesis_init(hw);
3531 else { 3546 else {
3532 /* switch power to VCC (WA for VAUX problem) */ 3547 /* switch power to VCC (WA for VAUX problem) */
@@ -3591,7 +3606,7 @@ static int skge_reset(struct skge_hw *hw)
3591 skge_write32(hw, B0_IMSK, hw->intr_mask); 3606 skge_write32(hw, B0_IMSK, hw->intr_mask);
3592 3607
3593 for (i = 0; i < hw->ports; i++) { 3608 for (i = 0; i < hw->ports; i++) {
3594 if (hw->chip_id == CHIP_ID_GENESIS) 3609 if (is_genesis(hw))
3595 genesis_reset(hw, i); 3610 genesis_reset(hw, i);
3596 else 3611 else
3597 yukon_reset(hw, i); 3612 yukon_reset(hw, i);
@@ -3802,9 +3817,9 @@ static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3802 skge->port = port; 3817 skge->port = port;
3803 3818
3804 /* Only used for Genesis XMAC */ 3819 /* Only used for Genesis XMAC */
3805 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge); 3820 if (is_genesis(hw))
3806 3821 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3807 if (hw->chip_id != CHIP_ID_GENESIS) { 3822 else {
3808 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 3823 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3809 NETIF_F_RXCSUM; 3824 NETIF_F_RXCSUM;
3810 dev->features |= dev->hw_features; 3825 dev->features |= dev->hw_features;