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authorJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-07-31 03:06:29 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2011-08-27 03:58:13 -0400
commit33f810b2036f13f1b123062a9e5c1794d400ce81 (patch)
tree370b55026f4bd856e96842f86af631ca2bab3da2 /drivers/net/skfp
parent3cd0999d134235d64b175edd2eb1d46ebc97b377 (diff)
fddi: Move the FDDI drivers
Move the FDDI drivers into drivers/net/fddi/ and make the necessary Kconfig and Makefile changes. CC: "Maciej W. Rozycki" <macro@linux-mips.org> CC: Christoph Goos <cgoos@syskonnect.de> CC: <linux@syskonnect.de> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/skfp')
-rw-r--r--drivers/net/skfp/Makefile20
-rw-r--r--drivers/net/skfp/cfm.c627
-rw-r--r--drivers/net/skfp/drvfbi.c584
-rw-r--r--drivers/net/skfp/ecm.c536
-rw-r--r--drivers/net/skfp/ess.c720
-rw-r--r--drivers/net/skfp/fplustm.c1491
-rw-r--r--drivers/net/skfp/h/cmtdef.h756
-rw-r--r--drivers/net/skfp/h/fddi.h69
-rw-r--r--drivers/net/skfp/h/fddimib.h349
-rw-r--r--drivers/net/skfp/h/fplustm.h274
-rw-r--r--drivers/net/skfp/h/hwmtm.h399
-rw-r--r--drivers/net/skfp/h/mbuf.h50
-rw-r--r--drivers/net/skfp/h/osdef1st.h125
-rw-r--r--drivers/net/skfp/h/sba.h142
-rw-r--r--drivers/net/skfp/h/sba_def.h76
-rw-r--r--drivers/net/skfp/h/skfbi.h1133
-rw-r--r--drivers/net/skfp/h/skfbiinc.h97
-rw-r--r--drivers/net/skfp/h/smc.h488
-rw-r--r--drivers/net/skfp/h/smt.h882
-rw-r--r--drivers/net/skfp/h/smt_p.h326
-rw-r--r--drivers/net/skfp/h/smtstate.h106
-rw-r--r--drivers/net/skfp/h/supern_2.h1059
-rw-r--r--drivers/net/skfp/h/targethw.h138
-rw-r--r--drivers/net/skfp/h/targetos.h165
-rw-r--r--drivers/net/skfp/h/types.h39
-rw-r--r--drivers/net/skfp/hwmtm.c2178
-rw-r--r--drivers/net/skfp/hwt.c269
-rw-r--r--drivers/net/skfp/pcmplc.c2014
-rw-r--r--drivers/net/skfp/pmf.c1663
-rw-r--r--drivers/net/skfp/queue.c173
-rw-r--r--drivers/net/skfp/rmt.c654
-rw-r--r--drivers/net/skfp/skfddi.c2260
-rw-r--r--drivers/net/skfp/smt.c2046
-rw-r--r--drivers/net/skfp/smtdef.c355
-rw-r--r--drivers/net/skfp/smtinit.c125
-rw-r--r--drivers/net/skfp/smttimer.c156
-rw-r--r--drivers/net/skfp/srf.c429
37 files changed, 0 insertions, 22973 deletions
diff --git a/drivers/net/skfp/Makefile b/drivers/net/skfp/Makefile
deleted file mode 100644
index b0be0234abf6..000000000000
--- a/drivers/net/skfp/Makefile
+++ /dev/null
@@ -1,20 +0,0 @@
1#
2# Makefile for the SysKonnect FDDI PCI adapter driver
3#
4
5obj-$(CONFIG_SKFP) += skfp.o
6
7skfp-objs := skfddi.o hwmtm.o fplustm.o smt.o cfm.o \
8 ecm.o pcmplc.o pmf.o queue.o rmt.o \
9 smtdef.o smtinit.o smttimer.o srf.o hwt.o \
10 drvfbi.o ess.o
11
12# NOTE:
13# Compiling this driver produces some warnings (and some more are
14# switched off below), but I did not fix this, because the Hardware
15# Module source (see skfddi.c for details) is used for different
16# drivers, and fixing it for Linux might bring problems on other
17# projects. To keep the source common for all those drivers (and
18# thus simplify fixes to it), please do not clean it up!
19
20ccflags-y := -Idrivers/net/skfp -DPCI -DMEM_MAPPED_IO -Wno-strict-prototypes
diff --git a/drivers/net/skfp/cfm.c b/drivers/net/skfp/cfm.c
deleted file mode 100644
index e395ace3120b..000000000000
--- a/drivers/net/skfp/cfm.c
+++ /dev/null
@@ -1,627 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 SMT CFM
19 Configuration Management
20 DAS with single MAC
21*/
22
23/*
24 * Hardware independent state machine implemantation
25 * The following external SMT functions are referenced :
26 *
27 * queue_event()
28 *
29 * The following external HW dependent functions are referenced :
30 * config_mux()
31 *
32 * The following HW dependent events are required :
33 * NONE
34 */
35
36#include "h/types.h"
37#include "h/fddi.h"
38#include "h/smc.h"
39
40#define KERNEL
41#include "h/smtstate.h"
42
43#ifndef lint
44static const char ID_sccs[] = "@(#)cfm.c 2.18 98/10/06 (C) SK " ;
45#endif
46
47/*
48 * FSM Macros
49 */
50#define AFLAG 0x10
51#define GO_STATE(x) (smc->mib.fddiSMTCF_State = (x)|AFLAG)
52#define ACTIONS_DONE() (smc->mib.fddiSMTCF_State &= ~AFLAG)
53#define ACTIONS(x) (x|AFLAG)
54
55#ifdef DEBUG
56/*
57 * symbolic state names
58 */
59static const char * const cfm_states[] = {
60 "SC0_ISOLATED","CF1","CF2","CF3","CF4",
61 "SC1_WRAP_A","SC2_WRAP_B","SC5_TRHU_B","SC7_WRAP_S",
62 "SC9_C_WRAP_A","SC10_C_WRAP_B","SC11_C_WRAP_S","SC4_THRU_A"
63} ;
64
65/*
66 * symbolic event names
67 */
68static const char * const cfm_events[] = {
69 "NONE","CF_LOOP_A","CF_LOOP_B","CF_JOIN_A","CF_JOIN_B"
70} ;
71#endif
72
73/*
74 * map from state to downstream port type
75 */
76static const unsigned char cf_to_ptype[] = {
77 TNONE,TNONE,TNONE,TNONE,TNONE,
78 TNONE,TB,TB,TS,
79 TA,TB,TS,TB
80} ;
81
82/*
83 * CEM port states
84 */
85#define CEM_PST_DOWN 0
86#define CEM_PST_UP 1
87#define CEM_PST_HOLD 2
88/* define portstate array only for A and B port */
89/* Do this within the smc structure (use in multiple cards) */
90
91/*
92 * all Globals are defined in smc.h
93 * struct s_cfm
94 */
95
96/*
97 * function declarations
98 */
99static void cfm_fsm(struct s_smc *smc, int cmd);
100
101/*
102 init CFM state machine
103 clear all CFM vars and flags
104*/
105void cfm_init(struct s_smc *smc)
106{
107 smc->mib.fddiSMTCF_State = ACTIONS(SC0_ISOLATED) ;
108 smc->r.rm_join = 0 ;
109 smc->r.rm_loop = 0 ;
110 smc->y[PA].scrub = 0 ;
111 smc->y[PB].scrub = 0 ;
112 smc->y[PA].cem_pst = CEM_PST_DOWN ;
113 smc->y[PB].cem_pst = CEM_PST_DOWN ;
114}
115
116/* Some terms conditions used by the selection criteria */
117#define THRU_ENABLED(smc) (smc->y[PA].pc_mode != PM_TREE && \
118 smc->y[PB].pc_mode != PM_TREE)
119/* Selection criteria for the ports */
120static void selection_criteria (struct s_smc *smc, struct s_phy *phy)
121{
122
123 switch (phy->mib->fddiPORTMy_Type) {
124 case TA:
125 if ( !THRU_ENABLED(smc) && smc->y[PB].cf_join ) {
126 phy->wc_flag = TRUE ;
127 } else {
128 phy->wc_flag = FALSE ;
129 }
130
131 break;
132 case TB:
133 /* take precedence over PA */
134 phy->wc_flag = FALSE ;
135 break;
136 case TS:
137 phy->wc_flag = FALSE ;
138 break;
139 case TM:
140 phy->wc_flag = FALSE ;
141 break;
142 }
143
144}
145
146void all_selection_criteria(struct s_smc *smc)
147{
148 struct s_phy *phy ;
149 int p ;
150
151 for ( p = 0,phy = smc->y ; p < NUMPHYS; p++, phy++ ) {
152 /* Do the selection criteria */
153 selection_criteria (smc,phy);
154 }
155}
156
157static void cem_priv_state(struct s_smc *smc, int event)
158/* State machine for private PORT states: used to optimize dual homing */
159{
160 int np; /* Number of the port */
161 int i;
162
163 /* Do this only in a DAS */
164 if (smc->s.sas != SMT_DAS )
165 return ;
166
167 np = event - CF_JOIN;
168
169 if (np != PA && np != PB) {
170 return ;
171 }
172 /* Change the port state according to the event (portnumber) */
173 if (smc->y[np].cf_join) {
174 smc->y[np].cem_pst = CEM_PST_UP ;
175 } else if (!smc->y[np].wc_flag) {
176 /* set the port to done only if it is not withheld */
177 smc->y[np].cem_pst = CEM_PST_DOWN ;
178 }
179
180 /* Don't set an hold port to down */
181
182 /* Check all ports of restart conditions */
183 for (i = 0 ; i < 2 ; i ++ ) {
184 /* Check all port for PORT is on hold and no withhold is done */
185 if ( smc->y[i].cem_pst == CEM_PST_HOLD && !smc->y[i].wc_flag ) {
186 smc->y[i].cem_pst = CEM_PST_DOWN;
187 queue_event(smc,(int)(EVENT_PCM+i),PC_START) ;
188 }
189 if ( smc->y[i].cem_pst == CEM_PST_UP && smc->y[i].wc_flag ) {
190 smc->y[i].cem_pst = CEM_PST_HOLD;
191 queue_event(smc,(int)(EVENT_PCM+i),PC_START) ;
192 }
193 if ( smc->y[i].cem_pst == CEM_PST_DOWN && smc->y[i].wc_flag ) {
194 /*
195 * The port must be restarted when the wc_flag
196 * will be reset. So set the port on hold.
197 */
198 smc->y[i].cem_pst = CEM_PST_HOLD;
199 }
200 }
201 return ;
202}
203
204/*
205 CFM state machine
206 called by dispatcher
207
208 do
209 display state change
210 process event
211 until SM is stable
212*/
213void cfm(struct s_smc *smc, int event)
214{
215 int state ; /* remember last state */
216 int cond ;
217 int oldstate ;
218
219 /* We will do the following: */
220 /* - compute the variable WC_Flag for every port (This is where */
221 /* we can extend the requested path checking !!) */
222 /* - do the old (SMT 6.2 like) state machine */
223 /* - do the resulting station states */
224
225 all_selection_criteria (smc);
226
227 /* We will check now whether a state transition is allowed or not */
228 /* - change the portstates */
229 cem_priv_state (smc, event);
230
231 oldstate = smc->mib.fddiSMTCF_State ;
232 do {
233 DB_CFM("CFM : state %s%s",
234 (smc->mib.fddiSMTCF_State & AFLAG) ? "ACTIONS " : "",
235 cfm_states[smc->mib.fddiSMTCF_State & ~AFLAG]) ;
236 DB_CFM(" event %s\n",cfm_events[event],0) ;
237 state = smc->mib.fddiSMTCF_State ;
238 cfm_fsm(smc,event) ;
239 event = 0 ;
240 } while (state != smc->mib.fddiSMTCF_State) ;
241
242#ifndef SLIM_SMT
243 /*
244 * check peer wrap condition
245 */
246 cond = FALSE ;
247 if ( (smc->mib.fddiSMTCF_State == SC9_C_WRAP_A &&
248 smc->y[PA].pc_mode == PM_PEER) ||
249 (smc->mib.fddiSMTCF_State == SC10_C_WRAP_B &&
250 smc->y[PB].pc_mode == PM_PEER) ||
251 (smc->mib.fddiSMTCF_State == SC11_C_WRAP_S &&
252 smc->y[PS].pc_mode == PM_PEER &&
253 smc->y[PS].mib->fddiPORTNeighborType != TS ) ) {
254 cond = TRUE ;
255 }
256 if (cond != smc->mib.fddiSMTPeerWrapFlag)
257 smt_srf_event(smc,SMT_COND_SMT_PEER_WRAP,0,cond) ;
258
259#if 0
260 /*
261 * Don't send ever MAC_PATH_CHANGE events. Our MAC is hard-wired
262 * to the primary path.
263 */
264 /*
265 * path change
266 */
267 if (smc->mib.fddiSMTCF_State != oldstate) {
268 smt_srf_event(smc,SMT_EVENT_MAC_PATH_CHANGE,INDEX_MAC,0) ;
269 }
270#endif
271#endif /* no SLIM_SMT */
272
273 /*
274 * set MAC port type
275 */
276 smc->mib.m[MAC0].fddiMACDownstreamPORTType =
277 cf_to_ptype[smc->mib.fddiSMTCF_State] ;
278 cfm_state_change(smc,(int)smc->mib.fddiSMTCF_State) ;
279}
280
281/*
282 process CFM event
283*/
284/*ARGSUSED1*/
285static void cfm_fsm(struct s_smc *smc, int cmd)
286{
287 switch(smc->mib.fddiSMTCF_State) {
288 case ACTIONS(SC0_ISOLATED) :
289 smc->mib.p[PA].fddiPORTCurrentPath = MIB_PATH_ISOLATED ;
290 smc->mib.p[PB].fddiPORTCurrentPath = MIB_PATH_ISOLATED ;
291 smc->mib.p[PA].fddiPORTMACPlacement = 0 ;
292 smc->mib.p[PB].fddiPORTMACPlacement = 0 ;
293 smc->mib.fddiSMTStationStatus = MIB_SMT_STASTA_SEPA ;
294 config_mux(smc,MUX_ISOLATE) ; /* configure PHY Mux */
295 smc->r.rm_loop = FALSE ;
296 smc->r.rm_join = FALSE ;
297 queue_event(smc,EVENT_RMT,RM_JOIN) ;/* signal RMT */
298 /* Don't do the WC-Flag changing here */
299 ACTIONS_DONE() ;
300 DB_CFMN(1,"CFM : %s\n",cfm_states[smc->mib.fddiSMTCF_State],0) ;
301 break;
302 case SC0_ISOLATED :
303 /*SC07*/
304 /*SAS port can be PA or PB ! */
305 if (smc->s.sas && (smc->y[PA].cf_join || smc->y[PA].cf_loop ||
306 smc->y[PB].cf_join || smc->y[PB].cf_loop)) {
307 GO_STATE(SC11_C_WRAP_S) ;
308 break ;
309 }
310 /*SC01*/
311 if ((smc->y[PA].cem_pst == CEM_PST_UP && smc->y[PA].cf_join &&
312 !smc->y[PA].wc_flag) || smc->y[PA].cf_loop) {
313 GO_STATE(SC9_C_WRAP_A) ;
314 break ;
315 }
316 /*SC02*/
317 if ((smc->y[PB].cem_pst == CEM_PST_UP && smc->y[PB].cf_join &&
318 !smc->y[PB].wc_flag) || smc->y[PB].cf_loop) {
319 GO_STATE(SC10_C_WRAP_B) ;
320 break ;
321 }
322 break ;
323 case ACTIONS(SC9_C_WRAP_A) :
324 smc->mib.p[PA].fddiPORTCurrentPath = MIB_PATH_CONCATENATED ;
325 smc->mib.p[PB].fddiPORTCurrentPath = MIB_PATH_ISOLATED ;
326 smc->mib.p[PA].fddiPORTMACPlacement = INDEX_MAC ;
327 smc->mib.p[PB].fddiPORTMACPlacement = 0 ;
328 smc->mib.fddiSMTStationStatus = MIB_SMT_STASTA_CON ;
329 config_mux(smc,MUX_WRAPA) ; /* configure PHY mux */
330 if (smc->y[PA].cf_loop) {
331 smc->r.rm_join = FALSE ;
332 smc->r.rm_loop = TRUE ;
333 queue_event(smc,EVENT_RMT,RM_LOOP) ;/* signal RMT */
334 }
335 if (smc->y[PA].cf_join) {
336 smc->r.rm_loop = FALSE ;
337 smc->r.rm_join = TRUE ;
338 queue_event(smc,EVENT_RMT,RM_JOIN) ;/* signal RMT */
339 }
340 ACTIONS_DONE() ;
341 DB_CFMN(1,"CFM : %s\n",cfm_states[smc->mib.fddiSMTCF_State],0) ;
342 break ;
343 case SC9_C_WRAP_A :
344 /*SC10*/
345 if ( (smc->y[PA].wc_flag || !smc->y[PA].cf_join) &&
346 !smc->y[PA].cf_loop ) {
347 GO_STATE(SC0_ISOLATED) ;
348 break ;
349 }
350 /*SC12*/
351 else if ( (smc->y[PB].cf_loop && smc->y[PA].cf_join &&
352 smc->y[PA].cem_pst == CEM_PST_UP) ||
353 ((smc->y[PB].cf_loop ||
354 (smc->y[PB].cf_join &&
355 smc->y[PB].cem_pst == CEM_PST_UP)) &&
356 (smc->y[PA].pc_mode == PM_TREE ||
357 smc->y[PB].pc_mode == PM_TREE))) {
358 smc->y[PA].scrub = TRUE ;
359 GO_STATE(SC10_C_WRAP_B) ;
360 break ;
361 }
362 /*SC14*/
363 else if (!smc->s.attach_s &&
364 smc->y[PA].cf_join &&
365 smc->y[PA].cem_pst == CEM_PST_UP &&
366 smc->y[PA].pc_mode == PM_PEER && smc->y[PB].cf_join &&
367 smc->y[PB].cem_pst == CEM_PST_UP &&
368 smc->y[PB].pc_mode == PM_PEER) {
369 smc->y[PA].scrub = TRUE ;
370 smc->y[PB].scrub = TRUE ;
371 GO_STATE(SC4_THRU_A) ;
372 break ;
373 }
374 /*SC15*/
375 else if ( smc->s.attach_s &&
376 smc->y[PA].cf_join &&
377 smc->y[PA].cem_pst == CEM_PST_UP &&
378 smc->y[PA].pc_mode == PM_PEER &&
379 smc->y[PB].cf_join &&
380 smc->y[PB].cem_pst == CEM_PST_UP &&
381 smc->y[PB].pc_mode == PM_PEER) {
382 smc->y[PA].scrub = TRUE ;
383 smc->y[PB].scrub = TRUE ;
384 GO_STATE(SC5_THRU_B) ;
385 break ;
386 }
387 break ;
388 case ACTIONS(SC10_C_WRAP_B) :
389 smc->mib.p[PA].fddiPORTCurrentPath = MIB_PATH_ISOLATED ;
390 smc->mib.p[PB].fddiPORTCurrentPath = MIB_PATH_CONCATENATED ;
391 smc->mib.p[PA].fddiPORTMACPlacement = 0 ;
392 smc->mib.p[PB].fddiPORTMACPlacement = INDEX_MAC ;
393 smc->mib.fddiSMTStationStatus = MIB_SMT_STASTA_CON ;
394 config_mux(smc,MUX_WRAPB) ; /* configure PHY mux */
395 if (smc->y[PB].cf_loop) {
396 smc->r.rm_join = FALSE ;
397 smc->r.rm_loop = TRUE ;
398 queue_event(smc,EVENT_RMT,RM_LOOP) ;/* signal RMT */
399 }
400 if (smc->y[PB].cf_join) {
401 smc->r.rm_loop = FALSE ;
402 smc->r.rm_join = TRUE ;
403 queue_event(smc,EVENT_RMT,RM_JOIN) ;/* signal RMT */
404 }
405 ACTIONS_DONE() ;
406 DB_CFMN(1,"CFM : %s\n",cfm_states[smc->mib.fddiSMTCF_State],0) ;
407 break ;
408 case SC10_C_WRAP_B :
409 /*SC20*/
410 if ( !smc->y[PB].cf_join && !smc->y[PB].cf_loop ) {
411 GO_STATE(SC0_ISOLATED) ;
412 break ;
413 }
414 /*SC21*/
415 else if ( smc->y[PA].cf_loop && smc->y[PA].pc_mode == PM_PEER &&
416 smc->y[PB].cf_join && smc->y[PB].pc_mode == PM_PEER) {
417 smc->y[PB].scrub = TRUE ;
418 GO_STATE(SC9_C_WRAP_A) ;
419 break ;
420 }
421 /*SC24*/
422 else if (!smc->s.attach_s &&
423 smc->y[PA].cf_join && smc->y[PA].pc_mode == PM_PEER &&
424 smc->y[PB].cf_join && smc->y[PB].pc_mode == PM_PEER) {
425 smc->y[PA].scrub = TRUE ;
426 smc->y[PB].scrub = TRUE ;
427 GO_STATE(SC4_THRU_A) ;
428 break ;
429 }
430 /*SC25*/
431 else if ( smc->s.attach_s &&
432 smc->y[PA].cf_join && smc->y[PA].pc_mode == PM_PEER &&
433 smc->y[PB].cf_join && smc->y[PB].pc_mode == PM_PEER) {
434 smc->y[PA].scrub = TRUE ;
435 smc->y[PB].scrub = TRUE ;
436 GO_STATE(SC5_THRU_B) ;
437 break ;
438 }
439 break ;
440 case ACTIONS(SC4_THRU_A) :
441 smc->mib.p[PA].fddiPORTCurrentPath = MIB_PATH_THRU ;
442 smc->mib.p[PB].fddiPORTCurrentPath = MIB_PATH_THRU ;
443 smc->mib.p[PA].fddiPORTMACPlacement = 0 ;
444 smc->mib.p[PB].fddiPORTMACPlacement = INDEX_MAC ;
445 smc->mib.fddiSMTStationStatus = MIB_SMT_STASTA_THRU ;
446 config_mux(smc,MUX_THRUA) ; /* configure PHY mux */
447 smc->r.rm_loop = FALSE ;
448 smc->r.rm_join = TRUE ;
449 queue_event(smc,EVENT_RMT,RM_JOIN) ;/* signal RMT */
450 ACTIONS_DONE() ;
451 DB_CFMN(1,"CFM : %s\n",cfm_states[smc->mib.fddiSMTCF_State],0) ;
452 break ;
453 case SC4_THRU_A :
454 /*SC41*/
455 if (smc->y[PB].wc_flag || !smc->y[PB].cf_join) {
456 smc->y[PA].scrub = TRUE ;
457 GO_STATE(SC9_C_WRAP_A) ;
458 break ;
459 }
460 /*SC42*/
461 else if (!smc->y[PA].cf_join || smc->y[PA].wc_flag) {
462 smc->y[PB].scrub = TRUE ;
463 GO_STATE(SC10_C_WRAP_B) ;
464 break ;
465 }
466 /*SC45*/
467 else if (smc->s.attach_s) {
468 smc->y[PB].scrub = TRUE ;
469 GO_STATE(SC5_THRU_B) ;
470 break ;
471 }
472 break ;
473 case ACTIONS(SC5_THRU_B) :
474 smc->mib.p[PA].fddiPORTCurrentPath = MIB_PATH_THRU ;
475 smc->mib.p[PB].fddiPORTCurrentPath = MIB_PATH_THRU ;
476 smc->mib.p[PA].fddiPORTMACPlacement = INDEX_MAC ;
477 smc->mib.p[PB].fddiPORTMACPlacement = 0 ;
478 smc->mib.fddiSMTStationStatus = MIB_SMT_STASTA_THRU ;
479 config_mux(smc,MUX_THRUB) ; /* configure PHY mux */
480 smc->r.rm_loop = FALSE ;
481 smc->r.rm_join = TRUE ;
482 queue_event(smc,EVENT_RMT,RM_JOIN) ;/* signal RMT */
483 ACTIONS_DONE() ;
484 DB_CFMN(1,"CFM : %s\n",cfm_states[smc->mib.fddiSMTCF_State],0) ;
485 break ;
486 case SC5_THRU_B :
487 /*SC51*/
488 if (!smc->y[PB].cf_join || smc->y[PB].wc_flag) {
489 smc->y[PA].scrub = TRUE ;
490 GO_STATE(SC9_C_WRAP_A) ;
491 break ;
492 }
493 /*SC52*/
494 else if (!smc->y[PA].cf_join || smc->y[PA].wc_flag) {
495 smc->y[PB].scrub = TRUE ;
496 GO_STATE(SC10_C_WRAP_B) ;
497 break ;
498 }
499 /*SC54*/
500 else if (!smc->s.attach_s) {
501 smc->y[PA].scrub = TRUE ;
502 GO_STATE(SC4_THRU_A) ;
503 break ;
504 }
505 break ;
506 case ACTIONS(SC11_C_WRAP_S) :
507 smc->mib.p[PS].fddiPORTCurrentPath = MIB_PATH_CONCATENATED ;
508 smc->mib.p[PS].fddiPORTMACPlacement = INDEX_MAC ;
509 smc->mib.fddiSMTStationStatus = MIB_SMT_STASTA_CON ;
510 config_mux(smc,MUX_WRAPS) ; /* configure PHY mux */
511 if (smc->y[PA].cf_loop || smc->y[PB].cf_loop) {
512 smc->r.rm_join = FALSE ;
513 smc->r.rm_loop = TRUE ;
514 queue_event(smc,EVENT_RMT,RM_LOOP) ;/* signal RMT */
515 }
516 if (smc->y[PA].cf_join || smc->y[PB].cf_join) {
517 smc->r.rm_loop = FALSE ;
518 smc->r.rm_join = TRUE ;
519 queue_event(smc,EVENT_RMT,RM_JOIN) ;/* signal RMT */
520 }
521 ACTIONS_DONE() ;
522 DB_CFMN(1,"CFM : %s\n",cfm_states[smc->mib.fddiSMTCF_State],0) ;
523 break ;
524 case SC11_C_WRAP_S :
525 /*SC70*/
526 if ( !smc->y[PA].cf_join && !smc->y[PA].cf_loop &&
527 !smc->y[PB].cf_join && !smc->y[PB].cf_loop) {
528 GO_STATE(SC0_ISOLATED) ;
529 break ;
530 }
531 break ;
532 default:
533 SMT_PANIC(smc,SMT_E0106, SMT_E0106_MSG) ;
534 break;
535 }
536}
537
538/*
539 * get MAC's input Port
540 * return :
541 * PA or PB
542 */
543int cfm_get_mac_input(struct s_smc *smc)
544{
545 return (smc->mib.fddiSMTCF_State == SC10_C_WRAP_B ||
546 smc->mib.fddiSMTCF_State == SC5_THRU_B) ? PB : PA;
547}
548
549/*
550 * get MAC's output Port
551 * return :
552 * PA or PB
553 */
554int cfm_get_mac_output(struct s_smc *smc)
555{
556 return (smc->mib.fddiSMTCF_State == SC10_C_WRAP_B ||
557 smc->mib.fddiSMTCF_State == SC4_THRU_A) ? PB : PA;
558}
559
560static char path_iso[] = {
561 0,0, 0,RES_PORT, 0,PA + INDEX_PORT, 0,PATH_ISO,
562 0,0, 0,RES_MAC, 0,INDEX_MAC, 0,PATH_ISO,
563 0,0, 0,RES_PORT, 0,PB + INDEX_PORT, 0,PATH_ISO
564} ;
565
566static char path_wrap_a[] = {
567 0,0, 0,RES_PORT, 0,PA + INDEX_PORT, 0,PATH_PRIM,
568 0,0, 0,RES_MAC, 0,INDEX_MAC, 0,PATH_PRIM,
569 0,0, 0,RES_PORT, 0,PB + INDEX_PORT, 0,PATH_ISO
570} ;
571
572static char path_wrap_b[] = {
573 0,0, 0,RES_PORT, 0,PB + INDEX_PORT, 0,PATH_PRIM,
574 0,0, 0,RES_MAC, 0,INDEX_MAC, 0,PATH_PRIM,
575 0,0, 0,RES_PORT, 0,PA + INDEX_PORT, 0,PATH_ISO
576} ;
577
578static char path_thru[] = {
579 0,0, 0,RES_PORT, 0,PA + INDEX_PORT, 0,PATH_PRIM,
580 0,0, 0,RES_MAC, 0,INDEX_MAC, 0,PATH_PRIM,
581 0,0, 0,RES_PORT, 0,PB + INDEX_PORT, 0,PATH_PRIM
582} ;
583
584static char path_wrap_s[] = {
585 0,0, 0,RES_PORT, 0,PS + INDEX_PORT, 0,PATH_PRIM,
586 0,0, 0,RES_MAC, 0,INDEX_MAC, 0,PATH_PRIM,
587} ;
588
589static char path_iso_s[] = {
590 0,0, 0,RES_PORT, 0,PS + INDEX_PORT, 0,PATH_ISO,
591 0,0, 0,RES_MAC, 0,INDEX_MAC, 0,PATH_ISO,
592} ;
593
594int cem_build_path(struct s_smc *smc, char *to, int path_index)
595{
596 char *path ;
597 int len ;
598
599 switch (smc->mib.fddiSMTCF_State) {
600 default :
601 case SC0_ISOLATED :
602 path = smc->s.sas ? path_iso_s : path_iso ;
603 len = smc->s.sas ? sizeof(path_iso_s) : sizeof(path_iso) ;
604 break ;
605 case SC9_C_WRAP_A :
606 path = path_wrap_a ;
607 len = sizeof(path_wrap_a) ;
608 break ;
609 case SC10_C_WRAP_B :
610 path = path_wrap_b ;
611 len = sizeof(path_wrap_b) ;
612 break ;
613 case SC4_THRU_A :
614 path = path_thru ;
615 len = sizeof(path_thru) ;
616 break ;
617 case SC11_C_WRAP_S :
618 path = path_wrap_s ;
619 len = sizeof(path_wrap_s) ;
620 break ;
621 }
622 memcpy(to,path,len) ;
623
624 LINT_USE(path_index);
625
626 return len;
627}
diff --git a/drivers/net/skfp/drvfbi.c b/drivers/net/skfp/drvfbi.c
deleted file mode 100644
index 07da97c303d6..000000000000
--- a/drivers/net/skfp/drvfbi.c
+++ /dev/null
@@ -1,584 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 * FBI board dependent Driver for SMT and LLC
19 */
20
21#include "h/types.h"
22#include "h/fddi.h"
23#include "h/smc.h"
24#include "h/supern_2.h"
25#include "h/skfbiinc.h"
26#include <linux/bitrev.h>
27
28#ifndef lint
29static const char ID_sccs[] = "@(#)drvfbi.c 1.63 99/02/11 (C) SK " ;
30#endif
31
32/*
33 * PCM active state
34 */
35#define PC8_ACTIVE 8
36
37#define LED_Y_ON 0x11 /* Used for ring up/down indication */
38#define LED_Y_OFF 0x10
39
40
41#define MS2BCLK(x) ((x)*12500L)
42
43/*
44 * valid configuration values are:
45 */
46
47/*
48 * xPOS_ID:xxxx
49 * | \ /
50 * | \/
51 * | --------------------- the patched POS_ID of the Adapter
52 * | xxxx = (Vendor ID low byte,
53 * | Vendor ID high byte,
54 * | Device ID low byte,
55 * | Device ID high byte)
56 * +------------------------------ the patched oem_id must be
57 * 'S' for SK or 'I' for IBM
58 * this is a short id for the driver.
59 */
60#ifndef MULT_OEM
61#ifndef OEM_CONCEPT
62const u_char oem_id[] = "xPOS_ID:xxxx" ;
63#else /* OEM_CONCEPT */
64const u_char oem_id[] = OEM_ID ;
65#endif /* OEM_CONCEPT */
66#define ID_BYTE0 8
67#define OEMID(smc,i) oem_id[ID_BYTE0 + i]
68#else /* MULT_OEM */
69const struct s_oem_ids oem_ids[] = {
70#include "oemids.h"
71{0}
72};
73#define OEMID(smc,i) smc->hw.oem_id->oi_id[i]
74#endif /* MULT_OEM */
75
76/* Prototypes of external functions */
77#ifdef AIX
78extern int AIX_vpdReadByte() ;
79#endif
80
81
82/* Prototype of a local function. */
83static void smt_stop_watchdog(struct s_smc *smc);
84
85/*
86 * FDDI card reset
87 */
88static void card_start(struct s_smc *smc)
89{
90 int i ;
91#ifdef PCI
92 u_char rev_id ;
93 u_short word;
94#endif
95
96 smt_stop_watchdog(smc) ;
97
98#ifdef PCI
99 /*
100 * make sure no transfer activity is pending
101 */
102 outpw(FM_A(FM_MDREG1),FM_MINIT) ;
103 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ;
104 hwt_wait_time(smc,hwt_quick_read(smc),MS2BCLK(10)) ;
105 /*
106 * now reset everything
107 */
108 outp(ADDR(B0_CTRL),CTRL_RST_SET) ; /* reset for all chips */
109 i = (int) inp(ADDR(B0_CTRL)) ; /* do dummy read */
110 SK_UNUSED(i) ; /* Make LINT happy. */
111 outp(ADDR(B0_CTRL), CTRL_RST_CLR) ;
112
113 /*
114 * Reset all bits in the PCI STATUS register
115 */
116 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_ON) ; /* enable for writes */
117 word = inpw(PCI_C(PCI_STATUS)) ;
118 outpw(PCI_C(PCI_STATUS), word | PCI_ERRBITS) ;
119 outp(ADDR(B0_TST_CTRL), TST_CFG_WRITE_OFF) ; /* disable writes */
120
121 /*
122 * Release the reset of all the State machines
123 * Release Master_Reset
124 * Release HPI_SM_Reset
125 */
126 outp(ADDR(B0_CTRL), CTRL_MRST_CLR|CTRL_HPI_CLR) ;
127
128 /*
129 * determine the adapter type
130 * Note: Do it here, because some drivers may call card_start() once
131 * at very first before any other initialization functions is
132 * executed.
133 */
134 rev_id = inp(PCI_C(PCI_REV_ID)) ;
135 if ((rev_id & 0xf0) == SK_ML_ID_1 || (rev_id & 0xf0) == SK_ML_ID_2) {
136 smc->hw.hw_is_64bit = TRUE ;
137 } else {
138 smc->hw.hw_is_64bit = FALSE ;
139 }
140
141 /*
142 * Watermark initialization
143 */
144 if (!smc->hw.hw_is_64bit) {
145 outpd(ADDR(B4_R1_F), RX_WATERMARK) ;
146 outpd(ADDR(B5_XA_F), TX_WATERMARK) ;
147 outpd(ADDR(B5_XS_F), TX_WATERMARK) ;
148 }
149
150 outp(ADDR(B0_CTRL),CTRL_RST_CLR) ; /* clear the reset chips */
151 outp(ADDR(B0_LED),LED_GA_OFF|LED_MY_ON|LED_GB_OFF) ; /* ye LED on */
152
153 /* init the timer value for the watch dog 2,5 minutes */
154 outpd(ADDR(B2_WDOG_INI),0x6FC23AC0) ;
155
156 /* initialize the ISR mask */
157 smc->hw.is_imask = ISR_MASK ;
158 smc->hw.hw_state = STOPPED ;
159#endif
160 GET_PAGE(0) ; /* necessary for BOOT */
161}
162
163void card_stop(struct s_smc *smc)
164{
165 smt_stop_watchdog(smc) ;
166 smc->hw.mac_ring_is_up = 0 ; /* ring down */
167
168#ifdef PCI
169 /*
170 * make sure no transfer activity is pending
171 */
172 outpw(FM_A(FM_MDREG1),FM_MINIT) ;
173 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ;
174 hwt_wait_time(smc,hwt_quick_read(smc),MS2BCLK(10)) ;
175 /*
176 * now reset everything
177 */
178 outp(ADDR(B0_CTRL),CTRL_RST_SET) ; /* reset for all chips */
179 outp(ADDR(B0_CTRL),CTRL_RST_CLR) ; /* reset for all chips */
180 outp(ADDR(B0_LED),LED_GA_OFF|LED_MY_OFF|LED_GB_OFF) ; /* all LEDs off */
181 smc->hw.hw_state = STOPPED ;
182#endif
183}
184/*--------------------------- ISR handling ----------------------------------*/
185
186void mac1_irq(struct s_smc *smc, u_short stu, u_short stl)
187{
188 int restart_tx = 0 ;
189again:
190
191 /*
192 * parity error: note encoding error is not possible in tag mode
193 */
194 if (stl & (FM_SPCEPDS | /* parity err. syn.q.*/
195 FM_SPCEPDA0 | /* parity err. a.q.0 */
196 FM_SPCEPDA1)) { /* parity err. a.q.1 */
197 SMT_PANIC(smc,SMT_E0134, SMT_E0134_MSG) ;
198 }
199 /*
200 * buffer underrun: can only occur if a tx threshold is specified
201 */
202 if (stl & (FM_STBURS | /* tx buffer underrun syn.q.*/
203 FM_STBURA0 | /* tx buffer underrun a.q.0 */
204 FM_STBURA1)) { /* tx buffer underrun a.q.2 */
205 SMT_PANIC(smc,SMT_E0133, SMT_E0133_MSG) ;
206 }
207
208 if ( (stu & (FM_SXMTABT | /* transmit abort */
209 FM_STXABRS | /* syn. tx abort */
210 FM_STXABRA0)) || /* asyn. tx abort */
211 (stl & (FM_SQLCKS | /* lock for syn. q. */
212 FM_SQLCKA0)) ) { /* lock for asyn. q. */
213 formac_tx_restart(smc) ; /* init tx */
214 restart_tx = 1 ;
215 stu = inpw(FM_A(FM_ST1U)) ;
216 stl = inpw(FM_A(FM_ST1L)) ;
217 stu &= ~ (FM_STECFRMA0 | FM_STEFRMA0 | FM_STEFRMS) ;
218 if (stu || stl)
219 goto again ;
220 }
221
222 if (stu & (FM_STEFRMA0 | /* end of asyn tx */
223 FM_STEFRMS)) { /* end of sync tx */
224 restart_tx = 1 ;
225 }
226
227 if (restart_tx)
228 llc_restart_tx(smc) ;
229}
230
231/*
232 * interrupt source= plc1
233 * this function is called in nwfbisr.asm
234 */
235void plc1_irq(struct s_smc *smc)
236{
237 u_short st = inpw(PLC(PB,PL_INTR_EVENT)) ;
238
239 plc_irq(smc,PB,st) ;
240}
241
242/*
243 * interrupt source= plc2
244 * this function is called in nwfbisr.asm
245 */
246void plc2_irq(struct s_smc *smc)
247{
248 u_short st = inpw(PLC(PA,PL_INTR_EVENT)) ;
249
250 plc_irq(smc,PA,st) ;
251}
252
253
254/*
255 * interrupt source= timer
256 */
257void timer_irq(struct s_smc *smc)
258{
259 hwt_restart(smc);
260 smc->hw.t_stop = smc->hw.t_start;
261 smt_timer_done(smc) ;
262}
263
264/*
265 * return S-port (PA or PB)
266 */
267int pcm_get_s_port(struct s_smc *smc)
268{
269 SK_UNUSED(smc) ;
270 return PS;
271}
272
273/*
274 * Station Label = "FDDI-XYZ" where
275 *
276 * X = connector type
277 * Y = PMD type
278 * Z = port type
279 */
280#define STATION_LABEL_CONNECTOR_OFFSET 5
281#define STATION_LABEL_PMD_OFFSET 6
282#define STATION_LABEL_PORT_OFFSET 7
283
284void read_address(struct s_smc *smc, u_char *mac_addr)
285{
286 char ConnectorType ;
287 char PmdType ;
288 int i ;
289
290#ifdef PCI
291 for (i = 0; i < 6; i++) { /* read mac address from board */
292 smc->hw.fddi_phys_addr.a[i] =
293 bitrev8(inp(ADDR(B2_MAC_0+i)));
294 }
295#endif
296
297 ConnectorType = inp(ADDR(B2_CONN_TYP)) ;
298 PmdType = inp(ADDR(B2_PMD_TYP)) ;
299
300 smc->y[PA].pmd_type[PMD_SK_CONN] =
301 smc->y[PB].pmd_type[PMD_SK_CONN] = ConnectorType ;
302 smc->y[PA].pmd_type[PMD_SK_PMD ] =
303 smc->y[PB].pmd_type[PMD_SK_PMD ] = PmdType ;
304
305 if (mac_addr) {
306 for (i = 0; i < 6 ;i++) {
307 smc->hw.fddi_canon_addr.a[i] = mac_addr[i] ;
308 smc->hw.fddi_home_addr.a[i] = bitrev8(mac_addr[i]);
309 }
310 return ;
311 }
312 smc->hw.fddi_home_addr = smc->hw.fddi_phys_addr ;
313
314 for (i = 0; i < 6 ;i++) {
315 smc->hw.fddi_canon_addr.a[i] =
316 bitrev8(smc->hw.fddi_phys_addr.a[i]);
317 }
318}
319
320/*
321 * FDDI card soft reset
322 */
323void init_board(struct s_smc *smc, u_char *mac_addr)
324{
325 card_start(smc) ;
326 read_address(smc,mac_addr) ;
327
328 if (!(inp(ADDR(B0_DAS)) & DAS_AVAIL))
329 smc->s.sas = SMT_SAS ; /* Single att. station */
330 else
331 smc->s.sas = SMT_DAS ; /* Dual att. station */
332
333 if (!(inp(ADDR(B0_DAS)) & DAS_BYP_ST))
334 smc->mib.fddiSMTBypassPresent = 0 ;
335 /* without opt. bypass */
336 else
337 smc->mib.fddiSMTBypassPresent = 1 ;
338 /* with opt. bypass */
339}
340
341/*
342 * insert or deinsert optical bypass (called by ECM)
343 */
344void sm_pm_bypass_req(struct s_smc *smc, int mode)
345{
346 DB_ECMN(1,"ECM : sm_pm_bypass_req(%s)\n",(mode == BP_INSERT) ?
347 "BP_INSERT" : "BP_DEINSERT",0) ;
348
349 if (smc->s.sas != SMT_DAS)
350 return ;
351
352#ifdef PCI
353 switch(mode) {
354 case BP_INSERT :
355 outp(ADDR(B0_DAS),DAS_BYP_INS) ; /* insert station */
356 break ;
357 case BP_DEINSERT :
358 outp(ADDR(B0_DAS),DAS_BYP_RMV) ; /* bypass station */
359 break ;
360 }
361#endif
362}
363
364/*
365 * check if bypass connected
366 */
367int sm_pm_bypass_present(struct s_smc *smc)
368{
369 return (inp(ADDR(B0_DAS)) & DAS_BYP_ST) ? TRUE : FALSE;
370}
371
372void plc_clear_irq(struct s_smc *smc, int p)
373{
374 SK_UNUSED(p) ;
375
376 SK_UNUSED(smc) ;
377}
378
379
380/*
381 * led_indication called by rmt_indication() and
382 * pcm_state_change()
383 *
384 * Input:
385 * smc: SMT context
386 * led_event:
387 * 0 Only switch green LEDs according to their respective PCM state
388 * LED_Y_OFF just switch yellow LED off
389 * LED_Y_ON just switch yello LED on
390 */
391static void led_indication(struct s_smc *smc, int led_event)
392{
393 /* use smc->hw.mac_ring_is_up == TRUE
394 * as indication for Ring Operational
395 */
396 u_short led_state ;
397 struct s_phy *phy ;
398 struct fddi_mib_p *mib_a ;
399 struct fddi_mib_p *mib_b ;
400
401 phy = &smc->y[PA] ;
402 mib_a = phy->mib ;
403 phy = &smc->y[PB] ;
404 mib_b = phy->mib ;
405
406#ifdef PCI
407 led_state = 0 ;
408
409 /* Ring up = yellow led OFF*/
410 if (led_event == LED_Y_ON) {
411 led_state |= LED_MY_ON ;
412 }
413 else if (led_event == LED_Y_OFF) {
414 led_state |= LED_MY_OFF ;
415 }
416 else { /* PCM state changed */
417 /* Link at Port A/S = green led A ON */
418 if (mib_a->fddiPORTPCMState == PC8_ACTIVE) {
419 led_state |= LED_GA_ON ;
420 }
421 else {
422 led_state |= LED_GA_OFF ;
423 }
424
425 /* Link at Port B = green led B ON */
426 if (mib_b->fddiPORTPCMState == PC8_ACTIVE) {
427 led_state |= LED_GB_ON ;
428 }
429 else {
430 led_state |= LED_GB_OFF ;
431 }
432 }
433
434 outp(ADDR(B0_LED), led_state) ;
435#endif /* PCI */
436
437}
438
439
440void pcm_state_change(struct s_smc *smc, int plc, int p_state)
441{
442 /*
443 * the current implementation of pcm_state_change() in the driver
444 * parts must be renamed to drv_pcm_state_change() which will be called
445 * now after led_indication.
446 */
447 DRV_PCM_STATE_CHANGE(smc,plc,p_state) ;
448
449 led_indication(smc,0) ;
450}
451
452
453void rmt_indication(struct s_smc *smc, int i)
454{
455 /* Call a driver special function if defined */
456 DRV_RMT_INDICATION(smc,i) ;
457
458 led_indication(smc, i ? LED_Y_OFF : LED_Y_ON) ;
459}
460
461
462/*
463 * llc_recover_tx called by init_tx (fplus.c)
464 */
465void llc_recover_tx(struct s_smc *smc)
466{
467#ifdef LOAD_GEN
468 extern int load_gen_flag ;
469
470 load_gen_flag = 0 ;
471#endif
472#ifndef SYNC
473 smc->hw.n_a_send= 0 ;
474#else
475 SK_UNUSED(smc) ;
476#endif
477}
478
479#ifdef MULT_OEM
480static int is_equal_num(char comp1[], char comp2[], int num)
481{
482 int i ;
483
484 for (i = 0 ; i < num ; i++) {
485 if (comp1[i] != comp2[i])
486 return 0;
487 }
488 return 1;
489} /* is_equal_num */
490
491
492/*
493 * set the OEM ID defaults, and test the contents of the OEM data base
494 * The default OEM is the first ACTIVE entry in the OEM data base
495 *
496 * returns: 0 success
497 * 1 error in data base
498 * 2 data base empty
499 * 3 no active entry
500 */
501int set_oi_id_def(struct s_smc *smc)
502{
503 int sel_id ;
504 int i ;
505 int act_entries ;
506
507 i = 0 ;
508 sel_id = -1 ;
509 act_entries = FALSE ;
510 smc->hw.oem_id = 0 ;
511 smc->hw.oem_min_status = OI_STAT_ACTIVE ;
512
513 /* check OEM data base */
514 while (oem_ids[i].oi_status) {
515 switch (oem_ids[i].oi_status) {
516 case OI_STAT_ACTIVE:
517 act_entries = TRUE ; /* we have active IDs */
518 if (sel_id == -1)
519 sel_id = i ; /* save the first active ID */
520 case OI_STAT_VALID:
521 case OI_STAT_PRESENT:
522 i++ ;
523 break ; /* entry ok */
524 default:
525 return 1; /* invalid oi_status */
526 }
527 }
528
529 if (i == 0)
530 return 2;
531 if (!act_entries)
532 return 3;
533
534 /* ok, we have a valid OEM data base with an active entry */
535 smc->hw.oem_id = (struct s_oem_ids *) &oem_ids[sel_id] ;
536 return 0;
537}
538#endif /* MULT_OEM */
539
540void driver_get_bia(struct s_smc *smc, struct fddi_addr *bia_addr)
541{
542 int i ;
543
544 for (i = 0 ; i < 6 ; i++)
545 bia_addr->a[i] = bitrev8(smc->hw.fddi_phys_addr.a[i]);
546}
547
548void smt_start_watchdog(struct s_smc *smc)
549{
550 SK_UNUSED(smc) ; /* Make LINT happy. */
551
552#ifndef DEBUG
553
554#ifdef PCI
555 if (smc->hw.wdog_used) {
556 outpw(ADDR(B2_WDOG_CRTL),TIM_START) ; /* Start timer. */
557 }
558#endif
559
560#endif /* DEBUG */
561}
562
563static void smt_stop_watchdog(struct s_smc *smc)
564{
565 SK_UNUSED(smc) ; /* Make LINT happy. */
566#ifndef DEBUG
567
568#ifdef PCI
569 if (smc->hw.wdog_used) {
570 outpw(ADDR(B2_WDOG_CRTL),TIM_STOP) ; /* Stop timer. */
571 }
572#endif
573
574#endif /* DEBUG */
575}
576
577#ifdef PCI
578
579void mac_do_pci_fix(struct s_smc *smc)
580{
581 SK_UNUSED(smc) ;
582}
583#endif /* PCI */
584
diff --git a/drivers/net/skfp/ecm.c b/drivers/net/skfp/ecm.c
deleted file mode 100644
index 47d922cb3c08..000000000000
--- a/drivers/net/skfp/ecm.c
+++ /dev/null
@@ -1,536 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 SMT ECM
19 Entity Coordination Management
20 Hardware independent state machine
21*/
22
23/*
24 * Hardware independent state machine implemantation
25 * The following external SMT functions are referenced :
26 *
27 * queue_event()
28 * smt_timer_start()
29 * smt_timer_stop()
30 *
31 * The following external HW dependent functions are referenced :
32 * sm_pm_bypass_req()
33 * sm_pm_ls_latch()
34 * sm_pm_get_ls()
35 *
36 * The following HW dependent events are required :
37 * NONE
38 *
39 */
40
41#include "h/types.h"
42#include "h/fddi.h"
43#include "h/smc.h"
44
45#define KERNEL
46#include "h/smtstate.h"
47
48#ifndef lint
49static const char ID_sccs[] = "@(#)ecm.c 2.7 99/08/05 (C) SK " ;
50#endif
51
52/*
53 * FSM Macros
54 */
55#define AFLAG 0x10
56#define GO_STATE(x) (smc->mib.fddiSMTECMState = (x)|AFLAG)
57#define ACTIONS_DONE() (smc->mib.fddiSMTECMState &= ~AFLAG)
58#define ACTIONS(x) (x|AFLAG)
59
60#define EC0_OUT 0 /* not inserted */
61#define EC1_IN 1 /* inserted */
62#define EC2_TRACE 2 /* tracing */
63#define EC3_LEAVE 3 /* leaving the ring */
64#define EC4_PATH_TEST 4 /* performing path test */
65#define EC5_INSERT 5 /* bypass being turned on */
66#define EC6_CHECK 6 /* checking bypass */
67#define EC7_DEINSERT 7 /* bypass being turnde off */
68
69#ifdef DEBUG
70/*
71 * symbolic state names
72 */
73static const char * const ecm_states[] = {
74 "EC0_OUT","EC1_IN","EC2_TRACE","EC3_LEAVE","EC4_PATH_TEST",
75 "EC5_INSERT","EC6_CHECK","EC7_DEINSERT"
76} ;
77
78/*
79 * symbolic event names
80 */
81static const char * const ecm_events[] = {
82 "NONE","EC_CONNECT","EC_DISCONNECT","EC_TRACE_PROP","EC_PATH_TEST",
83 "EC_TIMEOUT_TD","EC_TIMEOUT_TMAX",
84 "EC_TIMEOUT_IMAX","EC_TIMEOUT_INMAX","EC_TEST_DONE"
85} ;
86#endif
87
88/*
89 * all Globals are defined in smc.h
90 * struct s_ecm
91 */
92
93/*
94 * function declarations
95 */
96
97static void ecm_fsm(struct s_smc *smc, int cmd);
98static void start_ecm_timer(struct s_smc *smc, u_long value, int event);
99static void stop_ecm_timer(struct s_smc *smc);
100static void prop_actions(struct s_smc *smc);
101
102/*
103 init ECM state machine
104 clear all ECM vars and flags
105*/
106void ecm_init(struct s_smc *smc)
107{
108 smc->e.path_test = PT_PASSED ;
109 smc->e.trace_prop = 0 ;
110 smc->e.sb_flag = 0 ;
111 smc->mib.fddiSMTECMState = ACTIONS(EC0_OUT) ;
112 smc->e.ecm_line_state = FALSE ;
113}
114
115/*
116 ECM state machine
117 called by dispatcher
118
119 do
120 display state change
121 process event
122 until SM is stable
123*/
124void ecm(struct s_smc *smc, int event)
125{
126 int state ;
127
128 do {
129 DB_ECM("ECM : state %s%s",
130 (smc->mib.fddiSMTECMState & AFLAG) ? "ACTIONS " : "",
131 ecm_states[smc->mib.fddiSMTECMState & ~AFLAG]) ;
132 DB_ECM(" event %s\n",ecm_events[event],0) ;
133 state = smc->mib.fddiSMTECMState ;
134 ecm_fsm(smc,event) ;
135 event = 0 ;
136 } while (state != smc->mib.fddiSMTECMState) ;
137 ecm_state_change(smc,(int)smc->mib.fddiSMTECMState) ;
138}
139
140/*
141 process ECM event
142*/
143static void ecm_fsm(struct s_smc *smc, int cmd)
144{
145 int ls_a ; /* current line state PHY A */
146 int ls_b ; /* current line state PHY B */
147 int p ; /* ports */
148
149
150 smc->mib.fddiSMTBypassPresent = sm_pm_bypass_present(smc) ;
151 if (cmd == EC_CONNECT)
152 smc->mib.fddiSMTRemoteDisconnectFlag = FALSE ;
153
154 /* For AIX event notification: */
155 /* Is a disconnect command remotely issued ? */
156 if (cmd == EC_DISCONNECT &&
157 smc->mib.fddiSMTRemoteDisconnectFlag == TRUE)
158 AIX_EVENT (smc, (u_long) CIO_HARD_FAIL, (u_long)
159 FDDI_REMOTE_DISCONNECT, smt_get_event_word(smc),
160 smt_get_error_word(smc) );
161
162 /*jd 05-Aug-1999 Bug #10419 "Port Disconnect fails at Dup MAc Cond."*/
163 if (cmd == EC_CONNECT) {
164 smc->e.DisconnectFlag = FALSE ;
165 }
166 else if (cmd == EC_DISCONNECT) {
167 smc->e.DisconnectFlag = TRUE ;
168 }
169
170 switch(smc->mib.fddiSMTECMState) {
171 case ACTIONS(EC0_OUT) :
172 /*
173 * We do not perform a path test
174 */
175 smc->e.path_test = PT_PASSED ;
176 smc->e.ecm_line_state = FALSE ;
177 stop_ecm_timer(smc) ;
178 ACTIONS_DONE() ;
179 break ;
180 case EC0_OUT:
181 /*EC01*/
182 if (cmd == EC_CONNECT && !smc->mib.fddiSMTBypassPresent
183 && smc->e.path_test==PT_PASSED) {
184 GO_STATE(EC1_IN) ;
185 break ;
186 }
187 /*EC05*/
188 else if (cmd == EC_CONNECT && (smc->e.path_test==PT_PASSED) &&
189 smc->mib.fddiSMTBypassPresent &&
190 (smc->s.sas == SMT_DAS)) {
191 GO_STATE(EC5_INSERT) ;
192 break ;
193 }
194 break;
195 case ACTIONS(EC1_IN) :
196 stop_ecm_timer(smc) ;
197 smc->e.trace_prop = 0 ;
198 sm_ma_control(smc,MA_TREQ) ;
199 for (p = 0 ; p < NUMPHYS ; p++)
200 if (smc->mib.p[p].fddiPORTHardwarePresent)
201 queue_event(smc,EVENT_PCMA+p,PC_START) ;
202 ACTIONS_DONE() ;
203 break ;
204 case EC1_IN:
205 /*EC12*/
206 if (cmd == EC_TRACE_PROP) {
207 prop_actions(smc) ;
208 GO_STATE(EC2_TRACE) ;
209 break ;
210 }
211 /*EC13*/
212 else if (cmd == EC_DISCONNECT) {
213 GO_STATE(EC3_LEAVE) ;
214 break ;
215 }
216 break;
217 case ACTIONS(EC2_TRACE) :
218 start_ecm_timer(smc,MIB2US(smc->mib.fddiSMTTrace_MaxExpiration),
219 EC_TIMEOUT_TMAX) ;
220 ACTIONS_DONE() ;
221 break ;
222 case EC2_TRACE :
223 /*EC22*/
224 if (cmd == EC_TRACE_PROP) {
225 prop_actions(smc) ;
226 GO_STATE(EC2_TRACE) ;
227 break ;
228 }
229 /*EC23a*/
230 else if (cmd == EC_DISCONNECT) {
231 smc->e.path_test = PT_EXITING ;
232 GO_STATE(EC3_LEAVE) ;
233 break ;
234 }
235 /*EC23b*/
236 else if (smc->e.path_test == PT_PENDING) {
237 GO_STATE(EC3_LEAVE) ;
238 break ;
239 }
240 /*EC23c*/
241 else if (cmd == EC_TIMEOUT_TMAX) {
242 /* Trace_Max is expired */
243 /* -> send AIX_EVENT */
244 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS,
245 (u_long) FDDI_SMT_ERROR, (u_long)
246 FDDI_TRACE_MAX, smt_get_error_word(smc));
247 smc->e.path_test = PT_PENDING ;
248 GO_STATE(EC3_LEAVE) ;
249 break ;
250 }
251 break ;
252 case ACTIONS(EC3_LEAVE) :
253 start_ecm_timer(smc,smc->s.ecm_td_min,EC_TIMEOUT_TD) ;
254 for (p = 0 ; p < NUMPHYS ; p++)
255 queue_event(smc,EVENT_PCMA+p,PC_STOP) ;
256 ACTIONS_DONE() ;
257 break ;
258 case EC3_LEAVE:
259 /*EC30*/
260 if (cmd == EC_TIMEOUT_TD && !smc->mib.fddiSMTBypassPresent &&
261 (smc->e.path_test != PT_PENDING)) {
262 GO_STATE(EC0_OUT) ;
263 break ;
264 }
265 /*EC34*/
266 else if (cmd == EC_TIMEOUT_TD &&
267 (smc->e.path_test == PT_PENDING)) {
268 GO_STATE(EC4_PATH_TEST) ;
269 break ;
270 }
271 /*EC31*/
272 else if (cmd == EC_CONNECT && smc->e.path_test == PT_PASSED) {
273 GO_STATE(EC1_IN) ;
274 break ;
275 }
276 /*EC33*/
277 else if (cmd == EC_DISCONNECT &&
278 smc->e.path_test == PT_PENDING) {
279 smc->e.path_test = PT_EXITING ;
280 /*
281 * stay in state - state will be left via timeout
282 */
283 }
284 /*EC37*/
285 else if (cmd == EC_TIMEOUT_TD &&
286 smc->mib.fddiSMTBypassPresent &&
287 smc->e.path_test != PT_PENDING) {
288 GO_STATE(EC7_DEINSERT) ;
289 break ;
290 }
291 break ;
292 case ACTIONS(EC4_PATH_TEST) :
293 stop_ecm_timer(smc) ;
294 smc->e.path_test = PT_TESTING ;
295 start_ecm_timer(smc,smc->s.ecm_test_done,EC_TEST_DONE) ;
296 /* now perform path test ... just a simulation */
297 ACTIONS_DONE() ;
298 break ;
299 case EC4_PATH_TEST :
300 /* path test done delay */
301 if (cmd == EC_TEST_DONE)
302 smc->e.path_test = PT_PASSED ;
303
304 if (smc->e.path_test == PT_FAILED)
305 RS_SET(smc,RS_PATHTEST) ;
306
307 /*EC40a*/
308 if (smc->e.path_test == PT_FAILED &&
309 !smc->mib.fddiSMTBypassPresent) {
310 GO_STATE(EC0_OUT) ;
311 break ;
312 }
313 /*EC40b*/
314 else if (cmd == EC_DISCONNECT &&
315 !smc->mib.fddiSMTBypassPresent) {
316 GO_STATE(EC0_OUT) ;
317 break ;
318 }
319 /*EC41*/
320 else if (smc->e.path_test == PT_PASSED) {
321 GO_STATE(EC1_IN) ;
322 break ;
323 }
324 /*EC47a*/
325 else if (smc->e.path_test == PT_FAILED &&
326 smc->mib.fddiSMTBypassPresent) {
327 GO_STATE(EC7_DEINSERT) ;
328 break ;
329 }
330 /*EC47b*/
331 else if (cmd == EC_DISCONNECT &&
332 smc->mib.fddiSMTBypassPresent) {
333 GO_STATE(EC7_DEINSERT) ;
334 break ;
335 }
336 break ;
337 case ACTIONS(EC5_INSERT) :
338 sm_pm_bypass_req(smc,BP_INSERT);
339 start_ecm_timer(smc,smc->s.ecm_in_max,EC_TIMEOUT_INMAX) ;
340 ACTIONS_DONE() ;
341 break ;
342 case EC5_INSERT :
343 /*EC56*/
344 if (cmd == EC_TIMEOUT_INMAX) {
345 GO_STATE(EC6_CHECK) ;
346 break ;
347 }
348 /*EC57*/
349 else if (cmd == EC_DISCONNECT) {
350 GO_STATE(EC7_DEINSERT) ;
351 break ;
352 }
353 break ;
354 case ACTIONS(EC6_CHECK) :
355 /*
356 * in EC6_CHECK, we *POLL* the line state !
357 * check whether both bypass switches have switched.
358 */
359 start_ecm_timer(smc,smc->s.ecm_check_poll,0) ;
360 smc->e.ecm_line_state = TRUE ; /* flag to pcm: report Q/HLS */
361 (void) sm_pm_ls_latch(smc,PA,1) ; /* enable line state latch */
362 (void) sm_pm_ls_latch(smc,PB,1) ; /* enable line state latch */
363 ACTIONS_DONE() ;
364 break ;
365 case EC6_CHECK :
366 ls_a = sm_pm_get_ls(smc,PA) ;
367 ls_b = sm_pm_get_ls(smc,PB) ;
368
369 /*EC61*/
370 if (((ls_a == PC_QLS) || (ls_a == PC_HLS)) &&
371 ((ls_b == PC_QLS) || (ls_b == PC_HLS)) ) {
372 smc->e.sb_flag = FALSE ;
373 smc->e.ecm_line_state = FALSE ;
374 GO_STATE(EC1_IN) ;
375 break ;
376 }
377 /*EC66*/
378 else if (!smc->e.sb_flag &&
379 (((ls_a == PC_ILS) && (ls_b == PC_QLS)) ||
380 ((ls_a == PC_QLS) && (ls_b == PC_ILS)))){
381 smc->e.sb_flag = TRUE ;
382 DB_ECMN(1,"ECM : EC6_CHECK - stuck bypass\n",0,0) ;
383 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
384 FDDI_SMT_ERROR, (u_long) FDDI_BYPASS_STUCK,
385 smt_get_error_word(smc));
386 }
387 /*EC67*/
388 else if (cmd == EC_DISCONNECT) {
389 smc->e.ecm_line_state = FALSE ;
390 GO_STATE(EC7_DEINSERT) ;
391 break ;
392 }
393 else {
394 /*
395 * restart poll
396 */
397 start_ecm_timer(smc,smc->s.ecm_check_poll,0) ;
398 }
399 break ;
400 case ACTIONS(EC7_DEINSERT) :
401 sm_pm_bypass_req(smc,BP_DEINSERT);
402 start_ecm_timer(smc,smc->s.ecm_i_max,EC_TIMEOUT_IMAX) ;
403 ACTIONS_DONE() ;
404 break ;
405 case EC7_DEINSERT:
406 /*EC70*/
407 if (cmd == EC_TIMEOUT_IMAX) {
408 GO_STATE(EC0_OUT) ;
409 break ;
410 }
411 /*EC75*/
412 else if (cmd == EC_CONNECT && smc->e.path_test == PT_PASSED) {
413 GO_STATE(EC5_INSERT) ;
414 break ;
415 }
416 break;
417 default:
418 SMT_PANIC(smc,SMT_E0107, SMT_E0107_MSG) ;
419 break;
420 }
421}
422
423#ifndef CONCENTRATOR
424/*
425 * trace propagation actions for SAS & DAS
426 */
427static void prop_actions(struct s_smc *smc)
428{
429 int port_in = 0 ;
430 int port_out = 0 ;
431
432 RS_SET(smc,RS_EVENT) ;
433 switch (smc->s.sas) {
434 case SMT_SAS :
435 port_in = port_out = pcm_get_s_port(smc) ;
436 break ;
437 case SMT_DAS :
438 port_in = cfm_get_mac_input(smc) ; /* PA or PB */
439 port_out = cfm_get_mac_output(smc) ; /* PA or PB */
440 break ;
441 case SMT_NAC :
442 SMT_PANIC(smc,SMT_E0108, SMT_E0108_MSG) ;
443 return ;
444 }
445
446 DB_ECM("ECM : prop_actions - trace_prop %d\n", smc->e.trace_prop,0) ;
447 DB_ECM("ECM : prop_actions - in %d out %d\n", port_in,port_out) ;
448
449 if (smc->e.trace_prop & ENTITY_BIT(ENTITY_MAC)) {
450 /* trace initiatior */
451 DB_ECM("ECM : initiate TRACE on PHY %c\n",'A'+port_in-PA,0) ;
452 queue_event(smc,EVENT_PCM+port_in,PC_TRACE) ;
453 }
454 else if ((smc->e.trace_prop & ENTITY_BIT(ENTITY_PHY(PA))) &&
455 port_out != PA) {
456 /* trace propagate upstream */
457 DB_ECM("ECM : propagate TRACE on PHY B\n",0,0) ;
458 queue_event(smc,EVENT_PCMB,PC_TRACE) ;
459 }
460 else if ((smc->e.trace_prop & ENTITY_BIT(ENTITY_PHY(PB))) &&
461 port_out != PB) {
462 /* trace propagate upstream */
463 DB_ECM("ECM : propagate TRACE on PHY A\n",0,0) ;
464 queue_event(smc,EVENT_PCMA,PC_TRACE) ;
465 }
466 else {
467 /* signal trace termination */
468 DB_ECM("ECM : TRACE terminated\n",0,0) ;
469 smc->e.path_test = PT_PENDING ;
470 }
471 smc->e.trace_prop = 0 ;
472}
473#else
474/*
475 * trace propagation actions for Concentrator
476 */
477static void prop_actions(struct s_smc *smc)
478{
479 int initiator ;
480 int upstream ;
481 int p ;
482
483 RS_SET(smc,RS_EVENT) ;
484 while (smc->e.trace_prop) {
485 DB_ECM("ECM : prop_actions - trace_prop %d\n",
486 smc->e.trace_prop,0) ;
487
488 if (smc->e.trace_prop & ENTITY_BIT(ENTITY_MAC)) {
489 initiator = ENTITY_MAC ;
490 smc->e.trace_prop &= ~ENTITY_BIT(ENTITY_MAC) ;
491 DB_ECM("ECM: MAC initiates trace\n",0,0) ;
492 }
493 else {
494 for (p = NUMPHYS-1 ; p >= 0 ; p--) {
495 if (smc->e.trace_prop &
496 ENTITY_BIT(ENTITY_PHY(p)))
497 break ;
498 }
499 initiator = ENTITY_PHY(p) ;
500 smc->e.trace_prop &= ~ENTITY_BIT(ENTITY_PHY(p)) ;
501 }
502 upstream = cem_get_upstream(smc,initiator) ;
503
504 if (upstream == ENTITY_MAC) {
505 /* signal trace termination */
506 DB_ECM("ECM : TRACE terminated\n",0,0) ;
507 smc->e.path_test = PT_PENDING ;
508 }
509 else {
510 /* trace propagate upstream */
511 DB_ECM("ECM : propagate TRACE on PHY %d\n",upstream,0) ;
512 queue_event(smc,EVENT_PCM+upstream,PC_TRACE) ;
513 }
514 }
515}
516#endif
517
518
519/*
520 * SMT timer interface
521 * start ECM timer
522 */
523static void start_ecm_timer(struct s_smc *smc, u_long value, int event)
524{
525 smt_timer_start(smc,&smc->e.ecm_timer,value,EV_TOKEN(EVENT_ECM,event));
526}
527
528/*
529 * SMT timer interface
530 * stop ECM timer
531 */
532static void stop_ecm_timer(struct s_smc *smc)
533{
534 if (smc->e.ecm_timer.tm_active)
535 smt_timer_stop(smc,&smc->e.ecm_timer) ;
536}
diff --git a/drivers/net/skfp/ess.c b/drivers/net/skfp/ess.c
deleted file mode 100644
index 2fc5987b41dc..000000000000
--- a/drivers/net/skfp/ess.c
+++ /dev/null
@@ -1,720 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 * *******************************************************************
19 * This SBA code implements the Synchronous Bandwidth Allocation
20 * functions described in the "FDDI Synchronous Forum Implementer's
21 * Agreement" dated December 1th, 1993.
22 * *******************************************************************
23 *
24 * PURPOSE: The purpose of this function is to control
25 * synchronous allocations on a single FDDI segment.
26 * Allocations are limited to the primary FDDI ring.
27 * The SBM provides recovery mechanisms to recover
28 * unused bandwidth also resolves T_Neg and
29 * reconfiguration changes. Many of the SBM state
30 * machine inputs are sourced by the underlying
31 * FDDI sub-system supporting the SBA application.
32 *
33 * *******************************************************************
34 */
35
36#include "h/types.h"
37#include "h/fddi.h"
38#include "h/smc.h"
39#include "h/smt_p.h"
40
41
42#ifndef SLIM_SMT
43
44#ifdef ESS
45
46#ifndef lint
47static const char ID_sccs[] = "@(#)ess.c 1.10 96/02/23 (C) SK" ;
48#define LINT_USE(x)
49#else
50#define LINT_USE(x) (x)=(x)
51#endif
52#define MS2BCLK(x) ((x)*12500L)
53
54/*
55 -------------------------------------------------------------
56 LOCAL VARIABLES:
57 -------------------------------------------------------------
58*/
59
60static const u_short plist_raf_alc_res[] = { SMT_P0012, SMT_P320B, SMT_P320F,
61 SMT_P3210, SMT_P0019, SMT_P001A,
62 SMT_P001D, 0 } ;
63
64static const u_short plist_raf_chg_req[] = { SMT_P320B, SMT_P320F, SMT_P3210,
65 SMT_P001A, 0 } ;
66
67static const struct fddi_addr smt_sba_da = {{0x80,0x01,0x43,0x00,0x80,0x0C}} ;
68static const struct fddi_addr null_addr = {{0,0,0,0,0,0}} ;
69
70/*
71 -------------------------------------------------------------
72 GLOBAL VARIABLES:
73 -------------------------------------------------------------
74*/
75
76
77/*
78 -------------------------------------------------------------
79 LOCAL FUNCTIONS:
80 -------------------------------------------------------------
81*/
82
83static void ess_send_response(struct s_smc *smc, struct smt_header *sm,
84 int sba_cmd);
85static void ess_config_fifo(struct s_smc *smc);
86static void ess_send_alc_req(struct s_smc *smc);
87static void ess_send_frame(struct s_smc *smc, SMbuf *mb);
88
89/*
90 -------------------------------------------------------------
91 EXTERNAL FUNCTIONS:
92 -------------------------------------------------------------
93*/
94
95/*
96 -------------------------------------------------------------
97 PUBLIC FUNCTIONS:
98 -------------------------------------------------------------
99*/
100
101void ess_timer_poll(struct s_smc *smc);
102void ess_para_change(struct s_smc *smc);
103int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm,
104 int fs);
105static int process_bw_alloc(struct s_smc *smc, long int payload, long int overhead);
106
107
108/*
109 * --------------------------------------------------------------------------
110 * End Station Support (ESS)
111 * --------------------------------------------------------------------------
112 */
113
114/*
115 * evaluate the RAF frame
116 */
117int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm,
118 int fs)
119{
120 void *p ; /* universal pointer */
121 struct smt_p_0016 *cmd ; /* para: command for the ESS */
122 SMbuf *db ;
123 u_long msg_res_type ; /* recource type */
124 u_long payload, overhead ;
125 int local ;
126 int i ;
127
128 /*
129 * Message Processing Code
130 */
131 local = ((fs & L_INDICATOR) != 0) ;
132
133 /*
134 * get the resource type
135 */
136 if (!(p = (void *) sm_to_para(smc,sm,SMT_P0015))) {
137 DB_ESS("ESS: RAF frame error, parameter type not found\n",0,0) ;
138 return fs;
139 }
140 msg_res_type = ((struct smt_p_0015 *)p)->res_type ;
141
142 /*
143 * get the pointer to the ESS command
144 */
145 if (!(cmd = (struct smt_p_0016 *) sm_to_para(smc,sm,SMT_P0016))) {
146 /*
147 * error in frame: para ESS command was not found
148 */
149 DB_ESS("ESS: RAF frame error, parameter command not found\n",0,0);
150 return fs;
151 }
152
153 DB_ESSN(2,"fc %x ft %x\n",sm->smt_class,sm->smt_type) ;
154 DB_ESSN(2,"ver %x tran %lx\n",sm->smt_version,sm->smt_tid) ;
155 DB_ESSN(2,"stn_id %s\n",addr_to_string(&sm->smt_source),0) ;
156
157 DB_ESSN(2,"infolen %x res %x\n",sm->smt_len, msg_res_type) ;
158 DB_ESSN(2,"sbacmd %x\n",cmd->sba_cmd,0) ;
159
160 /*
161 * evaluate the ESS command
162 */
163 switch (cmd->sba_cmd) {
164
165 /*
166 * Process an ESS Allocation Request
167 */
168 case REQUEST_ALLOCATION :
169 /*
170 * check for an RAF Request (Allocation Request)
171 */
172 if (sm->smt_type == SMT_REQUEST) {
173 /*
174 * process the Allocation request only if the frame is
175 * local and no static allocation is used
176 */
177 if (!local || smc->mib.fddiESSPayload)
178 return fs;
179
180 p = (void *) sm_to_para(smc,sm,SMT_P0019) ;
181 for (i = 0; i < 5; i++) {
182 if (((struct smt_p_0019 *)p)->alloc_addr.a[i]) {
183 return fs;
184 }
185 }
186
187 /*
188 * Note: The Application should send a LAN_LOC_FRAME.
189 * The ESS do not send the Frame to the network!
190 */
191 smc->ess.alloc_trans_id = sm->smt_tid ;
192 DB_ESS("ESS: save Alloc Req Trans ID %lx\n",sm->smt_tid,0);
193 p = (void *) sm_to_para(smc,sm,SMT_P320F) ;
194 ((struct smt_p_320f *)p)->mib_payload =
195 smc->mib.a[PATH0].fddiPATHSbaPayload ;
196 p = (void *) sm_to_para(smc,sm,SMT_P3210) ;
197 ((struct smt_p_3210 *)p)->mib_overhead =
198 smc->mib.a[PATH0].fddiPATHSbaOverhead ;
199 sm->smt_dest = smt_sba_da ;
200
201 if (smc->ess.local_sba_active)
202 return fs | I_INDICATOR;
203
204 if (!(db = smt_get_mbuf(smc)))
205 return fs;
206
207 db->sm_len = mb->sm_len ;
208 db->sm_off = mb->sm_off ;
209 memcpy(((char *)(db->sm_data+db->sm_off)),(char *)sm,
210 (int)db->sm_len) ;
211 dump_smt(smc,
212 (struct smt_header *)(db->sm_data+db->sm_off),
213 "RAF") ;
214 smt_send_frame(smc,db,FC_SMT_INFO,0) ;
215 return fs;
216 }
217
218 /*
219 * The RAF frame is an Allocation Response !
220 * check the parameters
221 */
222 if (smt_check_para(smc,sm,plist_raf_alc_res)) {
223 DB_ESS("ESS: RAF with para problem, ignoring\n",0,0) ;
224 return fs;
225 }
226
227 /*
228 * VERIFY THE FRAME IS WELL BUILT:
229 *
230 * 1. path index = primary ring only
231 * 2. resource type = sync bw only
232 * 3. trans action id = alloc_trans_id
233 * 4. reason code = success
234 *
235 * If any are violated, discard the RAF frame
236 */
237 if ((((struct smt_p_320b *)sm_to_para(smc,sm,SMT_P320B))->path_index
238 != PRIMARY_RING) ||
239 (msg_res_type != SYNC_BW) ||
240 (((struct smt_p_reason *)sm_to_para(smc,sm,SMT_P0012))->rdf_reason
241 != SMT_RDF_SUCCESS) ||
242 (sm->smt_tid != smc->ess.alloc_trans_id)) {
243
244 DB_ESS("ESS: Allocation Response not accepted\n",0,0) ;
245 return fs;
246 }
247
248 /*
249 * Extract message parameters
250 */
251 p = (void *) sm_to_para(smc,sm,SMT_P320F) ;
252 if (!p) {
253 printk(KERN_ERR "ESS: sm_to_para failed");
254 return fs;
255 }
256 payload = ((struct smt_p_320f *)p)->mib_payload ;
257 p = (void *) sm_to_para(smc,sm,SMT_P3210) ;
258 if (!p) {
259 printk(KERN_ERR "ESS: sm_to_para failed");
260 return fs;
261 }
262 overhead = ((struct smt_p_3210 *)p)->mib_overhead ;
263
264 DB_ESSN(2,"payload= %lx overhead= %lx\n",payload,overhead) ;
265
266 /*
267 * process the bandwidth allocation
268 */
269 (void)process_bw_alloc(smc,(long)payload,(long)overhead) ;
270
271 return fs;
272 /* end of Process Allocation Request */
273
274 /*
275 * Process an ESS Change Request
276 */
277 case CHANGE_ALLOCATION :
278 /*
279 * except only replies
280 */
281 if (sm->smt_type != SMT_REQUEST) {
282 DB_ESS("ESS: Do not process Change Responses\n",0,0) ;
283 return fs;
284 }
285
286 /*
287 * check the para for the Change Request
288 */
289 if (smt_check_para(smc,sm,plist_raf_chg_req)) {
290 DB_ESS("ESS: RAF with para problem, ignoring\n",0,0) ;
291 return fs;
292 }
293
294 /*
295 * Verify the path index and resource
296 * type are correct. If any of
297 * these are false, don't process this
298 * change request frame.
299 */
300 if ((((struct smt_p_320b *)sm_to_para(smc,sm,SMT_P320B))->path_index
301 != PRIMARY_RING) || (msg_res_type != SYNC_BW)) {
302 DB_ESS("ESS: RAF frame with para problem, ignoring\n",0,0) ;
303 return fs;
304 }
305
306 /*
307 * Extract message queue parameters
308 */
309 p = (void *) sm_to_para(smc,sm,SMT_P320F) ;
310 payload = ((struct smt_p_320f *)p)->mib_payload ;
311 p = (void *) sm_to_para(smc,sm,SMT_P3210) ;
312 overhead = ((struct smt_p_3210 *)p)->mib_overhead ;
313
314 DB_ESSN(2,"ESS: Change Request from %s\n",
315 addr_to_string(&sm->smt_source),0) ;
316 DB_ESSN(2,"payload= %lx overhead= %lx\n",payload,overhead) ;
317
318 /*
319 * process the bandwidth allocation
320 */
321 if(!process_bw_alloc(smc,(long)payload,(long)overhead))
322 return fs;
323
324 /*
325 * send an RAF Change Reply
326 */
327 ess_send_response(smc,sm,CHANGE_ALLOCATION) ;
328
329 return fs;
330 /* end of Process Change Request */
331
332 /*
333 * Process Report Response
334 */
335 case REPORT_ALLOCATION :
336 /*
337 * except only requests
338 */
339 if (sm->smt_type != SMT_REQUEST) {
340 DB_ESS("ESS: Do not process a Report Reply\n",0,0) ;
341 return fs;
342 }
343
344 DB_ESSN(2,"ESS: Report Request from %s\n",
345 addr_to_string(&(sm->smt_source)),0) ;
346
347 /*
348 * verify that the resource type is sync bw only
349 */
350 if (msg_res_type != SYNC_BW) {
351 DB_ESS("ESS: ignoring RAF with para problem\n",0,0) ;
352 return fs;
353 }
354
355 /*
356 * send an RAF Change Reply
357 */
358 ess_send_response(smc,sm,REPORT_ALLOCATION) ;
359
360 return fs;
361 /* end of Process Report Request */
362
363 default:
364 /*
365 * error in frame
366 */
367 DB_ESS("ESS: ignoring RAF with bad sba_cmd\n",0,0) ;
368 break ;
369 }
370
371 return fs;
372}
373
374/*
375 * determines the synchronous bandwidth, set the TSYNC register and the
376 * mib variables SBAPayload, SBAOverhead and fddiMACT-NEG.
377 */
378static int process_bw_alloc(struct s_smc *smc, long int payload, long int overhead)
379{
380 /*
381 * determine the synchronous bandwidth (sync_bw) in bytes per T-NEG,
382 * if the payload is greater than zero.
383 * For the SBAPayload and the SBAOverhead we have the following
384 * unite quations
385 * _ _
386 * | bytes |
387 * SBAPayload = | 8000 ------ |
388 * | s |
389 * - -
390 * _ _
391 * | bytes |
392 * SBAOverhead = | ------ |
393 * | T-NEG |
394 * - -
395 *
396 * T-NEG is described by the equation:
397 *
398 * (-) fddiMACT-NEG
399 * T-NEG = -------------------
400 * 12500000 1/s
401 *
402 * The number of bytes we are able to send is the payload
403 * plus the overhead.
404 *
405 * bytes T-NEG SBAPayload 8000 bytes/s
406 * sync_bw = SBAOverhead ------ + -----------------------------
407 * T-NEG T-NEG
408 *
409 *
410 * 1
411 * sync_bw = SBAOverhead + ---- (-)fddiMACT-NEG * SBAPayload
412 * 1562
413 *
414 */
415
416 /*
417 * set the mib attributes fddiPATHSbaOverhead, fddiPATHSbaPayload
418 */
419/* if (smt_set_obj(smc,SMT_P320F,payload,S_SET)) {
420 DB_ESS("ESS: SMT does not accept the payload value\n",0,0) ;
421 return FALSE;
422 }
423 if (smt_set_obj(smc,SMT_P3210,overhead,S_SET)) {
424 DB_ESS("ESS: SMT does not accept the overhead value\n",0,0) ;
425 return FALSE;
426 } */
427
428 /* premliminary */
429 if (payload > MAX_PAYLOAD || overhead > 5000) {
430 DB_ESS("ESS: payload / overhead not accepted\n",0,0) ;
431 return FALSE;
432 }
433
434 /*
435 * start the iterative allocation process if the payload or the overhead
436 * are smaller than the parsed values
437 */
438 if (smc->mib.fddiESSPayload &&
439 ((u_long)payload != smc->mib.fddiESSPayload ||
440 (u_long)overhead != smc->mib.fddiESSOverhead)) {
441 smc->ess.raf_act_timer_poll = TRUE ;
442 smc->ess.timer_count = 0 ;
443 }
444
445 /*
446 * evulate the Payload
447 */
448 if (payload) {
449 DB_ESSN(2,"ESS: turn SMT_ST_SYNC_SERVICE bit on\n",0,0) ;
450 smc->ess.sync_bw_available = TRUE ;
451
452 smc->ess.sync_bw = overhead -
453 (long)smc->mib.m[MAC0].fddiMACT_Neg *
454 payload / 1562 ;
455 }
456 else {
457 DB_ESSN(2,"ESS: turn SMT_ST_SYNC_SERVICE bit off\n",0,0) ;
458 smc->ess.sync_bw_available = FALSE ;
459 smc->ess.sync_bw = 0 ;
460 overhead = 0 ;
461 }
462
463 smc->mib.a[PATH0].fddiPATHSbaPayload = payload ;
464 smc->mib.a[PATH0].fddiPATHSbaOverhead = overhead ;
465
466
467 DB_ESSN(2,"tsync = %lx\n",smc->ess.sync_bw,0) ;
468
469 ess_config_fifo(smc) ;
470 set_formac_tsync(smc,smc->ess.sync_bw) ;
471 return TRUE;
472}
473
474static void ess_send_response(struct s_smc *smc, struct smt_header *sm,
475 int sba_cmd)
476{
477 struct smt_sba_chg *chg ;
478 SMbuf *mb ;
479 void *p ;
480
481 /*
482 * get and initialize the response frame
483 */
484 if (sba_cmd == CHANGE_ALLOCATION) {
485 if (!(mb=smt_build_frame(smc,SMT_RAF,SMT_REPLY,
486 sizeof(struct smt_sba_chg))))
487 return ;
488 }
489 else {
490 if (!(mb=smt_build_frame(smc,SMT_RAF,SMT_REPLY,
491 sizeof(struct smt_sba_rep_res))))
492 return ;
493 }
494
495 chg = smtod(mb,struct smt_sba_chg *) ;
496 chg->smt.smt_tid = sm->smt_tid ;
497 chg->smt.smt_dest = sm->smt_source ;
498
499 /* set P15 */
500 chg->s_type.para.p_type = SMT_P0015 ;
501 chg->s_type.para.p_len = sizeof(struct smt_p_0015) - PARA_LEN ;
502 chg->s_type.res_type = SYNC_BW ;
503
504 /* set P16 */
505 chg->cmd.para.p_type = SMT_P0016 ;
506 chg->cmd.para.p_len = sizeof(struct smt_p_0016) - PARA_LEN ;
507 chg->cmd.sba_cmd = sba_cmd ;
508
509 /* set P320B */
510 chg->path.para.p_type = SMT_P320B ;
511 chg->path.para.p_len = sizeof(struct smt_p_320b) - PARA_LEN ;
512 chg->path.mib_index = SBAPATHINDEX ;
513 chg->path.path_pad = 0;
514 chg->path.path_index = PRIMARY_RING ;
515
516 /* set P320F */
517 chg->payload.para.p_type = SMT_P320F ;
518 chg->payload.para.p_len = sizeof(struct smt_p_320f) - PARA_LEN ;
519 chg->payload.mib_index = SBAPATHINDEX ;
520 chg->payload.mib_payload = smc->mib.a[PATH0].fddiPATHSbaPayload ;
521
522 /* set P3210 */
523 chg->overhead.para.p_type = SMT_P3210 ;
524 chg->overhead.para.p_len = sizeof(struct smt_p_3210) - PARA_LEN ;
525 chg->overhead.mib_index = SBAPATHINDEX ;
526 chg->overhead.mib_overhead = smc->mib.a[PATH0].fddiPATHSbaOverhead ;
527
528 if (sba_cmd == CHANGE_ALLOCATION) {
529 /* set P1A */
530 chg->cat.para.p_type = SMT_P001A ;
531 chg->cat.para.p_len = sizeof(struct smt_p_001a) - PARA_LEN ;
532 p = (void *) sm_to_para(smc,sm,SMT_P001A) ;
533 chg->cat.category = ((struct smt_p_001a *)p)->category ;
534 }
535 dump_smt(smc,(struct smt_header *)chg,"RAF") ;
536 ess_send_frame(smc,mb) ;
537}
538
539void ess_timer_poll(struct s_smc *smc)
540{
541 if (!smc->ess.raf_act_timer_poll)
542 return ;
543
544 DB_ESSN(2,"ESS: timer_poll\n",0,0) ;
545
546 smc->ess.timer_count++ ;
547 if (smc->ess.timer_count == 10) {
548 smc->ess.timer_count = 0 ;
549 ess_send_alc_req(smc) ;
550 }
551}
552
553static void ess_send_alc_req(struct s_smc *smc)
554{
555 struct smt_sba_alc_req *req ;
556 SMbuf *mb ;
557
558 /*
559 * send never allocation request where the requested payload and
560 * overhead is zero or deallocate bandwidth when no bandwidth is
561 * parsed
562 */
563 if (!smc->mib.fddiESSPayload) {
564 smc->mib.fddiESSOverhead = 0 ;
565 }
566 else {
567 if (!smc->mib.fddiESSOverhead)
568 smc->mib.fddiESSOverhead = DEFAULT_OV ;
569 }
570
571 if (smc->mib.fddiESSOverhead ==
572 smc->mib.a[PATH0].fddiPATHSbaOverhead &&
573 smc->mib.fddiESSPayload ==
574 smc->mib.a[PATH0].fddiPATHSbaPayload){
575 smc->ess.raf_act_timer_poll = FALSE ;
576 smc->ess.timer_count = 7 ; /* next RAF alc req after 3 s */
577 return ;
578 }
579
580 /*
581 * get and initialize the response frame
582 */
583 if (!(mb=smt_build_frame(smc,SMT_RAF,SMT_REQUEST,
584 sizeof(struct smt_sba_alc_req))))
585 return ;
586 req = smtod(mb,struct smt_sba_alc_req *) ;
587 req->smt.smt_tid = smc->ess.alloc_trans_id = smt_get_tid(smc) ;
588 req->smt.smt_dest = smt_sba_da ;
589
590 /* set P15 */
591 req->s_type.para.p_type = SMT_P0015 ;
592 req->s_type.para.p_len = sizeof(struct smt_p_0015) - PARA_LEN ;
593 req->s_type.res_type = SYNC_BW ;
594
595 /* set P16 */
596 req->cmd.para.p_type = SMT_P0016 ;
597 req->cmd.para.p_len = sizeof(struct smt_p_0016) - PARA_LEN ;
598 req->cmd.sba_cmd = REQUEST_ALLOCATION ;
599
600 /*
601 * set the parameter type and parameter length of all used
602 * parameters
603 */
604
605 /* set P320B */
606 req->path.para.p_type = SMT_P320B ;
607 req->path.para.p_len = sizeof(struct smt_p_320b) - PARA_LEN ;
608 req->path.mib_index = SBAPATHINDEX ;
609 req->path.path_pad = 0;
610 req->path.path_index = PRIMARY_RING ;
611
612 /* set P0017 */
613 req->pl_req.para.p_type = SMT_P0017 ;
614 req->pl_req.para.p_len = sizeof(struct smt_p_0017) - PARA_LEN ;
615 req->pl_req.sba_pl_req = smc->mib.fddiESSPayload -
616 smc->mib.a[PATH0].fddiPATHSbaPayload ;
617
618 /* set P0018 */
619 req->ov_req.para.p_type = SMT_P0018 ;
620 req->ov_req.para.p_len = sizeof(struct smt_p_0018) - PARA_LEN ;
621 req->ov_req.sba_ov_req = smc->mib.fddiESSOverhead -
622 smc->mib.a[PATH0].fddiPATHSbaOverhead ;
623
624 /* set P320F */
625 req->payload.para.p_type = SMT_P320F ;
626 req->payload.para.p_len = sizeof(struct smt_p_320f) - PARA_LEN ;
627 req->payload.mib_index = SBAPATHINDEX ;
628 req->payload.mib_payload = smc->mib.a[PATH0].fddiPATHSbaPayload ;
629
630 /* set P3210 */
631 req->overhead.para.p_type = SMT_P3210 ;
632 req->overhead.para.p_len = sizeof(struct smt_p_3210) - PARA_LEN ;
633 req->overhead.mib_index = SBAPATHINDEX ;
634 req->overhead.mib_overhead = smc->mib.a[PATH0].fddiPATHSbaOverhead ;
635
636 /* set P19 */
637 req->a_addr.para.p_type = SMT_P0019 ;
638 req->a_addr.para.p_len = sizeof(struct smt_p_0019) - PARA_LEN ;
639 req->a_addr.sba_pad = 0;
640 req->a_addr.alloc_addr = null_addr ;
641
642 /* set P1A */
643 req->cat.para.p_type = SMT_P001A ;
644 req->cat.para.p_len = sizeof(struct smt_p_001a) - PARA_LEN ;
645 req->cat.category = smc->mib.fddiESSCategory ;
646
647 /* set P1B */
648 req->tneg.para.p_type = SMT_P001B ;
649 req->tneg.para.p_len = sizeof(struct smt_p_001b) - PARA_LEN ;
650 req->tneg.max_t_neg = smc->mib.fddiESSMaxTNeg ;
651
652 /* set P1C */
653 req->segm.para.p_type = SMT_P001C ;
654 req->segm.para.p_len = sizeof(struct smt_p_001c) - PARA_LEN ;
655 req->segm.min_seg_siz = smc->mib.fddiESSMinSegmentSize ;
656
657 dump_smt(smc,(struct smt_header *)req,"RAF") ;
658 ess_send_frame(smc,mb) ;
659}
660
661static void ess_send_frame(struct s_smc *smc, SMbuf *mb)
662{
663 /*
664 * check if the frame must be send to the own ESS
665 */
666 if (smc->ess.local_sba_active) {
667 /*
668 * Send the Change Reply to the local SBA
669 */
670 DB_ESS("ESS:Send to the local SBA\n",0,0) ;
671 if (!smc->ess.sba_reply_pend)
672 smc->ess.sba_reply_pend = mb ;
673 else {
674 DB_ESS("Frame is lost - another frame was pending\n",0,0);
675 smt_free_mbuf(smc,mb) ;
676 }
677 }
678 else {
679 /*
680 * Send the SBA RAF Change Reply to the network
681 */
682 DB_ESS("ESS:Send to the network\n",0,0) ;
683 smt_send_frame(smc,mb,FC_SMT_INFO,0) ;
684 }
685}
686
687void ess_para_change(struct s_smc *smc)
688{
689 (void)process_bw_alloc(smc,(long)smc->mib.a[PATH0].fddiPATHSbaPayload,
690 (long)smc->mib.a[PATH0].fddiPATHSbaOverhead) ;
691}
692
693static void ess_config_fifo(struct s_smc *smc)
694{
695 /*
696 * if nothing to do exit
697 */
698 if (smc->mib.a[PATH0].fddiPATHSbaPayload) {
699 if (smc->hw.fp.fifo.fifo_config_mode & SYNC_TRAFFIC_ON &&
700 (smc->hw.fp.fifo.fifo_config_mode&SEND_ASYNC_AS_SYNC) ==
701 smc->mib.fddiESSSynchTxMode) {
702 return ;
703 }
704 }
705 else {
706 if (!(smc->hw.fp.fifo.fifo_config_mode & SYNC_TRAFFIC_ON)) {
707 return ;
708 }
709 }
710
711 /*
712 * split up the FIFO and reinitialize the queues
713 */
714 formac_reinit_tx(smc) ;
715}
716
717#endif /* ESS */
718
719#endif /* no SLIM_SMT */
720
diff --git a/drivers/net/skfp/fplustm.c b/drivers/net/skfp/fplustm.c
deleted file mode 100644
index a20ed1a98099..000000000000
--- a/drivers/net/skfp/fplustm.c
+++ /dev/null
@@ -1,1491 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 * FORMAC+ Driver for tag mode
19 */
20
21#include "h/types.h"
22#include "h/fddi.h"
23#include "h/smc.h"
24#include "h/supern_2.h"
25#include <linux/bitrev.h>
26
27#ifndef lint
28static const char ID_sccs[] = "@(#)fplustm.c 1.32 99/02/23 (C) SK " ;
29#endif
30
31#ifndef UNUSED
32#ifdef lint
33#define UNUSED(x) (x) = (x)
34#else
35#define UNUSED(x)
36#endif
37#endif
38
39#define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
40#define MS2BCLK(x) ((x)*12500L)
41#define US2BCLK(x) ((x)*1250L)
42
43/*
44 * prototypes for static function
45 */
46static void build_claim_beacon(struct s_smc *smc, u_long t_request);
47static int init_mac(struct s_smc *smc, int all);
48static void rtm_init(struct s_smc *smc);
49static void smt_split_up_fifo(struct s_smc *smc);
50
51#if (!defined(NO_SMT_PANIC) || defined(DEBUG))
52static char write_mdr_warning [] = "E350 write_mdr() FM_SNPPND is set\n";
53static char cam_warning [] = "E_SMT_004: CAM still busy\n";
54#endif
55
56#define DUMMY_READ() smc->hw.mc_dummy = (u_short) inp(ADDR(B0_RAP))
57
58#define CHECK_NPP() { unsigned k = 10000 ;\
59 while ((inpw(FM_A(FM_STMCHN)) & FM_SNPPND) && k) k--;\
60 if (!k) { \
61 SMT_PANIC(smc,SMT_E0130, SMT_E0130_MSG) ; \
62 } \
63 }
64
65#define CHECK_CAM() { unsigned k = 10 ;\
66 while (!(inpw(FM_A(FM_AFSTAT)) & FM_DONE) && k) k--;\
67 if (!k) { \
68 SMT_PANIC(smc,SMT_E0131, SMT_E0131_MSG) ; \
69 } \
70 }
71
72const struct fddi_addr fddi_broadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
73static const struct fddi_addr null_addr = {{0,0,0,0,0,0}};
74static const struct fddi_addr dbeacon_multi = {{0x01,0x80,0xc2,0x00,0x01,0x00}};
75
76static const u_short my_said = 0xffff ; /* short address (n.u.) */
77static const u_short my_sagp = 0xffff ; /* short group address (n.u.) */
78
79/*
80 * define my address
81 */
82#ifdef USE_CAN_ADDR
83#define MA smc->hw.fddi_canon_addr
84#else
85#define MA smc->hw.fddi_home_addr
86#endif
87
88
89/*
90 * useful interrupt bits
91 */
92static const int mac_imsk1u = FM_STXABRS | FM_STXABRA0 | FM_SXMTABT ;
93static const int mac_imsk1l = FM_SQLCKS | FM_SQLCKA0 | FM_SPCEPDS | FM_SPCEPDA0|
94 FM_STBURS | FM_STBURA0 ;
95
96 /* delete FM_SRBFL after tests */
97static const int mac_imsk2u = FM_SERRSF | FM_SNFSLD | FM_SRCVOVR | FM_SRBFL |
98 FM_SMYCLM ;
99static const int mac_imsk2l = FM_STRTEXR | FM_SDUPCLM | FM_SFRMCTR |
100 FM_SERRCTR | FM_SLSTCTR |
101 FM_STRTEXP | FM_SMULTDA | FM_SRNGOP ;
102
103static const int mac_imsk3u = FM_SRCVOVR2 | FM_SRBFL2 ;
104static const int mac_imsk3l = FM_SRPERRQ2 | FM_SRPERRQ1 ;
105
106static const int mac_beacon_imsk2u = FM_SOTRBEC | FM_SMYBEC | FM_SBEC |
107 FM_SLOCLM | FM_SHICLM | FM_SMYCLM | FM_SCLM ;
108
109
110static u_long mac_get_tneg(struct s_smc *smc)
111{
112 u_long tneg ;
113
114 tneg = (u_long)((long)inpw(FM_A(FM_TNEG))<<5) ;
115 return (u_long)((tneg + ((inpw(FM_A(FM_TMRS))>>10)&0x1f)) |
116 0xffe00000L) ;
117}
118
119void mac_update_counter(struct s_smc *smc)
120{
121 smc->mib.m[MAC0].fddiMACFrame_Ct =
122 (smc->mib.m[MAC0].fddiMACFrame_Ct & 0xffff0000L)
123 + (u_short) inpw(FM_A(FM_FCNTR)) ;
124 smc->mib.m[MAC0].fddiMACLost_Ct =
125 (smc->mib.m[MAC0].fddiMACLost_Ct & 0xffff0000L)
126 + (u_short) inpw(FM_A(FM_LCNTR)) ;
127 smc->mib.m[MAC0].fddiMACError_Ct =
128 (smc->mib.m[MAC0].fddiMACError_Ct & 0xffff0000L)
129 + (u_short) inpw(FM_A(FM_ECNTR)) ;
130 smc->mib.m[MAC0].fddiMACT_Neg = mac_get_tneg(smc) ;
131#ifdef SMT_REAL_TOKEN_CT
132 /*
133 * If the token counter is emulated it is updated in smt_event.
134 */
135 TBD
136#else
137 smt_emulate_token_ct( smc, MAC0 );
138#endif
139}
140
141/*
142 * write long value into buffer memory over memory data register (MDR),
143 */
144static void write_mdr(struct s_smc *smc, u_long val)
145{
146 CHECK_NPP() ;
147 MDRW(val) ;
148}
149
150#if 0
151/*
152 * read long value from buffer memory over memory data register (MDR),
153 */
154static u_long read_mdr(struct s_smc *smc, unsigned int addr)
155{
156 long p ;
157 CHECK_NPP() ;
158 MARR(addr) ;
159 outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ;
160 CHECK_NPP() ; /* needed for PCI to prevent from timeing violations */
161/* p = MDRR() ; */ /* bad read values if the workaround */
162 /* smc->hw.mc_dummy = *((short volatile far *)(addr)))*/
163 /* is used */
164 p = (u_long)inpw(FM_A(FM_MDRU))<<16 ;
165 p += (u_long)inpw(FM_A(FM_MDRL)) ;
166 return p;
167}
168#endif
169
170/*
171 * clear buffer memory
172 */
173static void init_ram(struct s_smc *smc)
174{
175 u_short i ;
176
177 smc->hw.fp.fifo.rbc_ram_start = 0 ;
178 smc->hw.fp.fifo.rbc_ram_end =
179 smc->hw.fp.fifo.rbc_ram_start + RBC_MEM_SIZE ;
180 CHECK_NPP() ;
181 MARW(smc->hw.fp.fifo.rbc_ram_start) ;
182 for (i = smc->hw.fp.fifo.rbc_ram_start;
183 i < (u_short) (smc->hw.fp.fifo.rbc_ram_end-1); i++)
184 write_mdr(smc,0L) ;
185 /* Erase the last byte too */
186 write_mdr(smc,0L) ;
187}
188
189/*
190 * set receive FIFO pointer
191 */
192static void set_recvptr(struct s_smc *smc)
193{
194 /*
195 * initialize the pointer for receive queue 1
196 */
197 outpw(FM_A(FM_RPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* RPR1 */
198 outpw(FM_A(FM_SWPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* SWPR1 */
199 outpw(FM_A(FM_WPR1),smc->hw.fp.fifo.rx1_fifo_start) ; /* WPR1 */
200 outpw(FM_A(FM_EARV1),smc->hw.fp.fifo.tx_s_start-1) ; /* EARV1 */
201
202 /*
203 * initialize the pointer for receive queue 2
204 */
205 if (smc->hw.fp.fifo.rx2_fifo_size) {
206 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
207 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
208 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rx2_fifo_start) ;
209 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
210 }
211 else {
212 outpw(FM_A(FM_RPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
213 outpw(FM_A(FM_SWPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
214 outpw(FM_A(FM_WPR2),smc->hw.fp.fifo.rbc_ram_end-1) ;
215 outpw(FM_A(FM_EARV2),smc->hw.fp.fifo.rbc_ram_end-1) ;
216 }
217}
218
219/*
220 * set transmit FIFO pointer
221 */
222static void set_txptr(struct s_smc *smc)
223{
224 outpw(FM_A(FM_CMDREG2),FM_IRSTQ) ; /* reset transmit queues */
225
226 /*
227 * initialize the pointer for asynchronous transmit queue
228 */
229 outpw(FM_A(FM_RPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* RPXA0 */
230 outpw(FM_A(FM_SWPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* SWPXA0 */
231 outpw(FM_A(FM_WPXA0),smc->hw.fp.fifo.tx_a0_start) ; /* WPXA0 */
232 outpw(FM_A(FM_EAA0),smc->hw.fp.fifo.rx2_fifo_start-1) ; /* EAA0 */
233
234 /*
235 * initialize the pointer for synchronous transmit queue
236 */
237 if (smc->hw.fp.fifo.tx_s_size) {
238 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_s_start) ;
239 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_s_start) ;
240 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_s_start) ;
241 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
242 }
243 else {
244 outpw(FM_A(FM_RPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
245 outpw(FM_A(FM_SWPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
246 outpw(FM_A(FM_WPXS),smc->hw.fp.fifo.tx_a0_start-1) ;
247 outpw(FM_A(FM_EAS),smc->hw.fp.fifo.tx_a0_start-1) ;
248 }
249}
250
251/*
252 * init memory buffer management registers
253 */
254static void init_rbc(struct s_smc *smc)
255{
256 u_short rbc_ram_addr ;
257
258 /*
259 * set unused pointers or permanent pointers
260 */
261 rbc_ram_addr = smc->hw.fp.fifo.rx2_fifo_start - 1 ;
262
263 outpw(FM_A(FM_RPXA1),rbc_ram_addr) ; /* a1-send pointer */
264 outpw(FM_A(FM_WPXA1),rbc_ram_addr) ;
265 outpw(FM_A(FM_SWPXA1),rbc_ram_addr) ;
266 outpw(FM_A(FM_EAA1),rbc_ram_addr) ;
267
268 set_recvptr(smc) ;
269 set_txptr(smc) ;
270}
271
272/*
273 * init rx pointer
274 */
275static void init_rx(struct s_smc *smc)
276{
277 struct s_smt_rx_queue *queue ;
278
279 /*
280 * init all tx data structures for receive queue 1
281 */
282 smc->hw.fp.rx[QUEUE_R1] = queue = &smc->hw.fp.rx_q[QUEUE_R1] ;
283 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R1_CSR) ;
284 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R1_DA) ;
285
286 /*
287 * init all tx data structures for receive queue 2
288 */
289 smc->hw.fp.rx[QUEUE_R2] = queue = &smc->hw.fp.rx_q[QUEUE_R2] ;
290 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R2_CSR) ;
291 queue->rx_bmu_dsc = (HW_PTR) ADDR(B4_R2_DA) ;
292}
293
294/*
295 * set the TSYNC register of the FORMAC to regulate synchronous transmission
296 */
297void set_formac_tsync(struct s_smc *smc, long sync_bw)
298{
299 outpw(FM_A(FM_TSYNC),(unsigned int) (((-sync_bw) >> 5) & 0xffff) ) ;
300}
301
302/*
303 * init all tx data structures
304 */
305static void init_tx(struct s_smc *smc)
306{
307 struct s_smt_tx_queue *queue ;
308
309 /*
310 * init all tx data structures for the synchronous queue
311 */
312 smc->hw.fp.tx[QUEUE_S] = queue = &smc->hw.fp.tx_q[QUEUE_S] ;
313 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XS_CSR) ;
314 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XS_DA) ;
315
316#ifdef ESS
317 set_formac_tsync(smc,smc->ess.sync_bw) ;
318#endif
319
320 /*
321 * init all tx data structures for the asynchronous queue 0
322 */
323 smc->hw.fp.tx[QUEUE_A0] = queue = &smc->hw.fp.tx_q[QUEUE_A0] ;
324 queue->tx_bmu_ctl = (HW_PTR) ADDR(B0_XA_CSR) ;
325 queue->tx_bmu_dsc = (HW_PTR) ADDR(B5_XA_DA) ;
326
327
328 llc_recover_tx(smc) ;
329}
330
331static void mac_counter_init(struct s_smc *smc)
332{
333 int i ;
334 u_long *ec ;
335
336 /*
337 * clear FORMAC+ frame-, lost- and error counter
338 */
339 outpw(FM_A(FM_FCNTR),0) ;
340 outpw(FM_A(FM_LCNTR),0) ;
341 outpw(FM_A(FM_ECNTR),0) ;
342 /*
343 * clear internal error counter structure
344 */
345 ec = (u_long *)&smc->hw.fp.err_stats ;
346 for (i = (sizeof(struct err_st)/sizeof(long)) ; i ; i--)
347 *ec++ = 0L ;
348 smc->mib.m[MAC0].fddiMACRingOp_Ct = 0 ;
349}
350
351/*
352 * set FORMAC address, and t_request
353 */
354static void set_formac_addr(struct s_smc *smc)
355{
356 long t_requ = smc->mib.m[MAC0].fddiMACT_Req ;
357
358 outpw(FM_A(FM_SAID),my_said) ; /* set short address */
359 outpw(FM_A(FM_LAIL),(unsigned)((smc->hw.fddi_home_addr.a[4]<<8) +
360 smc->hw.fddi_home_addr.a[5])) ;
361 outpw(FM_A(FM_LAIC),(unsigned)((smc->hw.fddi_home_addr.a[2]<<8) +
362 smc->hw.fddi_home_addr.a[3])) ;
363 outpw(FM_A(FM_LAIM),(unsigned)((smc->hw.fddi_home_addr.a[0]<<8) +
364 smc->hw.fddi_home_addr.a[1])) ;
365
366 outpw(FM_A(FM_SAGP),my_sagp) ; /* set short group address */
367
368 outpw(FM_A(FM_LAGL),(unsigned)((smc->hw.fp.group_addr.a[4]<<8) +
369 smc->hw.fp.group_addr.a[5])) ;
370 outpw(FM_A(FM_LAGC),(unsigned)((smc->hw.fp.group_addr.a[2]<<8) +
371 smc->hw.fp.group_addr.a[3])) ;
372 outpw(FM_A(FM_LAGM),(unsigned)((smc->hw.fp.group_addr.a[0]<<8) +
373 smc->hw.fp.group_addr.a[1])) ;
374
375 /* set r_request regs. (MSW & LSW of TRT ) */
376 outpw(FM_A(FM_TREQ1),(unsigned)(t_requ>>16)) ;
377 outpw(FM_A(FM_TREQ0),(unsigned)t_requ) ;
378}
379
380static void set_int(char *p, int l)
381{
382 p[0] = (char)(l >> 24) ;
383 p[1] = (char)(l >> 16) ;
384 p[2] = (char)(l >> 8) ;
385 p[3] = (char)(l >> 0) ;
386}
387
388/*
389 * copy TX descriptor to buffer mem
390 * append FC field and MAC frame
391 * if more bit is set in descr
392 * append pointer to descriptor (endless loop)
393 * else
394 * append 'end of chain' pointer
395 */
396static void copy_tx_mac(struct s_smc *smc, u_long td, struct fddi_mac *mac,
397 unsigned off, int len)
398/* u_long td; transmit descriptor */
399/* struct fddi_mac *mac; mac frame pointer */
400/* unsigned off; start address within buffer memory */
401/* int len ; length of the frame including the FC */
402{
403 int i ;
404 __le32 *p ;
405
406 CHECK_NPP() ;
407 MARW(off) ; /* set memory address reg for writes */
408
409 p = (__le32 *) mac ;
410 for (i = (len + 3)/4 ; i ; i--) {
411 if (i == 1) {
412 /* last word, set the tag bit */
413 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ;
414 }
415 write_mdr(smc,le32_to_cpu(*p)) ;
416 p++ ;
417 }
418
419 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
420 write_mdr(smc,td) ; /* write over memory data reg to buffer */
421}
422
423/*
424 BEGIN_MANUAL_ENTRY(module;tests;3)
425 How to test directed beacon frames
426 ----------------------------------------------------------------
427
428 o Insert a break point in the function build_claim_beacon()
429 before calling copy_tx_mac() for building the claim frame.
430 o Modify the RM3_DETECT case so that the RM6_DETECT state
431 will always entered from the RM3_DETECT state (function rmt_fsm(),
432 rmt.c)
433 o Compile the driver.
434 o Set the parameter TREQ in the protocol.ini or net.cfg to a
435 small value to make sure your station will win the claim
436 process.
437 o Start the driver.
438 o When you reach the break point, modify the SA and DA address
439 of the claim frame (e.g. SA = DA = 10005affffff).
440 o When you see RM3_DETECT and RM6_DETECT, observe the direct
441 beacon frames on the UPPSLANA.
442
443 END_MANUAL_ENTRY
444 */
445static void directed_beacon(struct s_smc *smc)
446{
447 SK_LOC_DECL(__le32,a[2]) ;
448
449 /*
450 * set UNA in frame
451 * enable FORMAC to send endless queue of directed beacon
452 * important: the UNA starts at byte 1 (not at byte 0)
453 */
454 * (char *) a = (char) ((long)DBEACON_INFO<<24L) ;
455 a[1] = 0 ;
456 memcpy((char *)a+1,(char *) &smc->mib.m[MAC0].fddiMACUpstreamNbr,6) ;
457
458 CHECK_NPP() ;
459 /* set memory address reg for writes */
460 MARW(smc->hw.fp.fifo.rbc_ram_start+DBEACON_FRAME_OFF+4) ;
461 write_mdr(smc,le32_to_cpu(a[0])) ;
462 outpw(FM_A(FM_CMDREG2),FM_ISTTB) ; /* set the tag bit */
463 write_mdr(smc,le32_to_cpu(a[1])) ;
464
465 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF) ;
466}
467
468/*
469 setup claim & beacon pointer
470 NOTE :
471 special frame packets end with a pointer to their own
472 descriptor, and the MORE bit is set in the descriptor
473*/
474static void build_claim_beacon(struct s_smc *smc, u_long t_request)
475{
476 u_int td ;
477 int len ;
478 struct fddi_mac_sf *mac ;
479
480 /*
481 * build claim packet
482 */
483 len = 17 ;
484 td = TX_DESCRIPTOR | ((((u_int)len-1)&3)<<27) ;
485 mac = &smc->hw.fp.mac_sfb ;
486 mac->mac_fc = FC_CLAIM ;
487 /* DA == SA in claim frame */
488 mac->mac_source = mac->mac_dest = MA ;
489 /* 2's complement */
490 set_int((char *)mac->mac_info,(int)t_request) ;
491
492 copy_tx_mac(smc,td,(struct fddi_mac *)mac,
493 smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF,len) ;
494 /* set CLAIM start pointer */
495 outpw(FM_A(FM_SACL),smc->hw.fp.fifo.rbc_ram_start + CLAIM_FRAME_OFF) ;
496
497 /*
498 * build beacon packet
499 */
500 len = 17 ;
501 td = TX_DESCRIPTOR | ((((u_int)len-1)&3)<<27) ;
502 mac->mac_fc = FC_BEACON ;
503 mac->mac_source = MA ;
504 mac->mac_dest = null_addr ; /* DA == 0 in beacon frame */
505 set_int((char *) mac->mac_info,((int)BEACON_INFO<<24) + 0 ) ;
506
507 copy_tx_mac(smc,td,(struct fddi_mac *)mac,
508 smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF,len) ;
509 /* set beacon start pointer */
510 outpw(FM_A(FM_SABC),smc->hw.fp.fifo.rbc_ram_start + BEACON_FRAME_OFF) ;
511
512 /*
513 * build directed beacon packet
514 * contains optional UNA
515 */
516 len = 23 ;
517 td = TX_DESCRIPTOR | ((((u_int)len-1)&3)<<27) ;
518 mac->mac_fc = FC_BEACON ;
519 mac->mac_source = MA ;
520 mac->mac_dest = dbeacon_multi ; /* multicast */
521 set_int((char *) mac->mac_info,((int)DBEACON_INFO<<24) + 0 ) ;
522 set_int((char *) mac->mac_info+4,0) ;
523 set_int((char *) mac->mac_info+8,0) ;
524
525 copy_tx_mac(smc,td,(struct fddi_mac *)mac,
526 smc->hw.fp.fifo.rbc_ram_start + DBEACON_FRAME_OFF,len) ;
527
528 /* end of claim/beacon queue */
529 outpw(FM_A(FM_EACB),smc->hw.fp.fifo.rx1_fifo_start-1) ;
530
531 outpw(FM_A(FM_WPXSF),0) ;
532 outpw(FM_A(FM_RPXSF),0) ;
533}
534
535static void formac_rcv_restart(struct s_smc *smc)
536{
537 /* enable receive function */
538 SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
539
540 outpw(FM_A(FM_CMDREG1),FM_ICLLR) ; /* clear receive lock */
541}
542
543void formac_tx_restart(struct s_smc *smc)
544{
545 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
546 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
547}
548
549static void enable_formac(struct s_smc *smc)
550{
551 /* set formac IMSK : 0 enables irq */
552 outpw(FM_A(FM_IMSK1U),(unsigned short)~mac_imsk1u);
553 outpw(FM_A(FM_IMSK1L),(unsigned short)~mac_imsk1l);
554 outpw(FM_A(FM_IMSK2U),(unsigned short)~mac_imsk2u);
555 outpw(FM_A(FM_IMSK2L),(unsigned short)~mac_imsk2l);
556 outpw(FM_A(FM_IMSK3U),(unsigned short)~mac_imsk3u);
557 outpw(FM_A(FM_IMSK3L),(unsigned short)~mac_imsk3l);
558}
559
560#if 0 /* Removed because the driver should use the ASICs TX complete IRQ. */
561 /* The FORMACs tx complete IRQ should be used any longer */
562
563/*
564 BEGIN_MANUAL_ENTRY(if,func;others;4)
565
566 void enable_tx_irq(smc, queue)
567 struct s_smc *smc ;
568 u_short queue ;
569
570Function DOWNCALL (SMT, fplustm.c)
571 enable_tx_irq() enables the FORMACs transmit complete
572 interrupt of the queue.
573
574Para queue = QUEUE_S: synchronous queue
575 = QUEUE_A0: asynchronous queue
576
577Note After any ring operational change the transmit complete
578 interrupts are disabled.
579 The operating system dependent module must enable
580 the transmit complete interrupt of a queue,
581 - when it queues the first frame,
582 because of no transmit resources are beeing
583 available and
584 - when it escapes from the function llc_restart_tx
585 while some frames are still queued.
586
587 END_MANUAL_ENTRY
588 */
589void enable_tx_irq(struct s_smc *smc, u_short queue)
590/* u_short queue; 0 = synchronous queue, 1 = asynchronous queue 0 */
591{
592 u_short imask ;
593
594 imask = ~(inpw(FM_A(FM_IMSK1U))) ;
595
596 if (queue == 0) {
597 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMS)) ;
598 }
599 if (queue == 1) {
600 outpw(FM_A(FM_IMSK1U),~(imask|FM_STEFRMA0)) ;
601 }
602}
603
604/*
605 BEGIN_MANUAL_ENTRY(if,func;others;4)
606
607 void disable_tx_irq(smc, queue)
608 struct s_smc *smc ;
609 u_short queue ;
610
611Function DOWNCALL (SMT, fplustm.c)
612 disable_tx_irq disables the FORMACs transmit complete
613 interrupt of the queue
614
615Para queue = QUEUE_S: synchronous queue
616 = QUEUE_A0: asynchronous queue
617
618Note The operating system dependent module should disable
619 the transmit complete interrupts if it escapes from the
620 function llc_restart_tx and no frames are queued.
621
622 END_MANUAL_ENTRY
623 */
624void disable_tx_irq(struct s_smc *smc, u_short queue)
625/* u_short queue; 0 = synchronous queue, 1 = asynchronous queue 0 */
626{
627 u_short imask ;
628
629 imask = ~(inpw(FM_A(FM_IMSK1U))) ;
630
631 if (queue == 0) {
632 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMS)) ;
633 }
634 if (queue == 1) {
635 outpw(FM_A(FM_IMSK1U),~(imask&~FM_STEFRMA0)) ;
636 }
637}
638#endif
639
640static void disable_formac(struct s_smc *smc)
641{
642 /* clear formac IMSK : 1 disables irq */
643 outpw(FM_A(FM_IMSK1U),MW) ;
644 outpw(FM_A(FM_IMSK1L),MW) ;
645 outpw(FM_A(FM_IMSK2U),MW) ;
646 outpw(FM_A(FM_IMSK2L),MW) ;
647 outpw(FM_A(FM_IMSK3U),MW) ;
648 outpw(FM_A(FM_IMSK3L),MW) ;
649}
650
651
652static void mac_ring_up(struct s_smc *smc, int up)
653{
654 if (up) {
655 formac_rcv_restart(smc) ; /* enable receive function */
656 smc->hw.mac_ring_is_up = TRUE ;
657 llc_restart_tx(smc) ; /* TX queue */
658 }
659 else {
660 /* disable receive function */
661 SETMASK(FM_A(FM_MDREG1),FM_MDISRCV,FM_ADDET) ;
662
663 /* abort current transmit activity */
664 outpw(FM_A(FM_CMDREG2),FM_IACTR) ;
665
666 smc->hw.mac_ring_is_up = FALSE ;
667 }
668}
669
670/*--------------------------- ISR handling ----------------------------------*/
671/*
672 * mac1_irq is in drvfbi.c
673 */
674
675/*
676 * mac2_irq: status bits for the receive queue 1, and ring status
677 * ring status indication bits
678 */
679void mac2_irq(struct s_smc *smc, u_short code_s2u, u_short code_s2l)
680{
681 u_short change_s2l ;
682 u_short change_s2u ;
683
684 /* (jd) 22-Feb-1999
685 * Restart 2_DMax Timer after end of claiming or beaconing
686 */
687 if (code_s2u & (FM_SCLM|FM_SHICLM|FM_SBEC|FM_SOTRBEC)) {
688 queue_event(smc,EVENT_RMT,RM_TX_STATE_CHANGE) ;
689 }
690 else if (code_s2l & (FM_STKISS)) {
691 queue_event(smc,EVENT_RMT,RM_TX_STATE_CHANGE) ;
692 }
693
694 /*
695 * XOR current st bits with the last to avoid useless RMT event queuing
696 */
697 change_s2l = smc->hw.fp.s2l ^ code_s2l ;
698 change_s2u = smc->hw.fp.s2u ^ code_s2u ;
699
700 if ((change_s2l & FM_SRNGOP) ||
701 (!smc->hw.mac_ring_is_up && ((code_s2l & FM_SRNGOP)))) {
702 if (code_s2l & FM_SRNGOP) {
703 mac_ring_up(smc,1) ;
704 queue_event(smc,EVENT_RMT,RM_RING_OP) ;
705 smc->mib.m[MAC0].fddiMACRingOp_Ct++ ;
706 }
707 else {
708 mac_ring_up(smc,0) ;
709 queue_event(smc,EVENT_RMT,RM_RING_NON_OP) ;
710 }
711 goto mac2_end ;
712 }
713 if (code_s2l & FM_SMISFRM) { /* missed frame */
714 smc->mib.m[MAC0].fddiMACNotCopied_Ct++ ;
715 }
716 if (code_s2u & (FM_SRCVOVR | /* recv. FIFO overflow */
717 FM_SRBFL)) { /* recv. buffer full */
718 smc->hw.mac_ct.mac_r_restart_counter++ ;
719/* formac_rcv_restart(smc) ; */
720 smt_stat_counter(smc,1) ;
721/* goto mac2_end ; */
722 }
723 if (code_s2u & FM_SOTRBEC)
724 queue_event(smc,EVENT_RMT,RM_OTHER_BEACON) ;
725 if (code_s2u & FM_SMYBEC)
726 queue_event(smc,EVENT_RMT,RM_MY_BEACON) ;
727 if (change_s2u & code_s2u & FM_SLOCLM) {
728 DB_RMTN(2,"RMT : lower claim received\n",0,0) ;
729 }
730 if ((code_s2u & FM_SMYCLM) && !(code_s2l & FM_SDUPCLM)) {
731 /*
732 * This is my claim and that claim is not detected as a
733 * duplicate one.
734 */
735 queue_event(smc,EVENT_RMT,RM_MY_CLAIM) ;
736 }
737 if (code_s2l & FM_SDUPCLM) {
738 /*
739 * If a duplicate claim frame (same SA but T_Bid != T_Req)
740 * this flag will be set.
741 * In the RMT state machine we need a RM_VALID_CLAIM event
742 * to do the appropriate state change.
743 * RM(34c)
744 */
745 queue_event(smc,EVENT_RMT,RM_VALID_CLAIM) ;
746 }
747 if (change_s2u & code_s2u & FM_SHICLM) {
748 DB_RMTN(2,"RMT : higher claim received\n",0,0) ;
749 }
750 if ( (code_s2l & FM_STRTEXP) ||
751 (code_s2l & FM_STRTEXR) )
752 queue_event(smc,EVENT_RMT,RM_TRT_EXP) ;
753 if (code_s2l & FM_SMULTDA) {
754 /*
755 * The MAC has found a 2. MAC with the same address.
756 * Signal dup_addr_test = failed to RMT state machine.
757 * RM(25)
758 */
759 smc->r.dup_addr_test = DA_FAILED ;
760 queue_event(smc,EVENT_RMT,RM_DUP_ADDR) ;
761 }
762 if (code_s2u & FM_SBEC)
763 smc->hw.fp.err_stats.err_bec_stat++ ;
764 if (code_s2u & FM_SCLM)
765 smc->hw.fp.err_stats.err_clm_stat++ ;
766 if (code_s2l & FM_STVXEXP)
767 smc->mib.m[MAC0].fddiMACTvxExpired_Ct++ ;
768 if ((code_s2u & (FM_SBEC|FM_SCLM))) {
769 if (!(change_s2l & FM_SRNGOP) && (smc->hw.fp.s2l & FM_SRNGOP)) {
770 mac_ring_up(smc,0) ;
771 queue_event(smc,EVENT_RMT,RM_RING_NON_OP) ;
772
773 mac_ring_up(smc,1) ;
774 queue_event(smc,EVENT_RMT,RM_RING_OP) ;
775 smc->mib.m[MAC0].fddiMACRingOp_Ct++ ;
776 }
777 }
778 if (code_s2l & FM_SPHINV)
779 smc->hw.fp.err_stats.err_phinv++ ;
780 if (code_s2l & FM_SSIFG)
781 smc->hw.fp.err_stats.err_sifg_det++ ;
782 if (code_s2l & FM_STKISS)
783 smc->hw.fp.err_stats.err_tkiss++ ;
784 if (code_s2l & FM_STKERR)
785 smc->hw.fp.err_stats.err_tkerr++ ;
786 if (code_s2l & FM_SFRMCTR)
787 smc->mib.m[MAC0].fddiMACFrame_Ct += 0x10000L ;
788 if (code_s2l & FM_SERRCTR)
789 smc->mib.m[MAC0].fddiMACError_Ct += 0x10000L ;
790 if (code_s2l & FM_SLSTCTR)
791 smc->mib.m[MAC0].fddiMACLost_Ct += 0x10000L ;
792 if (code_s2u & FM_SERRSF) {
793 SMT_PANIC(smc,SMT_E0114, SMT_E0114_MSG) ;
794 }
795mac2_end:
796 /* notice old status */
797 smc->hw.fp.s2l = code_s2l ;
798 smc->hw.fp.s2u = code_s2u ;
799 outpw(FM_A(FM_IMSK2U),~mac_imsk2u) ;
800}
801
802/*
803 * mac3_irq: receive queue 2 bits and address detection bits
804 */
805void mac3_irq(struct s_smc *smc, u_short code_s3u, u_short code_s3l)
806{
807 UNUSED(code_s3l) ;
808
809 if (code_s3u & (FM_SRCVOVR2 | /* recv. FIFO overflow */
810 FM_SRBFL2)) { /* recv. buffer full */
811 smc->hw.mac_ct.mac_r_restart_counter++ ;
812 smt_stat_counter(smc,1);
813 }
814
815
816 if (code_s3u & FM_SRPERRQ2) { /* parity error receive queue 2 */
817 SMT_PANIC(smc,SMT_E0115, SMT_E0115_MSG) ;
818 }
819 if (code_s3u & FM_SRPERRQ1) { /* parity error receive queue 2 */
820 SMT_PANIC(smc,SMT_E0116, SMT_E0116_MSG) ;
821 }
822}
823
824
825/*
826 * take formac offline
827 */
828static void formac_offline(struct s_smc *smc)
829{
830 outpw(FM_A(FM_CMDREG2),FM_IACTR) ;/* abort current transmit activity */
831
832 /* disable receive function */
833 SETMASK(FM_A(FM_MDREG1),FM_MDISRCV,FM_ADDET) ;
834
835 /* FORMAC+ 'Initialize Mode' */
836 SETMASK(FM_A(FM_MDREG1),FM_MINIT,FM_MMODE) ;
837
838 disable_formac(smc) ;
839 smc->hw.mac_ring_is_up = FALSE ;
840 smc->hw.hw_state = STOPPED ;
841}
842
843/*
844 * bring formac online
845 */
846static void formac_online(struct s_smc *smc)
847{
848 enable_formac(smc) ;
849 SETMASK(FM_A(FM_MDREG1),FM_MONLINE | FM_SELRA | MDR1INIT |
850 smc->hw.fp.rx_mode, FM_MMODE | FM_SELRA | FM_ADDRX) ;
851}
852
853/*
854 * FORMAC+ full init. (tx, rx, timer, counter, claim & beacon)
855 */
856int init_fplus(struct s_smc *smc)
857{
858 smc->hw.fp.nsa_mode = FM_MRNNSAFNMA ;
859 smc->hw.fp.rx_mode = FM_MDAMA ;
860 smc->hw.fp.group_addr = fddi_broadcast ;
861 smc->hw.fp.func_addr = 0 ;
862 smc->hw.fp.frselreg_init = 0 ;
863
864 init_driver_fplus(smc) ;
865 if (smc->s.sas == SMT_DAS)
866 smc->hw.fp.mdr3init |= FM_MENDAS ;
867
868 smc->hw.mac_ct.mac_nobuf_counter = 0 ;
869 smc->hw.mac_ct.mac_r_restart_counter = 0 ;
870
871 smc->hw.fp.fm_st1u = (HW_PTR) ADDR(B0_ST1U) ;
872 smc->hw.fp.fm_st1l = (HW_PTR) ADDR(B0_ST1L) ;
873 smc->hw.fp.fm_st2u = (HW_PTR) ADDR(B0_ST2U) ;
874 smc->hw.fp.fm_st2l = (HW_PTR) ADDR(B0_ST2L) ;
875 smc->hw.fp.fm_st3u = (HW_PTR) ADDR(B0_ST3U) ;
876 smc->hw.fp.fm_st3l = (HW_PTR) ADDR(B0_ST3L) ;
877
878 smc->hw.fp.s2l = smc->hw.fp.s2u = 0 ;
879 smc->hw.mac_ring_is_up = 0 ;
880
881 mac_counter_init(smc) ;
882
883 /* convert BCKL units to symbol time */
884 smc->hw.mac_pa.t_neg = (u_long)0 ;
885 smc->hw.mac_pa.t_pri = (u_long)0 ;
886
887 /* make sure all PCI settings are correct */
888 mac_do_pci_fix(smc) ;
889
890 return init_mac(smc, 1);
891 /* enable_formac(smc) ; */
892}
893
894static int init_mac(struct s_smc *smc, int all)
895{
896 u_short t_max,x ;
897 u_long time=0 ;
898
899 /*
900 * clear memory
901 */
902 outpw(FM_A(FM_MDREG1),FM_MINIT) ; /* FORMAC+ init mode */
903 set_formac_addr(smc) ;
904 outpw(FM_A(FM_MDREG1),FM_MMEMACT) ; /* FORMAC+ memory activ mode */
905 /* Note: Mode register 2 is set here, incase parity is enabled. */
906 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
907
908 if (all) {
909 init_ram(smc) ;
910 }
911 else {
912 /*
913 * reset the HPI, the Master and the BMUs
914 */
915 outp(ADDR(B0_CTRL), CTRL_HPI_SET) ;
916 time = hwt_quick_read(smc) ;
917 }
918
919 /*
920 * set all pointers, frames etc
921 */
922 smt_split_up_fifo(smc) ;
923
924 init_tx(smc) ;
925 init_rx(smc) ;
926 init_rbc(smc) ;
927
928 build_claim_beacon(smc,smc->mib.m[MAC0].fddiMACT_Req) ;
929
930 /* set RX threshold */
931 /* see Errata #SN2 Phantom receive overflow */
932 outpw(FM_A(FM_FRMTHR),14<<12) ; /* switch on */
933
934 /* set formac work mode */
935 outpw(FM_A(FM_MDREG1),MDR1INIT | FM_SELRA | smc->hw.fp.rx_mode) ;
936 outpw(FM_A(FM_MDREG2),smc->hw.fp.mdr2init) ;
937 outpw(FM_A(FM_MDREG3),smc->hw.fp.mdr3init) ;
938 outpw(FM_A(FM_FRSELREG),smc->hw.fp.frselreg_init) ;
939
940 /* set timer */
941 /*
942 * errata #22 fplus:
943 * T_MAX must not be FFFE
944 * or one of FFDF, FFB8, FF91 (-0x27 etc..)
945 */
946 t_max = (u_short)(smc->mib.m[MAC0].fddiMACT_Max/32) ;
947 x = t_max/0x27 ;
948 x *= 0x27 ;
949 if ((t_max == 0xfffe) || (t_max - x == 0x16))
950 t_max-- ;
951 outpw(FM_A(FM_TMAX),(u_short)t_max) ;
952
953 /* BugFix for report #10204 */
954 if (smc->mib.m[MAC0].fddiMACTvxValue < (u_long) (- US2BCLK(52))) {
955 outpw(FM_A(FM_TVX), (u_short) (- US2BCLK(52))/255 & MB) ;
956 } else {
957 outpw(FM_A(FM_TVX),
958 (u_short)((smc->mib.m[MAC0].fddiMACTvxValue/255) & MB)) ;
959 }
960
961 outpw(FM_A(FM_CMDREG1),FM_ICLLS) ; /* clear s-frame lock */
962 outpw(FM_A(FM_CMDREG1),FM_ICLLA0) ; /* clear a-frame lock */
963 outpw(FM_A(FM_CMDREG1),FM_ICLLR); /* clear receive lock */
964
965 /* Auto unlock receice threshold for receive queue 1 and 2 */
966 outpw(FM_A(FM_UNLCKDLY),(0xff|(0xff<<8))) ;
967
968 rtm_init(smc) ; /* RT-Monitor */
969
970 if (!all) {
971 /*
972 * after 10ms, reset the BMUs and repair the rings
973 */
974 hwt_wait_time(smc,time,MS2BCLK(10)) ;
975 outpd(ADDR(B0_R1_CSR),CSR_SET_RESET) ;
976 outpd(ADDR(B0_XA_CSR),CSR_SET_RESET) ;
977 outpd(ADDR(B0_XS_CSR),CSR_SET_RESET) ;
978 outp(ADDR(B0_CTRL), CTRL_HPI_CLR) ;
979 outpd(ADDR(B0_R1_CSR),CSR_CLR_RESET) ;
980 outpd(ADDR(B0_XA_CSR),CSR_CLR_RESET) ;
981 outpd(ADDR(B0_XS_CSR),CSR_CLR_RESET) ;
982 if (!smc->hw.hw_is_64bit) {
983 outpd(ADDR(B4_R1_F), RX_WATERMARK) ;
984 outpd(ADDR(B5_XA_F), TX_WATERMARK) ;
985 outpd(ADDR(B5_XS_F), TX_WATERMARK) ;
986 }
987 smc->hw.hw_state = STOPPED ;
988 mac_drv_repair_descr(smc) ;
989 }
990 smc->hw.hw_state = STARTED ;
991
992 return 0;
993}
994
995
996/*
997 * called by CFM
998 */
999void config_mux(struct s_smc *smc, int mux)
1000{
1001 plc_config_mux(smc,mux) ;
1002
1003 SETMASK(FM_A(FM_MDREG1),FM_SELRA,FM_SELRA) ;
1004}
1005
1006/*
1007 * called by RMT
1008 * enable CLAIM/BEACON interrupts
1009 * (only called if these events are of interest, e.g. in DETECT state
1010 * the interrupt must not be permanently enabled
1011 * RMT calls this function periodically (timer driven polling)
1012 */
1013void sm_mac_check_beacon_claim(struct s_smc *smc)
1014{
1015 /* set formac IMSK : 0 enables irq */
1016 outpw(FM_A(FM_IMSK2U),~(mac_imsk2u | mac_beacon_imsk2u)) ;
1017 /* the driver must receive the directed beacons */
1018 formac_rcv_restart(smc) ;
1019 process_receive(smc) ;
1020}
1021
1022/*-------------------------- interface functions ----------------------------*/
1023/*
1024 * control MAC layer (called by RMT)
1025 */
1026void sm_ma_control(struct s_smc *smc, int mode)
1027{
1028 switch(mode) {
1029 case MA_OFFLINE :
1030 /* Add to make the MAC offline in RM0_ISOLATED state */
1031 formac_offline(smc) ;
1032 break ;
1033 case MA_RESET :
1034 (void)init_mac(smc,0) ;
1035 break ;
1036 case MA_BEACON :
1037 formac_online(smc) ;
1038 break ;
1039 case MA_DIRECTED :
1040 directed_beacon(smc) ;
1041 break ;
1042 case MA_TREQ :
1043 /*
1044 * no actions necessary, TREQ is already set
1045 */
1046 break ;
1047 }
1048}
1049
1050int sm_mac_get_tx_state(struct s_smc *smc)
1051{
1052 return (inpw(FM_A(FM_STMCHN))>>4) & 7;
1053}
1054
1055/*
1056 * multicast functions
1057 */
1058
1059static struct s_fpmc* mac_get_mc_table(struct s_smc *smc,
1060 struct fddi_addr *user,
1061 struct fddi_addr *own,
1062 int del, int can)
1063{
1064 struct s_fpmc *tb ;
1065 struct s_fpmc *slot ;
1066 u_char *p ;
1067 int i ;
1068
1069 /*
1070 * set own = can(user)
1071 */
1072 *own = *user ;
1073 if (can) {
1074 p = own->a ;
1075 for (i = 0 ; i < 6 ; i++, p++)
1076 *p = bitrev8(*p);
1077 }
1078 slot = NULL;
1079 for (i = 0, tb = smc->hw.fp.mc.table ; i < FPMAX_MULTICAST ; i++, tb++){
1080 if (!tb->n) { /* not used */
1081 if (!del && !slot) /* if !del save first free */
1082 slot = tb ;
1083 continue ;
1084 }
1085 if (memcmp((char *)&tb->a,(char *)own,6))
1086 continue ;
1087 return tb;
1088 }
1089 return slot; /* return first free or NULL */
1090}
1091
1092/*
1093 BEGIN_MANUAL_ENTRY(if,func;others;2)
1094
1095 void mac_clear_multicast(smc)
1096 struct s_smc *smc ;
1097
1098Function DOWNCALL (SMT, fplustm.c)
1099 Clear all multicast entries
1100
1101 END_MANUAL_ENTRY()
1102 */
1103void mac_clear_multicast(struct s_smc *smc)
1104{
1105 struct s_fpmc *tb ;
1106 int i ;
1107
1108 smc->hw.fp.os_slots_used = 0 ; /* note the SMT addresses */
1109 /* will not be deleted */
1110 for (i = 0, tb = smc->hw.fp.mc.table ; i < FPMAX_MULTICAST ; i++, tb++){
1111 if (!tb->perm) {
1112 tb->n = 0 ;
1113 }
1114 }
1115}
1116
1117/*
1118 BEGIN_MANUAL_ENTRY(if,func;others;2)
1119
1120 int mac_add_multicast(smc,addr,can)
1121 struct s_smc *smc ;
1122 struct fddi_addr *addr ;
1123 int can ;
1124
1125Function DOWNCALL (SMC, fplustm.c)
1126 Add an entry to the multicast table
1127
1128Para addr pointer to a multicast address
1129 can = 0: the multicast address has the physical format
1130 = 1: the multicast address has the canonical format
1131 | 0x80 permanent
1132
1133Returns 0: success
1134 1: address table full
1135
1136Note After a 'driver reset' or a 'station set address' all
1137 entries of the multicast table are cleared.
1138 In this case the driver has to fill the multicast table again.
1139 After the operating system dependent module filled
1140 the multicast table it must call mac_update_multicast
1141 to activate the new multicast addresses!
1142
1143 END_MANUAL_ENTRY()
1144 */
1145int mac_add_multicast(struct s_smc *smc, struct fddi_addr *addr, int can)
1146{
1147 SK_LOC_DECL(struct fddi_addr,own) ;
1148 struct s_fpmc *tb ;
1149
1150 /*
1151 * check if there are free table entries
1152 */
1153 if (can & 0x80) {
1154 if (smc->hw.fp.smt_slots_used >= SMT_MAX_MULTI) {
1155 return 1;
1156 }
1157 }
1158 else {
1159 if (smc->hw.fp.os_slots_used >= FPMAX_MULTICAST-SMT_MAX_MULTI) {
1160 return 1;
1161 }
1162 }
1163
1164 /*
1165 * find empty slot
1166 */
1167 if (!(tb = mac_get_mc_table(smc,addr,&own,0,can & ~0x80)))
1168 return 1;
1169 tb->n++ ;
1170 tb->a = own ;
1171 tb->perm = (can & 0x80) ? 1 : 0 ;
1172
1173 if (can & 0x80)
1174 smc->hw.fp.smt_slots_used++ ;
1175 else
1176 smc->hw.fp.os_slots_used++ ;
1177
1178 return 0;
1179}
1180
1181/*
1182 * mode
1183 */
1184
1185#define RX_MODE_PROM 0x1
1186#define RX_MODE_ALL_MULTI 0x2
1187
1188/*
1189 BEGIN_MANUAL_ENTRY(if,func;others;2)
1190
1191 void mac_update_multicast(smc)
1192 struct s_smc *smc ;
1193
1194Function DOWNCALL (SMT, fplustm.c)
1195 Update FORMAC multicast registers
1196
1197 END_MANUAL_ENTRY()
1198 */
1199void mac_update_multicast(struct s_smc *smc)
1200{
1201 struct s_fpmc *tb ;
1202 u_char *fu ;
1203 int i ;
1204
1205 /*
1206 * invalidate the CAM
1207 */
1208 outpw(FM_A(FM_AFCMD),FM_IINV_CAM) ;
1209
1210 /*
1211 * set the functional address
1212 */
1213 if (smc->hw.fp.func_addr) {
1214 fu = (u_char *) &smc->hw.fp.func_addr ;
1215 outpw(FM_A(FM_AFMASK2),0xffff) ;
1216 outpw(FM_A(FM_AFMASK1),(u_short) ~((fu[0] << 8) + fu[1])) ;
1217 outpw(FM_A(FM_AFMASK0),(u_short) ~((fu[2] << 8) + fu[3])) ;
1218 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
1219 outpw(FM_A(FM_AFCOMP2), 0xc000) ;
1220 outpw(FM_A(FM_AFCOMP1), 0x0000) ;
1221 outpw(FM_A(FM_AFCOMP0), 0x0000) ;
1222 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
1223 }
1224
1225 /*
1226 * set the mask and the personality register(s)
1227 */
1228 outpw(FM_A(FM_AFMASK0),0xffff) ;
1229 outpw(FM_A(FM_AFMASK1),0xffff) ;
1230 outpw(FM_A(FM_AFMASK2),0xffff) ;
1231 outpw(FM_A(FM_AFPERS),FM_VALID|FM_DA) ;
1232
1233 for (i = 0, tb = smc->hw.fp.mc.table; i < FPMAX_MULTICAST; i++, tb++) {
1234 if (tb->n) {
1235 CHECK_CAM() ;
1236
1237 /*
1238 * write the multicast address into the CAM
1239 */
1240 outpw(FM_A(FM_AFCOMP2),
1241 (u_short)((tb->a.a[0]<<8)+tb->a.a[1])) ;
1242 outpw(FM_A(FM_AFCOMP1),
1243 (u_short)((tb->a.a[2]<<8)+tb->a.a[3])) ;
1244 outpw(FM_A(FM_AFCOMP0),
1245 (u_short)((tb->a.a[4]<<8)+tb->a.a[5])) ;
1246 outpw(FM_A(FM_AFCMD),FM_IWRITE_CAM) ;
1247 }
1248 }
1249}
1250
1251/*
1252 BEGIN_MANUAL_ENTRY(if,func;others;3)
1253
1254 void mac_set_rx_mode(smc,mode)
1255 struct s_smc *smc ;
1256 int mode ;
1257
1258Function DOWNCALL/INTERN (SMT, fplustm.c)
1259 This function enables / disables the selected receive.
1260 Don't call this function if the hardware module is
1261 used -- use mac_drv_rx_mode() instead of.
1262
1263Para mode = 1 RX_ENABLE_ALLMULTI enable all multicasts
1264 2 RX_DISABLE_ALLMULTI disable "enable all multicasts"
1265 3 RX_ENABLE_PROMISC enable promiscuous
1266 4 RX_DISABLE_PROMISC disable promiscuous
1267 5 RX_ENABLE_NSA enable reception of NSA frames
1268 6 RX_DISABLE_NSA disable reception of NSA frames
1269
1270Note The selected receive modes will be lost after 'driver reset'
1271 or 'set station address'
1272
1273 END_MANUAL_ENTRY
1274 */
1275void mac_set_rx_mode(struct s_smc *smc, int mode)
1276{
1277 switch (mode) {
1278 case RX_ENABLE_ALLMULTI :
1279 smc->hw.fp.rx_prom |= RX_MODE_ALL_MULTI ;
1280 break ;
1281 case RX_DISABLE_ALLMULTI :
1282 smc->hw.fp.rx_prom &= ~RX_MODE_ALL_MULTI ;
1283 break ;
1284 case RX_ENABLE_PROMISC :
1285 smc->hw.fp.rx_prom |= RX_MODE_PROM ;
1286 break ;
1287 case RX_DISABLE_PROMISC :
1288 smc->hw.fp.rx_prom &= ~RX_MODE_PROM ;
1289 break ;
1290 case RX_ENABLE_NSA :
1291 smc->hw.fp.nsa_mode = FM_MDAMA ;
1292 smc->hw.fp.rx_mode = (smc->hw.fp.rx_mode & ~FM_ADDET) |
1293 smc->hw.fp.nsa_mode ;
1294 break ;
1295 case RX_DISABLE_NSA :
1296 smc->hw.fp.nsa_mode = FM_MRNNSAFNMA ;
1297 smc->hw.fp.rx_mode = (smc->hw.fp.rx_mode & ~FM_ADDET) |
1298 smc->hw.fp.nsa_mode ;
1299 break ;
1300 }
1301 if (smc->hw.fp.rx_prom & RX_MODE_PROM) {
1302 smc->hw.fp.rx_mode = FM_MLIMPROM ;
1303 }
1304 else if (smc->hw.fp.rx_prom & RX_MODE_ALL_MULTI) {
1305 smc->hw.fp.rx_mode = smc->hw.fp.nsa_mode | FM_EXGPA0 ;
1306 }
1307 else
1308 smc->hw.fp.rx_mode = smc->hw.fp.nsa_mode ;
1309 SETMASK(FM_A(FM_MDREG1),smc->hw.fp.rx_mode,FM_ADDRX) ;
1310 mac_update_multicast(smc) ;
1311}
1312
1313/*
1314 BEGIN_MANUAL_ENTRY(module;tests;3)
1315 How to test the Restricted Token Monitor
1316 ----------------------------------------------------------------
1317
1318 o Insert a break point in the function rtm_irq()
1319 o Remove all stations with a restricted token monitor from the
1320 network.
1321 o Connect a UPPS ISA or EISA station to the network.
1322 o Give the FORMAC of UPPS station the command to send
1323 restricted tokens until the ring becomes instable.
1324 o Now connect your test test client.
1325 o The restricted token monitor should detect the restricted token,
1326 and your break point will be reached.
1327 o You can ovserve how the station will clean the ring.
1328
1329 END_MANUAL_ENTRY
1330 */
1331void rtm_irq(struct s_smc *smc)
1332{
1333 outpw(ADDR(B2_RTM_CRTL),TIM_CL_IRQ) ; /* clear IRQ */
1334 if (inpw(ADDR(B2_RTM_CRTL)) & TIM_RES_TOK) {
1335 outpw(FM_A(FM_CMDREG1),FM_ICL) ; /* force claim */
1336 DB_RMT("RMT: fddiPATHT_Rmode expired\n",0,0) ;
1337 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS,
1338 (u_long) FDDI_SMT_EVENT,
1339 (u_long) FDDI_RTT, smt_get_event_word(smc));
1340 }
1341 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable RTM monitoring */
1342}
1343
1344static void rtm_init(struct s_smc *smc)
1345{
1346 outpd(ADDR(B2_RTM_INI),0) ; /* timer = 0 */
1347 outpw(ADDR(B2_RTM_CRTL),TIM_START) ; /* enable IRQ */
1348}
1349
1350void rtm_set_timer(struct s_smc *smc)
1351{
1352 /*
1353 * MIB timer and hardware timer have the same resolution of 80nS
1354 */
1355 DB_RMT("RMT: setting new fddiPATHT_Rmode, t = %d ns\n",
1356 (int) smc->mib.a[PATH0].fddiPATHT_Rmode,0) ;
1357 outpd(ADDR(B2_RTM_INI),smc->mib.a[PATH0].fddiPATHT_Rmode) ;
1358}
1359
1360static void smt_split_up_fifo(struct s_smc *smc)
1361{
1362
1363/*
1364 BEGIN_MANUAL_ENTRY(module;mem;1)
1365 -------------------------------------------------------------
1366 RECEIVE BUFFER MEMORY DIVERSION
1367 -------------------------------------------------------------
1368
1369 R1_RxD == SMT_R1_RXD_COUNT
1370 R2_RxD == SMT_R2_RXD_COUNT
1371
1372 SMT_R1_RXD_COUNT must be unequal zero
1373
1374 | R1_RxD R2_RxD |R1_RxD R2_RxD | R1_RxD R2_RxD
1375 | x 0 | x 1-3 | x < 3
1376 ----------------------------------------------------------------------
1377 | 63,75 kB | 54,75 | R1_RxD
1378 rx queue 1 | RX_FIFO_SPACE | RX_LARGE_FIFO| ------------- * 63,75 kB
1379 | | | R1_RxD+R2_RxD
1380 ----------------------------------------------------------------------
1381 | | 9 kB | R2_RxD
1382 rx queue 2 | 0 kB | RX_SMALL_FIFO| ------------- * 63,75 kB
1383 | (not used) | | R1_RxD+R2_RxD
1384
1385 END_MANUAL_ENTRY
1386*/
1387
1388 if (SMT_R1_RXD_COUNT == 0) {
1389 SMT_PANIC(smc,SMT_E0117, SMT_E0117_MSG) ;
1390 }
1391
1392 switch(SMT_R2_RXD_COUNT) {
1393 case 0:
1394 smc->hw.fp.fifo.rx1_fifo_size = RX_FIFO_SPACE ;
1395 smc->hw.fp.fifo.rx2_fifo_size = 0 ;
1396 break ;
1397 case 1:
1398 case 2:
1399 case 3:
1400 smc->hw.fp.fifo.rx1_fifo_size = RX_LARGE_FIFO ;
1401 smc->hw.fp.fifo.rx2_fifo_size = RX_SMALL_FIFO ;
1402 break ;
1403 default: /* this is not the real defaule */
1404 smc->hw.fp.fifo.rx1_fifo_size = RX_FIFO_SPACE *
1405 SMT_R1_RXD_COUNT/(SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT) ;
1406 smc->hw.fp.fifo.rx2_fifo_size = RX_FIFO_SPACE *
1407 SMT_R2_RXD_COUNT/(SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT) ;
1408 break ;
1409 }
1410
1411/*
1412 BEGIN_MANUAL_ENTRY(module;mem;1)
1413 -------------------------------------------------------------
1414 TRANSMIT BUFFER MEMORY DIVERSION
1415 -------------------------------------------------------------
1416
1417
1418 | no sync bw | sync bw available and | sync bw available and
1419 | available | SynchTxMode = SPLIT | SynchTxMode = ALL
1420 -----------------------------------------------------------------------
1421 sync tx | 0 kB | 32 kB | 55 kB
1422 queue | | TX_MEDIUM_FIFO | TX_LARGE_FIFO
1423 -----------------------------------------------------------------------
1424 async tx | 64 kB | 32 kB | 9 k
1425 queue | TX_FIFO_SPACE| TX_MEDIUM_FIFO | TX_SMALL_FIFO
1426
1427 END_MANUAL_ENTRY
1428*/
1429
1430 /*
1431 * set the tx mode bits
1432 */
1433 if (smc->mib.a[PATH0].fddiPATHSbaPayload) {
1434#ifdef ESS
1435 smc->hw.fp.fifo.fifo_config_mode |=
1436 smc->mib.fddiESSSynchTxMode | SYNC_TRAFFIC_ON ;
1437#endif
1438 }
1439 else {
1440 smc->hw.fp.fifo.fifo_config_mode &=
1441 ~(SEND_ASYNC_AS_SYNC|SYNC_TRAFFIC_ON) ;
1442 }
1443
1444 /*
1445 * split up the FIFO
1446 */
1447 if (smc->hw.fp.fifo.fifo_config_mode & SYNC_TRAFFIC_ON) {
1448 if (smc->hw.fp.fifo.fifo_config_mode & SEND_ASYNC_AS_SYNC) {
1449 smc->hw.fp.fifo.tx_s_size = TX_LARGE_FIFO ;
1450 smc->hw.fp.fifo.tx_a0_size = TX_SMALL_FIFO ;
1451 }
1452 else {
1453 smc->hw.fp.fifo.tx_s_size = TX_MEDIUM_FIFO ;
1454 smc->hw.fp.fifo.tx_a0_size = TX_MEDIUM_FIFO ;
1455 }
1456 }
1457 else {
1458 smc->hw.fp.fifo.tx_s_size = 0 ;
1459 smc->hw.fp.fifo.tx_a0_size = TX_FIFO_SPACE ;
1460 }
1461
1462 smc->hw.fp.fifo.rx1_fifo_start = smc->hw.fp.fifo.rbc_ram_start +
1463 RX_FIFO_OFF ;
1464 smc->hw.fp.fifo.tx_s_start = smc->hw.fp.fifo.rx1_fifo_start +
1465 smc->hw.fp.fifo.rx1_fifo_size ;
1466 smc->hw.fp.fifo.tx_a0_start = smc->hw.fp.fifo.tx_s_start +
1467 smc->hw.fp.fifo.tx_s_size ;
1468 smc->hw.fp.fifo.rx2_fifo_start = smc->hw.fp.fifo.tx_a0_start +
1469 smc->hw.fp.fifo.tx_a0_size ;
1470
1471 DB_SMT("FIFO split: mode = %x\n",smc->hw.fp.fifo.fifo_config_mode,0) ;
1472 DB_SMT("rbc_ram_start = %x rbc_ram_end = %x\n",
1473 smc->hw.fp.fifo.rbc_ram_start, smc->hw.fp.fifo.rbc_ram_end) ;
1474 DB_SMT("rx1_fifo_start = %x tx_s_start = %x\n",
1475 smc->hw.fp.fifo.rx1_fifo_start, smc->hw.fp.fifo.tx_s_start) ;
1476 DB_SMT("tx_a0_start = %x rx2_fifo_start = %x\n",
1477 smc->hw.fp.fifo.tx_a0_start, smc->hw.fp.fifo.rx2_fifo_start) ;
1478}
1479
1480void formac_reinit_tx(struct s_smc *smc)
1481{
1482 /*
1483 * Split up the FIFO and reinitialize the MAC if synchronous
1484 * bandwidth becomes available but no synchronous queue is
1485 * configured.
1486 */
1487 if (!smc->hw.fp.fifo.tx_s_size && smc->mib.a[PATH0].fddiPATHSbaPayload){
1488 (void)init_mac(smc,0) ;
1489 }
1490}
1491
diff --git a/drivers/net/skfp/h/cmtdef.h b/drivers/net/skfp/h/cmtdef.h
deleted file mode 100644
index 5a6c6122ccb0..000000000000
--- a/drivers/net/skfp/h/cmtdef.h
+++ /dev/null
@@ -1,756 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _CMTDEF_
16#define _CMTDEF_
17
18/* **************************************************************** */
19
20/*
21 * implementation specific constants
22 * MODIIFY THE FOLLOWING THREE DEFINES
23 */
24#define AMDPLC /* if Amd PLC chip used */
25#ifdef CONC
26#define NUMPHYS 12 /* 2 for SAS or DAS, more for Concentrator */
27#else
28#ifdef CONC_II
29#define NUMPHYS 24 /* 2 for SAS or DAS, more for Concentrator */
30#else
31#define NUMPHYS 2 /* 2 for SAS or DAS, more for Concentrator */
32#endif
33#endif
34#define NUMMACS 1 /* only 1 supported at the moment */
35#define NUMPATHS 2 /* primary and secondary path supported */
36
37/*
38 * DO NOT MODIFY BEYOND THIS POINT
39 */
40
41/* **************************************************************** */
42
43#if NUMPHYS > 2
44#define CONCENTRATOR
45#endif
46
47/*
48 * Definitions for comfortable LINT usage
49 */
50#ifdef lint
51#define LINT_USE(x) (x)=(x)
52#else
53#define LINT_USE(x)
54#endif
55
56#ifdef DEBUG
57#define DB_PR(flag,a,b,c) { if (flag) printf(a,b,c) ; }
58#else
59#define DB_PR(flag,a,b,c)
60#endif
61
62#ifdef DEBUG_BRD
63#define DB_ECM(a,b,c) DB_PR((smc->debug.d_smt&1),a,b,c)
64#define DB_ECMN(n,a,b,c) DB_PR((smc->debug.d_ecm >=(n)),a,b,c)
65#define DB_RMT(a,b,c) DB_PR((smc->debug.d_smt&2),a,b,c)
66#define DB_RMTN(n,a,b,c) DB_PR((smc->debug.d_rmt >=(n)),a,b,c)
67#define DB_CFM(a,b,c) DB_PR((smc->debug.d_smt&4),a,b,c)
68#define DB_CFMN(n,a,b,c) DB_PR((smc->debug.d_cfm >=(n)),a,b,c)
69#define DB_PCM(a,b,c) DB_PR((smc->debug.d_smt&8),a,b,c)
70#define DB_PCMN(n,a,b,c) DB_PR((smc->debug.d_pcm >=(n)),a,b,c)
71#define DB_SMT(a,b,c) DB_PR((smc->debug.d_smtf),a,b,c)
72#define DB_SMTN(n,a,b,c) DB_PR((smc->debug.d_smtf >=(n)),a,b,c)
73#define DB_SBA(a,b,c) DB_PR((smc->debug.d_sba),a,b,c)
74#define DB_SBAN(n,a,b,c) DB_PR((smc->debug.d_sba >=(n)),a,b,c)
75#define DB_ESS(a,b,c) DB_PR((smc->debug.d_ess),a,b,c)
76#define DB_ESSN(n,a,b,c) DB_PR((smc->debug.d_ess >=(n)),a,b,c)
77#else
78#define DB_ECM(a,b,c) DB_PR((debug.d_smt&1),a,b,c)
79#define DB_ECMN(n,a,b,c) DB_PR((debug.d_ecm >=(n)),a,b,c)
80#define DB_RMT(a,b,c) DB_PR((debug.d_smt&2),a,b,c)
81#define DB_RMTN(n,a,b,c) DB_PR((debug.d_rmt >=(n)),a,b,c)
82#define DB_CFM(a,b,c) DB_PR((debug.d_smt&4),a,b,c)
83#define DB_CFMN(n,a,b,c) DB_PR((debug.d_cfm >=(n)),a,b,c)
84#define DB_PCM(a,b,c) DB_PR((debug.d_smt&8),a,b,c)
85#define DB_PCMN(n,a,b,c) DB_PR((debug.d_pcm >=(n)),a,b,c)
86#define DB_SMT(a,b,c) DB_PR((debug.d_smtf),a,b,c)
87#define DB_SMTN(n,a,b,c) DB_PR((debug.d_smtf >=(n)),a,b,c)
88#define DB_SBA(a,b,c) DB_PR((debug.d_sba),a,b,c)
89#define DB_SBAN(n,a,b,c) DB_PR((debug.d_sba >=(n)),a,b,c)
90#define DB_ESS(a,b,c) DB_PR((debug.d_ess),a,b,c)
91#define DB_ESSN(n,a,b,c) DB_PR((debug.d_ess >=(n)),a,b,c)
92#endif
93
94#ifndef SS_NOT_DS
95#define SK_LOC_DECL(type,var) type var
96#else
97#define SK_LOC_DECL(type,var) static type var
98#endif
99/*
100 * PHYs and PORTS
101 * Note: Don't touch the definition of PA and PB. Those might be used
102 * by some "for" loops.
103 */
104#define PA 0
105#define PB 1
106#if defined(SUPERNET_3) || defined(CONC_II)
107/*
108 * The port indices have to be different,
109 * because the MAC output goes through the 2. PLC
110 * Conc II: It has to be the first port in the row.
111 */
112#define PS 0 /* Internal PLC which is the same as PA */
113#else
114#define PS 1
115#endif
116#define PM 2 /* PM .. PA+NUM_PHYS-1 */
117
118/*
119 * PHY types - as in path descriptor 'fddiPHYType'
120 */
121#define TA 0 /* A port */
122#define TB 1 /* B port */
123#define TS 2 /* S port */
124#define TM 3 /* M port */
125#define TNONE 4
126
127
128/*
129 * indexes in MIB
130 */
131#define INDEX_MAC 1
132#define INDEX_PATH 1
133#define INDEX_PORT 1
134
135
136/*
137 * policies
138 */
139#define POLICY_AA (1<<0) /* reject AA */
140#define POLICY_AB (1<<1) /* reject AB */
141#define POLICY_AS (1<<2) /* reject AS */
142#define POLICY_AM (1<<3) /* reject AM */
143#define POLICY_BA (1<<4) /* reject BA */
144#define POLICY_BB (1<<5) /* reject BB */
145#define POLICY_BS (1<<6) /* reject BS */
146#define POLICY_BM (1<<7) /* reject BM */
147#define POLICY_SA (1<<8) /* reject SA */
148#define POLICY_SB (1<<9) /* reject SB */
149#define POLICY_SS (1<<10) /* reject SS */
150#define POLICY_SM (1<<11) /* reject SM */
151#define POLICY_MA (1<<12) /* reject MA */
152#define POLICY_MB (1<<13) /* reject MB */
153#define POLICY_MS (1<<14) /* reject MS */
154#define POLICY_MM (1<<15) /* reject MM */
155
156/*
157 * commands
158 */
159
160/*
161 * EVENTS
162 * event classes
163 */
164#define EVENT_ECM 1 /* event class ECM */
165#define EVENT_CFM 2 /* event class CFM */
166#define EVENT_RMT 3 /* event class RMT */
167#define EVENT_SMT 4 /* event class SMT */
168#define EVENT_PCM 5 /* event class PCM */
169#define EVENT_PCMA 5 /* event class PCMA */
170#define EVENT_PCMB 6 /* event class PCMB */
171
172/* WARNING :
173 * EVENT_PCM* must be last in the above list
174 * if more than two ports are used, EVENT_PCM .. EVENT_PCMA+NUM_PHYS-1
175 * are used !
176 */
177
178#define EV_TOKEN(class,event) (((u_long)(class)<<16L)|((u_long)(event)))
179#define EV_T_CLASS(token) ((int)((token)>>16)&0xffff)
180#define EV_T_EVENT(token) ((int)(token)&0xffff)
181
182/*
183 * ECM events
184 */
185#define EC_CONNECT 1 /* connect request */
186#define EC_DISCONNECT 2 /* disconnect request */
187#define EC_TRACE_PROP 3 /* trace propagation */
188#define EC_PATH_TEST 4 /* path test */
189#define EC_TIMEOUT_TD 5 /* timer TD_min */
190#define EC_TIMEOUT_TMAX 6 /* timer trace_max */
191#define EC_TIMEOUT_IMAX 7 /* timer I_max */
192#define EC_TIMEOUT_INMAX 8 /* timer IN_max */
193#define EC_TEST_DONE 9 /* path test done */
194
195/*
196 * CFM events
197 */
198#define CF_LOOP 1 /* cf_loop flag from PCM */
199#define CF_LOOP_A 1 /* cf_loop flag from PCM */
200#define CF_LOOP_B 2 /* cf_loop flag from PCM */
201#define CF_JOIN 3 /* cf_join flag from PCM */
202#define CF_JOIN_A 3 /* cf_join flag from PCM */
203#define CF_JOIN_B 4 /* cf_join flag from PCM */
204
205/*
206 * PCM events
207 */
208#define PC_START 1
209#define PC_STOP 2
210#define PC_LOOP 3
211#define PC_JOIN 4
212#define PC_SIGNAL 5
213#define PC_REJECT 6
214#define PC_MAINT 7
215#define PC_TRACE 8
216#define PC_PDR 9
217#define PC_ENABLE 10
218#define PC_DISABLE 11
219
220/*
221 * must be ordered as in LineStateType
222 */
223#define PC_QLS 12
224#define PC_ILS 13
225#define PC_MLS 14
226#define PC_HLS 15
227#define PC_LS_PDR 16
228#define PC_LS_NONE 17
229#define LS2MIB(x) ((x)-PC_QLS)
230#define MIB2LS(x) ((x)+PC_QLS)
231
232#define PC_TIMEOUT_TB_MAX 18 /* timer TB_max */
233#define PC_TIMEOUT_TB_MIN 19 /* timer TB_min */
234#define PC_TIMEOUT_C_MIN 20 /* timer C_Min */
235#define PC_TIMEOUT_T_OUT 21 /* timer T_Out */
236#define PC_TIMEOUT_TL_MIN 22 /* timer TL_Min */
237#define PC_TIMEOUT_T_NEXT 23 /* timer t_next[] */
238#define PC_TIMEOUT_LCT 24
239#define PC_NSE 25 /* NOISE hardware timer */
240#define PC_LEM 26 /* LEM done */
241
242/*
243 * RMT events meaning from
244 */
245#define RM_RING_OP 1 /* ring operational MAC */
246#define RM_RING_NON_OP 2 /* ring not operational MAC */
247#define RM_MY_BEACON 3 /* recvd my beacon MAC */
248#define RM_OTHER_BEACON 4 /* recvd other beacon MAC */
249#define RM_MY_CLAIM 5 /* recvd my claim MAC */
250#define RM_TRT_EXP 6 /* TRT exp MAC */
251#define RM_VALID_CLAIM 7 /* claim from dup addr MAC */
252#define RM_JOIN 8 /* signal rm_join CFM */
253#define RM_LOOP 9 /* signal rm_loop CFM */
254#define RM_DUP_ADDR 10 /* dup_addr_test hange SMT-NIF */
255#define RM_ENABLE_FLAG 11 /* enable flag */
256
257#define RM_TIMEOUT_NON_OP 12 /* timeout T_Non_OP */
258#define RM_TIMEOUT_T_STUCK 13 /* timeout T_Stuck */
259#define RM_TIMEOUT_ANNOUNCE 14 /* timeout T_Announce */
260#define RM_TIMEOUT_T_DIRECT 15 /* timeout T_Direct */
261#define RM_TIMEOUT_D_MAX 16 /* timeout D_Max */
262#define RM_TIMEOUT_POLL 17 /* claim/beacon poller */
263#define RM_TX_STATE_CHANGE 18 /* To restart timer for D_Max */
264
265/*
266 * SMT events
267 */
268#define SM_TIMER 1 /* timer */
269#define SM_FAST 2 /* smt_force_irq */
270
271/* PC modes */
272#define PM_NONE 0
273#define PM_PEER 1
274#define PM_TREE 2
275
276/*
277 * PCM withhold codes
278 * MIB PC-WithholdType ENUM
279 */
280#define PC_WH_NONE 0 /* ok */
281#define PC_WH_M_M 1 /* M to M */
282#define PC_WH_OTHER 2 /* other incompatible phys */
283#define PC_WH_PATH 3 /* path not available */
284/*
285 * LCT duration
286 */
287#define LC_SHORT 1 /* short LCT */
288#define LC_MEDIUM 2 /* medium LCT */
289#define LC_LONG 3 /* long LCT */
290#define LC_EXTENDED 4 /* extended LCT */
291
292/*
293 * path_test values
294 */
295#define PT_NONE 0
296#define PT_TESTING 1 /* test is running */
297#define PT_PASSED 2 /* test passed */
298#define PT_FAILED 3 /* test failed */
299#define PT_PENDING 4 /* path test follows */
300#define PT_EXITING 5 /* disconnected while in trace/leave */
301
302/*
303 * duplicate address test
304 * MIB DupAddressTest ENUM
305 */
306#define DA_NONE 0 /* */
307#define DA_PASSED 1 /* test passed */
308#define DA_FAILED 2 /* test failed */
309
310
311/*
312 * optical bypass
313 */
314#define BP_DEINSERT 0 /* disable bypass */
315#define BP_INSERT 1 /* enable bypass */
316
317/*
318 * ODL enable/disable
319 */
320#define PM_TRANSMIT_DISABLE 0 /* disable xmit */
321#define PM_TRANSMIT_ENABLE 1 /* enable xmit */
322
323/*
324 * parameter for config_mux
325 * note : number is index in config_endec table !
326 */
327#define MUX_THRUA 0 /* through A */
328#define MUX_THRUB 1 /* through B */
329#define MUX_WRAPA 2 /* wrap A */
330#define MUX_WRAPB 3 /* wrap B */
331#define MUX_ISOLATE 4 /* isolated */
332#define MUX_WRAPS 5 /* SAS */
333
334/*
335 * MAC control
336 */
337#define MA_RESET 0
338#define MA_BEACON 1
339#define MA_CLAIM 2
340#define MA_DIRECTED 3 /* directed beacon */
341#define MA_TREQ 4 /* change T_Req */
342#define MA_OFFLINE 5 /* switch MAC to offline */
343
344
345/*
346 * trace prop
347 * bit map for trace propagation
348 */
349#define ENTITY_MAC (NUMPHYS)
350#define ENTITY_PHY(p) (p)
351#define ENTITY_BIT(m) (1<<(m))
352
353/*
354 * Resource Tag Types
355 */
356#define PATH_ISO 0 /* isolated */
357#define PATH_PRIM 3 /* primary path */
358#define PATH_THRU 5 /* through path */
359
360#define RES_MAC 2 /* resource type MAC */
361#define RES_PORT 4 /* resource type PORT */
362
363
364/*
365 * CFM state
366 * oops: MUST MATCH CF-StateType in SMT7.2 !
367 */
368#define SC0_ISOLATED 0 /* isolated */
369#define SC1_WRAP_A 5 /* wrap A (not used) */
370#define SC2_WRAP_B 6 /* wrap B (not used) */
371#define SC4_THRU_A 12 /* through A */
372#define SC5_THRU_B 7 /* through B (used in SMT 6.2) */
373#define SC7_WRAP_S 8 /* SAS (not used) */
374#define SC9_C_WRAP_A 9 /* c wrap A */
375#define SC10_C_WRAP_B 10 /* c wrap B */
376#define SC11_C_WRAP_S 11 /* c wrap S */
377
378/*
379 * convert MIB time in units of 80nS to uS
380 */
381#define MIB2US(t) ((t)/12)
382#define SEC2MIB(s) ((s)*12500000L)
383/*
384 * SMT timer
385 */
386struct smt_timer {
387 struct smt_timer *tm_next ; /* linked list */
388 struct s_smc *tm_smc ; /* pointer to context */
389 u_long tm_delta ; /* delta time */
390 u_long tm_token ; /* token value */
391 u_short tm_active ; /* flag : active/inactive */
392 u_short tm_pad ; /* pad field */
393} ;
394
395/*
396 * communication structures
397 */
398struct mac_parameter {
399 u_long t_neg ; /* T_Neg parameter */
400 u_long t_pri ; /* T_Pri register in MAC */
401} ;
402
403/*
404 * MAC counters
405 */
406struct mac_counter {
407 u_long mac_nobuf_counter ; /* MAC SW counter: no buffer */
408 u_long mac_r_restart_counter ; /* MAC SW counter: rx restarted */
409} ;
410
411/*
412 * para struct context for SMT parameters
413 */
414struct s_pcon {
415 int pc_len ;
416 int pc_err ;
417 int pc_badset ;
418 void *pc_p ;
419} ;
420
421/*
422 * link error monitor
423 */
424#define LEM_AVG 5
425struct lem_counter {
426#ifdef AM29K
427 int lem_on ;
428 u_long lem_errors ;
429 u_long lem_symbols ;
430 u_long lem_tsymbols ;
431 int lem_s_count ;
432 int lem_n_s ;
433 int lem_values ;
434 int lem_index ;
435 int lem_avg_ber[LEM_AVG] ;
436 int lem_sum ;
437#else
438 u_short lem_float_ber ; /* 10E-nn bit error rate */
439 u_long lem_errors ; /* accumulated error count */
440 u_short lem_on ;
441#endif
442} ;
443
444#define NUMBITS 10
445
446#ifdef AMDPLC
447
448/*
449 * PLC state table
450 */
451struct s_plc {
452 u_short p_state ; /* current state */
453 u_short p_bits ; /* number of bits to send */
454 u_short p_start ; /* first bit pos */
455 u_short p_pad ; /* padding for alignment */
456 u_long soft_err ; /* error counter */
457 u_long parity_err ; /* error counter */
458 u_long ebuf_err ; /* error counter */
459 u_long ebuf_cont ; /* continuous error counter */
460 u_long phyinv ; /* error counter */
461 u_long vsym_ctr ; /* error counter */
462 u_long mini_ctr ; /* error counter */
463 u_long tpc_exp ; /* error counter */
464 u_long np_err ; /* error counter */
465 u_long b_pcs ; /* error counter */
466 u_long b_tpc ; /* error counter */
467 u_long b_tne ; /* error counter */
468 u_long b_qls ; /* error counter */
469 u_long b_ils ; /* error counter */
470 u_long b_hls ; /* error counter */
471} ;
472#endif
473
474#ifdef PROTOTYP_INC
475#include "fddi/driver.pro"
476#else /* PROTOTYP_INC */
477/*
478 * function prototypes
479 */
480#include "h/mbuf.h" /* Type definitions for MBUFs */
481#include "h/smtstate.h" /* struct smt_state */
482
483void hwt_restart(struct s_smc *smc); /* hwt.c */
484SMbuf *smt_build_frame(struct s_smc *smc, int class, int type,
485 int length); /* smt.c */
486SMbuf *smt_get_mbuf(struct s_smc *smc); /* drvsr.c */
487void *sm_to_para(struct s_smc *smc, struct smt_header *sm,
488 int para); /* smt.c */
489
490#ifndef SK_UNUSED
491#define SK_UNUSED(var) (void)(var)
492#endif
493
494void queue_event(struct s_smc *smc, int class, int event);
495void ecm(struct s_smc *smc, int event);
496void ecm_init(struct s_smc *smc);
497void rmt(struct s_smc *smc, int event);
498void rmt_init(struct s_smc *smc);
499void pcm(struct s_smc *smc, const int np, int event);
500void pcm_init(struct s_smc *smc);
501void cfm(struct s_smc *smc, int event);
502void cfm_init(struct s_smc *smc);
503void smt_timer_start(struct s_smc *smc, struct smt_timer *timer, u_long time,
504 u_long token);
505void smt_timer_stop(struct s_smc *smc, struct smt_timer *timer);
506void pcm_status_state(struct s_smc *smc, int np, int *type, int *state,
507 int *remote, int *mac);
508void plc_config_mux(struct s_smc *smc, int mux);
509void sm_lem_evaluate(struct s_smc *smc);
510void mac_update_counter(struct s_smc *smc);
511void sm_pm_ls_latch(struct s_smc *smc, int phy, int on_off);
512void sm_ma_control(struct s_smc *smc, int mode);
513void sm_mac_check_beacon_claim(struct s_smc *smc);
514void config_mux(struct s_smc *smc, int mux);
515void smt_agent_init(struct s_smc *smc);
516void smt_timer_init(struct s_smc *smc);
517void smt_received_pack(struct s_smc *smc, SMbuf *mb, int fs);
518void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
519 int index, int local);
520void smt_swap_para(struct smt_header *sm, int len, int direction);
521void ev_init(struct s_smc *smc);
522void hwt_init(struct s_smc *smc);
523u_long hwt_read(struct s_smc *smc);
524void hwt_stop(struct s_smc *smc);
525void hwt_start(struct s_smc *smc, u_long time);
526void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc);
527void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
528void sm_pm_bypass_req(struct s_smc *smc, int mode);
529void rmt_indication(struct s_smc *smc, int i);
530void cfm_state_change(struct s_smc *smc, int c_state);
531
532#if defined(DEBUG) || !defined(NO_SMT_PANIC)
533void smt_panic(struct s_smc *smc, char *text);
534#else
535#define smt_panic(smc,text)
536#endif /* DEBUG || !NO_SMT_PANIC */
537
538void smt_stat_counter(struct s_smc *smc, int stat);
539void smt_timer_poll(struct s_smc *smc);
540u_long smt_get_time(void);
541u_long smt_get_tid(struct s_smc *smc);
542void smt_timer_done(struct s_smc *smc);
543void smt_fixup_mib(struct s_smc *smc);
544void smt_reset_defaults(struct s_smc *smc, int level);
545void smt_agent_task(struct s_smc *smc);
546int smt_check_para(struct s_smc *smc, struct smt_header *sm,
547 const u_short list[]);
548void driver_get_bia(struct s_smc *smc, struct fddi_addr *bia_addr);
549
550#ifdef SUPERNET_3
551void drv_reset_indication(struct s_smc *smc);
552#endif /* SUPERNET_3 */
553
554void smt_start_watchdog(struct s_smc *smc);
555void smt_event(struct s_smc *smc, int event);
556void timer_event(struct s_smc *smc, u_long token);
557void ev_dispatcher(struct s_smc *smc);
558void pcm_get_state(struct s_smc *smc, struct smt_state *state);
559void ecm_state_change(struct s_smc *smc, int e_state);
560int sm_pm_bypass_present(struct s_smc *smc);
561void pcm_state_change(struct s_smc *smc, int plc, int p_state);
562void rmt_state_change(struct s_smc *smc, int r_state);
563int sm_pm_get_ls(struct s_smc *smc, int phy);
564int pcm_get_s_port(struct s_smc *smc);
565int pcm_rooted_station(struct s_smc *smc);
566int cfm_get_mac_input(struct s_smc *smc);
567int cfm_get_mac_output(struct s_smc *smc);
568int cem_build_path(struct s_smc *smc, char *to, int path_index);
569int sm_mac_get_tx_state(struct s_smc *smc);
570char *get_pcmstate(struct s_smc *smc, int np);
571int smt_action(struct s_smc *smc, int class, int code, int index);
572u_short smt_online(struct s_smc *smc, int on);
573void smt_force_irq(struct s_smc *smc);
574void smt_pmf_received_pack(struct s_smc *smc, SMbuf *mb, int local);
575void smt_send_frame(struct s_smc *smc, SMbuf *mb, int fc, int local);
576void smt_set_timestamp(struct s_smc *smc, u_char *p);
577void mac_set_rx_mode(struct s_smc *smc, int mode);
578int mac_add_multicast(struct s_smc *smc, struct fddi_addr *addr, int can);
579void mac_update_multicast(struct s_smc *smc);
580void mac_clear_multicast(struct s_smc *smc);
581void set_formac_tsync(struct s_smc *smc, long sync_bw);
582void formac_reinit_tx(struct s_smc *smc);
583void formac_tx_restart(struct s_smc *smc);
584void process_receive(struct s_smc *smc);
585void init_driver_fplus(struct s_smc *smc);
586void rtm_irq(struct s_smc *smc);
587void rtm_set_timer(struct s_smc *smc);
588void ring_status_indication(struct s_smc *smc, u_long status);
589void llc_recover_tx(struct s_smc *smc);
590void llc_restart_tx(struct s_smc *smc);
591void plc_clear_irq(struct s_smc *smc, int p);
592void plc_irq(struct s_smc *smc, int np, unsigned int cmd);
593int smt_set_mac_opvalues(struct s_smc *smc);
594
595#ifdef TAG_MODE
596void mac_do_pci_fix(struct s_smc *smc);
597void mac_drv_clear_tx_queue(struct s_smc *smc);
598void mac_drv_repair_descr(struct s_smc *smc);
599u_long hwt_quick_read(struct s_smc *smc);
600void hwt_wait_time(struct s_smc *smc, u_long start, long duration);
601#endif
602
603#ifdef SMT_PNMI
604int pnmi_init(struct s_smc* smc);
605int pnmi_process_ndis_id(struct s_smc *smc, u_long ndis_oid, void *buf, int len,
606 int *BytesAccessed, int *BytesNeeded, u_char action);
607#endif
608
609#ifdef SBA
610#ifndef _H2INC
611void sba();
612#endif
613void sba_raf_received_pack();
614void sba_timer_poll();
615void smt_init_sba();
616#endif
617
618#ifdef ESS
619int ess_raf_received_pack(struct s_smc *smc, SMbuf *mb, struct smt_header *sm,
620 int fs);
621void ess_timer_poll(struct s_smc *smc);
622void ess_para_change(struct s_smc *smc);
623#endif
624
625#ifndef BOOT
626void smt_init_evc(struct s_smc *smc);
627void smt_srf_event(struct s_smc *smc, int code, int index, int cond);
628#else
629#define smt_init_evc(smc)
630#define smt_srf_event(smc,code,index,cond)
631#endif
632
633#ifndef SMT_REAL_TOKEN_CT
634void smt_emulate_token_ct(struct s_smc *smc, int mac_index);
635#endif
636
637#if defined(DEBUG) && !defined(BOOT)
638void dump_smt(struct s_smc *smc, struct smt_header *sm, char *text);
639#else
640#define dump_smt(smc,sm,text)
641#endif
642
643#ifdef DEBUG
644char* addr_to_string(struct fddi_addr *addr);
645void dump_hex(char *p, int len);
646#endif
647
648#endif /* PROTOTYP_INC */
649
650/* PNMI default defines */
651#ifndef PNMI_INIT
652#define PNMI_INIT(smc) /* Nothing */
653#endif
654#ifndef PNMI_GET_ID
655#define PNMI_GET_ID( smc, ndis_oid, buf, len, BytesWritten, BytesNeeded ) \
656 ( 1 ? (-1) : (-1) )
657#endif
658#ifndef PNMI_SET_ID
659#define PNMI_SET_ID( smc, ndis_oid, buf, len, BytesRead, BytesNeeded, \
660 set_type) ( 1 ? (-1) : (-1) )
661#endif
662
663/*
664 * SMT_PANIC defines
665 */
666#ifndef SMT_PANIC
667#define SMT_PANIC(smc,nr,msg) smt_panic (smc, msg)
668#endif
669
670#ifndef SMT_ERR_LOG
671#define SMT_ERR_LOG(smc,nr,msg) SMT_PANIC (smc, nr, msg)
672#endif
673
674#ifndef SMT_EBASE
675#define SMT_EBASE 100
676#endif
677
678#define SMT_E0100 SMT_EBASE + 0
679#define SMT_E0100_MSG "cfm FSM: invalid ce_type"
680#define SMT_E0101 SMT_EBASE + 1
681#define SMT_E0101_MSG "CEM: case ???"
682#define SMT_E0102 SMT_EBASE + 2
683#define SMT_E0102_MSG "CEM A: invalid state"
684#define SMT_E0103 SMT_EBASE + 3
685#define SMT_E0103_MSG "CEM B: invalid state"
686#define SMT_E0104 SMT_EBASE + 4
687#define SMT_E0104_MSG "CEM M: invalid state"
688#define SMT_E0105 SMT_EBASE + 5
689#define SMT_E0105_MSG "CEM S: invalid state"
690#define SMT_E0106 SMT_EBASE + 6
691#define SMT_E0106_MSG "CFM : invalid state"
692#define SMT_E0107 SMT_EBASE + 7
693#define SMT_E0107_MSG "ECM : invalid state"
694#define SMT_E0108 SMT_EBASE + 8
695#define SMT_E0108_MSG "prop_actions : NAC in DAS CFM"
696#define SMT_E0109 SMT_EBASE + 9
697#define SMT_E0109_MSG "ST2U.FM_SERRSF error in special frame"
698#define SMT_E0110 SMT_EBASE + 10
699#define SMT_E0110_MSG "ST2U.FM_SRFRCTOV recv. count. overflow"
700#define SMT_E0111 SMT_EBASE + 11
701#define SMT_E0111_MSG "ST2U.FM_SNFSLD NP & FORMAC simult. load"
702#define SMT_E0112 SMT_EBASE + 12
703#define SMT_E0112_MSG "ST2U.FM_SRCVFRM single-frame recv.-mode"
704#define SMT_E0113 SMT_EBASE + 13
705#define SMT_E0113_MSG "FPLUS: Buffer Memory Error"
706#define SMT_E0114 SMT_EBASE + 14
707#define SMT_E0114_MSG "ST2U.FM_SERRSF error in special frame"
708#define SMT_E0115 SMT_EBASE + 15
709#define SMT_E0115_MSG "ST3L: parity error in receive queue 2"
710#define SMT_E0116 SMT_EBASE + 16
711#define SMT_E0116_MSG "ST3L: parity error in receive queue 1"
712#define SMT_E0117 SMT_EBASE + 17
713#define SMT_E0117_MSG "E_SMT_001: RxD count for receive queue 1 = 0"
714#define SMT_E0118 SMT_EBASE + 18
715#define SMT_E0118_MSG "PCM : invalid state"
716#define SMT_E0119 SMT_EBASE + 19
717#define SMT_E0119_MSG "smt_add_para"
718#define SMT_E0120 SMT_EBASE + 20
719#define SMT_E0120_MSG "smt_set_para"
720#define SMT_E0121 SMT_EBASE + 21
721#define SMT_E0121_MSG "invalid event in dispatcher"
722#define SMT_E0122 SMT_EBASE + 22
723#define SMT_E0122_MSG "RMT : invalid state"
724#define SMT_E0123 SMT_EBASE + 23
725#define SMT_E0123_MSG "SBA: state machine has invalid state"
726#define SMT_E0124 SMT_EBASE + 24
727#define SMT_E0124_MSG "sba_free_session() called with NULL pointer"
728#define SMT_E0125 SMT_EBASE + 25
729#define SMT_E0125_MSG "SBA : invalid session pointer"
730#define SMT_E0126 SMT_EBASE + 26
731#define SMT_E0126_MSG "smt_free_mbuf() called with NULL pointer\n"
732#define SMT_E0127 SMT_EBASE + 27
733#define SMT_E0127_MSG "sizeof evcs"
734#define SMT_E0128 SMT_EBASE + 28
735#define SMT_E0128_MSG "evc->evc_cond_state = 0"
736#define SMT_E0129 SMT_EBASE + 29
737#define SMT_E0129_MSG "evc->evc_multiple = 0"
738#define SMT_E0130 SMT_EBASE + 30
739#define SMT_E0130_MSG write_mdr_warning
740#define SMT_E0131 SMT_EBASE + 31
741#define SMT_E0131_MSG cam_warning
742#define SMT_E0132 SMT_EBASE + 32
743#define SMT_E0132_MSG "ST1L.FM_SPCEPDx parity/coding error"
744#define SMT_E0133 SMT_EBASE + 33
745#define SMT_E0133_MSG "ST1L.FM_STBURx tx buffer underrun"
746#define SMT_E0134 SMT_EBASE + 34
747#define SMT_E0134_MSG "ST1L.FM_SPCEPDx parity error"
748#define SMT_E0135 SMT_EBASE + 35
749#define SMT_E0135_MSG "RMT: duplicate MAC address detected. Ring left!"
750#define SMT_E0136 SMT_EBASE + 36
751#define SMT_E0136_MSG "Elasticity Buffer hang-up"
752#define SMT_E0137 SMT_EBASE + 37
753#define SMT_E0137_MSG "SMT: queue overrun"
754#define SMT_E0138 SMT_EBASE + 38
755#define SMT_E0138_MSG "RMT: duplicate MAC address detected. Ring NOT left!"
756#endif /* _CMTDEF_ */
diff --git a/drivers/net/skfp/h/fddi.h b/drivers/net/skfp/h/fddi.h
deleted file mode 100644
index c9a28a8a383b..000000000000
--- a/drivers/net/skfp/h/fddi.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _FDDI_
16#define _FDDI_
17
18struct fddi_addr {
19 u_char a[6] ;
20} ;
21
22#define GROUP_ADDR 0x80 /* MSB in a[0] */
23
24struct fddi_mac {
25 struct fddi_addr mac_dest ;
26 struct fddi_addr mac_source ;
27 u_char mac_info[4478] ;
28} ;
29
30#define FDDI_MAC_SIZE (12)
31#define FDDI_RAW_MTU (4500-5) /* exl. Pr,SD, ED/FS */
32#define FDDI_RAW (4500)
33
34/*
35 * FC values
36 */
37#define FC_VOID 0x40 /* void frame */
38#define FC_TOKEN 0x80 /* token */
39#define FC_RES_TOKEN 0xc0 /* restricted token */
40#define FC_SMT_INFO 0x41 /* SMT Info frame */
41/*
42 * FC_SMT_LAN_LOC && FC_SMT_LOC are SK specific !
43 */
44#define FC_SMT_LAN_LOC 0x42 /* local SMT Info frame */
45#define FC_SMT_LOC 0x43 /* local SMT Info frame */
46#define FC_SMT_NSA 0x4f /* SMT NSA frame */
47#define FC_MAC 0xc0 /* MAC frame */
48#define FC_BEACON 0xc2 /* MAC beacon frame */
49#define FC_CLAIM 0xc3 /* MAC claim frame */
50#define FC_SYNC_LLC 0xd0 /* sync. LLC frame */
51#define FC_ASYNC_LLC 0x50 /* async. LLC frame */
52#define FC_SYNC_BIT 0x80 /* sync. bit in FC */
53
54#define FC_LLC_PRIOR 0x07 /* priority bits */
55
56#define BEACON_INFO 0 /* beacon type */
57#define DBEACON_INFO 1 /* beacon type DIRECTED */
58
59
60/*
61 * indicator bits
62 */
63#define C_INDICATOR (1<<0)
64#define A_INDICATOR (1<<1)
65#define E_INDICATOR (1<<2)
66#define I_INDICATOR (1<<6) /* SK specific */
67#define L_INDICATOR (1<<7) /* SK specific */
68
69#endif /* _FDDI_ */
diff --git a/drivers/net/skfp/h/fddimib.h b/drivers/net/skfp/h/fddimib.h
deleted file mode 100644
index d1acdc773950..000000000000
--- a/drivers/net/skfp/h/fddimib.h
+++ /dev/null
@@ -1,349 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 * FDDI MIB
17 */
18
19/*
20 * typedefs
21 */
22
23typedef u_long Counter ;
24typedef u_char TimeStamp[8] ;
25typedef struct fddi_addr LongAddr ;
26typedef u_long Timer_2 ;
27typedef u_long Timer ;
28typedef u_short ResId ;
29typedef u_short SMTEnum ;
30typedef u_char SMTFlag ;
31
32typedef struct {
33 Counter count ;
34 TimeStamp timestamp ;
35} SetCountType ;
36
37/*
38 * bits for bit string "available_path"
39 */
40#define MIB_PATH_P (1<<0)
41#define MIB_PATH_S (1<<1)
42#define MIB_PATH_L (1<<2)
43
44/*
45 * bits for bit string PermittedPaths & RequestedPaths (SIZE(8))
46 */
47#define MIB_P_PATH_LOCAL (1<<0)
48#define MIB_P_PATH_SEC_ALTER (1<<1)
49#define MIB_P_PATH_PRIM_ALTER (1<<2)
50#define MIB_P_PATH_CON_ALTER (1<<3)
51#define MIB_P_PATH_SEC_PREFER (1<<4)
52#define MIB_P_PATH_PRIM_PREFER (1<<5)
53#define MIB_P_PATH_CON_PREFER (1<<6)
54#define MIB_P_PATH_THRU (1<<7)
55
56/*
57 * enum current path
58 */
59#define MIB_PATH_ISOLATED 0
60#define MIB_PATH_LOCAL 1
61#define MIB_PATH_SECONDARY 2
62#define MIB_PATH_PRIMARY 3
63#define MIB_PATH_CONCATENATED 4
64#define MIB_PATH_THRU 5
65
66/*
67 * enum PMDClass
68 */
69#define MIB_PMDCLASS_MULTI 0
70#define MIB_PMDCLASS_SINGLE1 1
71#define MIB_PMDCLASS_SINGLE2 2
72#define MIB_PMDCLASS_SONET 3
73#define MIB_PMDCLASS_LCF 4
74#define MIB_PMDCLASS_TP 5
75#define MIB_PMDCLASS_UNKNOWN 6
76#define MIB_PMDCLASS_UNSPEC 7
77
78/*
79 * enum SMTStationStatus
80 */
81#define MIB_SMT_STASTA_CON 0
82#define MIB_SMT_STASTA_SEPA 1
83#define MIB_SMT_STASTA_THRU 2
84
85
86struct fddi_mib {
87 /*
88 * private
89 */
90 u_char fddiPRPMFPasswd[8] ;
91 struct smt_sid fddiPRPMFStation ;
92
93#ifdef ESS
94 /*
95 * private variables for static allocation of the
96 * End Station Support
97 */
98 u_long fddiESSPayload ; /* payload for static alloc */
99 u_long fddiESSOverhead ; /* frame ov for static alloc */
100 u_long fddiESSMaxTNeg ; /* maximum of T-NEG */
101 u_long fddiESSMinSegmentSize ; /* min size of the sync frames */
102 u_long fddiESSCategory ; /* category for the Alloc req */
103 short fddiESSSynchTxMode ; /* send all LLC frames as sync */
104#endif /* ESS */
105#ifdef SBA
106 /*
107 * private variables for the Synchronous Bandwidth Allocator
108 */
109 char fddiSBACommand ; /* holds the parsed SBA cmd */
110 u_char fddiSBAAvailable ; /* SBA allocatable value */
111#endif /* SBA */
112
113 /*
114 * SMT standard mib
115 */
116 struct smt_sid fddiSMTStationId ;
117 u_short fddiSMTOpVersionId ;
118 u_short fddiSMTHiVersionId ;
119 u_short fddiSMTLoVersionId ;
120 u_char fddiSMTManufacturerData[32] ;
121 u_char fddiSMTUserData[32] ;
122 u_short fddiSMTMIBVersionId ;
123
124 /*
125 * ConfigGrp
126 */
127 u_char fddiSMTMac_Ct ;
128 u_char fddiSMTNonMaster_Ct ;
129 u_char fddiSMTMaster_Ct ;
130 u_char fddiSMTAvailablePaths ;
131 u_short fddiSMTConfigCapabilities ;
132 u_short fddiSMTConfigPolicy ;
133 u_short fddiSMTConnectionPolicy ;
134 u_short fddiSMTTT_Notify ;
135 u_char fddiSMTStatRptPolicy ;
136 u_long fddiSMTTrace_MaxExpiration ;
137 u_short fddiSMTPORTIndexes[NUMPHYS] ;
138 u_short fddiSMTMACIndexes ;
139 u_char fddiSMTBypassPresent ;
140
141 /*
142 * StatusGrp
143 */
144 SMTEnum fddiSMTECMState ;
145 SMTEnum fddiSMTCF_State ;
146 SMTEnum fddiSMTStationStatus ;
147 u_char fddiSMTRemoteDisconnectFlag ;
148 u_char fddiSMTPeerWrapFlag ;
149
150 /*
151 * MIBOperationGrp
152 */
153 TimeStamp fddiSMTTimeStamp ;
154 TimeStamp fddiSMTTransitionTimeStamp ;
155 SetCountType fddiSMTSetCount ;
156 struct smt_sid fddiSMTLastSetStationId ;
157
158 struct fddi_mib_m {
159 u_short fddiMACFrameStatusFunctions ;
160 Timer_2 fddiMACT_MaxCapabilitiy ;
161 Timer_2 fddiMACTVXCapabilitiy ;
162
163 /* ConfigGrp */
164 u_char fddiMACMultiple_N ; /* private */
165 u_char fddiMACMultiple_P ; /* private */
166 u_char fddiMACDuplicateAddressCond ;/* private */
167 u_char fddiMACAvailablePaths ;
168 u_short fddiMACCurrentPath ;
169 LongAddr fddiMACUpstreamNbr ;
170 LongAddr fddiMACDownstreamNbr ;
171 LongAddr fddiMACOldUpstreamNbr ;
172 LongAddr fddiMACOldDownstreamNbr ;
173 SMTEnum fddiMACDupAddressTest ;
174 u_short fddiMACRequestedPaths ;
175 SMTEnum fddiMACDownstreamPORTType ;
176 ResId fddiMACIndex ;
177
178 /* AddressGrp */
179 LongAddr fddiMACSMTAddress ;
180
181 /* OperationGrp */
182 Timer_2 fddiMACT_Min ; /* private */
183 Timer_2 fddiMACT_ReqMIB ;
184 Timer_2 fddiMACT_Req ; /* private */
185 Timer_2 fddiMACT_Neg ;
186 Timer_2 fddiMACT_MaxMIB ;
187 Timer_2 fddiMACT_Max ; /* private */
188 Timer_2 fddiMACTvxValueMIB ;
189 Timer_2 fddiMACTvxValue ; /* private */
190 Timer_2 fddiMACT_Pri0 ;
191 Timer_2 fddiMACT_Pri1 ;
192 Timer_2 fddiMACT_Pri2 ;
193 Timer_2 fddiMACT_Pri3 ;
194 Timer_2 fddiMACT_Pri4 ;
195 Timer_2 fddiMACT_Pri5 ;
196 Timer_2 fddiMACT_Pri6 ;
197
198 /* CountersGrp */
199 Counter fddiMACFrame_Ct ;
200 Counter fddiMACCopied_Ct ;
201 Counter fddiMACTransmit_Ct ;
202 Counter fddiMACToken_Ct ;
203 Counter fddiMACError_Ct ;
204 Counter fddiMACLost_Ct ;
205 Counter fddiMACTvxExpired_Ct ;
206 Counter fddiMACNotCopied_Ct ;
207 Counter fddiMACRingOp_Ct ;
208
209 Counter fddiMACSMTCopied_Ct ; /* private */
210 Counter fddiMACSMTTransmit_Ct ; /* private */
211
212 /* private for delta ratio */
213 Counter fddiMACOld_Frame_Ct ;
214 Counter fddiMACOld_Copied_Ct ;
215 Counter fddiMACOld_Error_Ct ;
216 Counter fddiMACOld_Lost_Ct ;
217 Counter fddiMACOld_NotCopied_Ct ;
218
219 /* FrameErrorConditionGrp */
220 u_short fddiMACFrameErrorThreshold ;
221 u_short fddiMACFrameErrorRatio ;
222
223 /* NotCopiedConditionGrp */
224 u_short fddiMACNotCopiedThreshold ;
225 u_short fddiMACNotCopiedRatio ;
226
227 /* StatusGrp */
228 SMTEnum fddiMACRMTState ;
229 SMTFlag fddiMACDA_Flag ;
230 SMTFlag fddiMACUNDA_Flag ;
231 SMTFlag fddiMACFrameErrorFlag ;
232 SMTFlag fddiMACNotCopiedFlag ;
233 SMTFlag fddiMACMA_UnitdataAvailable ;
234 SMTFlag fddiMACHardwarePresent ;
235 SMTFlag fddiMACMA_UnitdataEnable ;
236
237 } m[NUMMACS] ;
238#define MAC0 0
239
240 struct fddi_mib_a {
241 ResId fddiPATHIndex ;
242 u_long fddiPATHSbaPayload ;
243 u_long fddiPATHSbaOverhead ;
244 /* fddiPATHConfiguration is built on demand */
245 /* u_long fddiPATHConfiguration ; */
246 Timer fddiPATHT_Rmode ;
247 u_long fddiPATHSbaAvailable ;
248 Timer_2 fddiPATHTVXLowerBound ;
249 Timer_2 fddiPATHT_MaxLowerBound ;
250 Timer_2 fddiPATHMaxT_Req ;
251 } a[NUMPATHS] ;
252#define PATH0 0
253
254 struct fddi_mib_p {
255 /* ConfigGrp */
256 SMTEnum fddiPORTMy_Type ;
257 SMTEnum fddiPORTNeighborType ;
258 u_char fddiPORTConnectionPolicies ;
259 struct {
260 u_char T_val ;
261 u_char R_val ;
262 } fddiPORTMacIndicated ;
263 SMTEnum fddiPORTCurrentPath ;
264 /* must be 4: is 32 bit in SMT format
265 * indices :
266 * 1 none
267 * 2 tree
268 * 3 peer
269 */
270 u_char fddiPORTRequestedPaths[4] ;
271 u_short fddiPORTMACPlacement ;
272 u_char fddiPORTAvailablePaths ;
273 u_char fddiPORTConnectionCapabilities ;
274 SMTEnum fddiPORTPMDClass ;
275 ResId fddiPORTIndex ;
276
277 /* OperationGrp */
278 SMTEnum fddiPORTMaint_LS ;
279 SMTEnum fddiPORTPC_LS ;
280 u_char fddiPORTBS_Flag ;
281
282 /* ErrorCtrsGrp */
283 Counter fddiPORTLCTFail_Ct ;
284 Counter fddiPORTEBError_Ct ;
285 Counter fddiPORTOldEBError_Ct ;
286
287 /* LerGrp */
288 Counter fddiPORTLem_Reject_Ct ;
289 Counter fddiPORTLem_Ct ;
290 u_char fddiPORTLer_Estimate ;
291 u_char fddiPORTLer_Cutoff ;
292 u_char fddiPORTLer_Alarm ;
293
294 /* StatusGrp */
295 SMTEnum fddiPORTConnectState ;
296 SMTEnum fddiPORTPCMState ; /* real value */
297 SMTEnum fddiPORTPCMStateX ; /* value for MIB */
298 SMTEnum fddiPORTPC_Withhold ;
299 SMTFlag fddiPORTHardwarePresent ;
300 u_char fddiPORTLerFlag ;
301
302 u_char fddiPORTMultiple_U ; /* private */
303 u_char fddiPORTMultiple_P ; /* private */
304 u_char fddiPORTEB_Condition ; /* private */
305 } p[NUMPHYS] ;
306 struct {
307 Counter fddiPRIVECF_Req_Rx ; /* ECF req received */
308 Counter fddiPRIVECF_Reply_Rx ; /* ECF repl received */
309 Counter fddiPRIVECF_Req_Tx ; /* ECF req transm */
310 Counter fddiPRIVECF_Reply_Tx ; /* ECF repl transm */
311 Counter fddiPRIVPMF_Get_Rx ; /* PMF Get rec */
312 Counter fddiPRIVPMF_Set_Rx ; /* PMF Set rec */
313 Counter fddiPRIVRDF_Rx ; /* RDF received */
314 Counter fddiPRIVRDF_Tx ; /* RDF transmitted */
315 } priv ;
316} ;
317
318/*
319 * OIDs for statistics
320 */
321#define SMT_OID_CF_STATE 1 /* fddiSMTCF_State */
322#define SMT_OID_PCM_STATE_A 2 /* fddiPORTPCMState port A */
323#define SMT_OID_PCM_STATE_B 17 /* fddiPORTPCMState port B */
324#define SMT_OID_RMT_STATE 3 /* fddiMACRMTState */
325#define SMT_OID_UNA 4 /* fddiMACUpstreamNbr */
326#define SMT_OID_DNA 5 /* fddiMACOldDownstreamNbr */
327#define SMT_OID_ERROR_CT 6 /* fddiMACError_Ct */
328#define SMT_OID_LOST_CT 7 /* fddiMACLost_Ct */
329#define SMT_OID_LEM_CT 8 /* fddiPORTLem_Ct */
330#define SMT_OID_LEM_CT_A 11 /* fddiPORTLem_Ct port A */
331#define SMT_OID_LEM_CT_B 12 /* fddiPORTLem_Ct port B */
332#define SMT_OID_LCT_FAIL_CT 9 /* fddiPORTLCTFail_Ct */
333#define SMT_OID_LCT_FAIL_CT_A 13 /* fddiPORTLCTFail_Ct port A */
334#define SMT_OID_LCT_FAIL_CT_B 14 /* fddiPORTLCTFail_Ct port B */
335#define SMT_OID_LEM_REJECT_CT 10 /* fddiPORTLem_Reject_Ct */
336#define SMT_OID_LEM_REJECT_CT_A 15 /* fddiPORTLem_Reject_Ct port A */
337#define SMT_OID_LEM_REJECT_CT_B 16 /* fddiPORTLem_Reject_Ct port B */
338
339/*
340 * SK MIB
341 */
342#define SMT_OID_ECF_REQ_RX 20 /* ECF requests received */
343#define SMT_OID_ECF_REPLY_RX 21 /* ECF replies received */
344#define SMT_OID_ECF_REQ_TX 22 /* ECF requests transmitted */
345#define SMT_OID_ECF_REPLY_TX 23 /* ECF replies transmitted */
346#define SMT_OID_PMF_GET_RX 24 /* PMF get requests received */
347#define SMT_OID_PMF_SET_RX 25 /* PMF set requests received */
348#define SMT_OID_RDF_RX 26 /* RDF received */
349#define SMT_OID_RDF_TX 27 /* RDF transmitted */
diff --git a/drivers/net/skfp/h/fplustm.h b/drivers/net/skfp/h/fplustm.h
deleted file mode 100644
index d43191ed938b..000000000000
--- a/drivers/net/skfp/h/fplustm.h
+++ /dev/null
@@ -1,274 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 * AMD Fplus in tag mode data structs
17 * defs for fplustm.c
18 */
19
20#ifndef _FPLUS_
21#define _FPLUS_
22
23#ifndef HW_PTR
24#define HW_PTR void __iomem *
25#endif
26
27/*
28 * fplus error statistic structure
29 */
30struct err_st {
31 u_long err_valid ; /* memory status valid */
32 u_long err_abort ; /* memory status receive abort */
33 u_long err_e_indicator ; /* error indicator */
34 u_long err_crc ; /* error detected (CRC or length) */
35 u_long err_llc_frame ; /* LLC frame */
36 u_long err_mac_frame ; /* MAC frame */
37 u_long err_smt_frame ; /* SMT frame */
38 u_long err_imp_frame ; /* implementer frame */
39 u_long err_no_buf ; /* no buffer available */
40 u_long err_too_long ; /* longer than max. buffer */
41 u_long err_bec_stat ; /* beacon state entered */
42 u_long err_clm_stat ; /* claim state entered */
43 u_long err_sifg_det ; /* short interframe gap detect */
44 u_long err_phinv ; /* PHY invalid */
45 u_long err_tkiss ; /* token issued */
46 u_long err_tkerr ; /* token error */
47} ;
48
49/*
50 * Transmit Descriptor struct
51 */
52struct s_smt_fp_txd {
53 __le32 txd_tbctrl ; /* transmit buffer control */
54 __le32 txd_txdscr ; /* transmit frame status word */
55 __le32 txd_tbadr ; /* physical tx buffer address */
56 __le32 txd_ntdadr ; /* physical pointer to the next TxD */
57#ifdef ENA_64BIT_SUP
58 __le32 txd_tbadr_hi ; /* physical tx buffer addr (high dword)*/
59#endif
60 char far *txd_virt ; /* virtual pointer to the data frag */
61 /* virt pointer to the next TxD */
62 struct s_smt_fp_txd volatile far *txd_next ;
63 struct s_txd_os txd_os ; /* OS - specific struct */
64} ;
65
66/*
67 * Receive Descriptor struct
68 */
69struct s_smt_fp_rxd {
70 __le32 rxd_rbctrl ; /* receive buffer control */
71 __le32 rxd_rfsw ; /* receive frame status word */
72 __le32 rxd_rbadr ; /* physical rx buffer address */
73 __le32 rxd_nrdadr ; /* physical pointer to the next RxD */
74#ifdef ENA_64BIT_SUP
75 __le32 rxd_rbadr_hi ; /* physical tx buffer addr (high dword)*/
76#endif
77 char far *rxd_virt ; /* virtual pointer to the data frag */
78 /* virt pointer to the next RxD */
79 struct s_smt_fp_rxd volatile far *rxd_next ;
80 struct s_rxd_os rxd_os ; /* OS - specific struct */
81} ;
82
83/*
84 * Descriptor Union Definition
85 */
86union s_fp_descr {
87 struct s_smt_fp_txd t ; /* pointer to the TxD */
88 struct s_smt_fp_rxd r ; /* pointer to the RxD */
89} ;
90
91/*
92 * TxD Ring Control struct
93 */
94struct s_smt_tx_queue {
95 struct s_smt_fp_txd volatile *tx_curr_put ; /* next free TxD */
96 struct s_smt_fp_txd volatile *tx_prev_put ; /* shadow put pointer */
97 struct s_smt_fp_txd volatile *tx_curr_get ; /* next TxD to release*/
98 u_short tx_free ; /* count of free TxD's */
99 u_short tx_used ; /* count of used TxD's */
100 HW_PTR tx_bmu_ctl ; /* BMU addr for tx start */
101 HW_PTR tx_bmu_dsc ; /* BMU addr for curr dsc. */
102} ;
103
104/*
105 * RxD Ring Control struct
106 */
107struct s_smt_rx_queue {
108 struct s_smt_fp_rxd volatile *rx_curr_put ; /* next RxD to queue into */
109 struct s_smt_fp_rxd volatile *rx_prev_put ; /* shadow put pointer */
110 struct s_smt_fp_rxd volatile *rx_curr_get ; /* next RxD to fill */
111 u_short rx_free ; /* count of free RxD's */
112 u_short rx_used ; /* count of used RxD's */
113 HW_PTR rx_bmu_ctl ; /* BMU addr for rx start */
114 HW_PTR rx_bmu_dsc ; /* BMU addr for curr dsc. */
115} ;
116
117#define VOID_FRAME_OFF 0x00
118#define CLAIM_FRAME_OFF 0x08
119#define BEACON_FRAME_OFF 0x10
120#define DBEACON_FRAME_OFF 0x18
121#define RX_FIFO_OFF 0x21 /* to get a prime number for */
122 /* the RX_FIFO_SPACE */
123
124#define RBC_MEM_SIZE 0x8000
125#define SEND_ASYNC_AS_SYNC 0x1
126#define SYNC_TRAFFIC_ON 0x2
127
128/* big FIFO memory */
129#define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
130#define TX_FIFO_SPACE 0x4000
131
132#define TX_SMALL_FIFO 0x0900
133#define TX_MEDIUM_FIFO TX_FIFO_SPACE / 2
134#define TX_LARGE_FIFO TX_FIFO_SPACE - TX_SMALL_FIFO
135
136#define RX_SMALL_FIFO 0x0900
137#define RX_LARGE_FIFO RX_FIFO_SPACE - RX_SMALL_FIFO
138
139struct s_smt_fifo_conf {
140 u_short rbc_ram_start ; /* FIFO start address */
141 u_short rbc_ram_end ; /* FIFO size */
142 u_short rx1_fifo_start ; /* rx queue start address */
143 u_short rx1_fifo_size ; /* rx queue size */
144 u_short rx2_fifo_start ; /* rx queue start address */
145 u_short rx2_fifo_size ; /* rx queue size */
146 u_short tx_s_start ; /* sync queue start address */
147 u_short tx_s_size ; /* sync queue size */
148 u_short tx_a0_start ; /* async queue A0 start address */
149 u_short tx_a0_size ; /* async queue A0 size */
150 u_short fifo_config_mode ; /* FIFO configuration mode */
151} ;
152
153#define FM_ADDRX (FM_ADDET|FM_EXGPA0|FM_EXGPA1)
154
155struct s_smt_fp {
156 u_short mdr2init ; /* mode register 2 init value */
157 u_short mdr3init ; /* mode register 3 init value */
158 u_short frselreg_init ; /* frame selection register init val */
159 u_short rx_mode ; /* address mode broad/multi/promisc */
160 u_short nsa_mode ;
161 u_short rx_prom ;
162 u_short exgpa ;
163
164 struct err_st err_stats ; /* error statistics */
165
166 /*
167 * MAC buffers
168 */
169 struct fddi_mac_sf { /* special frame build buffer */
170 u_char mac_fc ;
171 struct fddi_addr mac_dest ;
172 struct fddi_addr mac_source ;
173 u_char mac_info[0x20] ;
174 } mac_sfb ;
175
176
177 /*
178 * queues
179 */
180#define QUEUE_S 0
181#define QUEUE_A0 1
182#define QUEUE_R1 0
183#define QUEUE_R2 1
184#define USED_QUEUES 2
185
186 /*
187 * queue pointers; points to the queue dependent variables
188 */
189 struct s_smt_tx_queue *tx[USED_QUEUES] ;
190 struct s_smt_rx_queue *rx[USED_QUEUES] ;
191
192 /*
193 * queue dependent variables
194 */
195 struct s_smt_tx_queue tx_q[USED_QUEUES] ;
196 struct s_smt_rx_queue rx_q[USED_QUEUES] ;
197
198 /*
199 * FIFO configuration struct
200 */
201 struct s_smt_fifo_conf fifo ;
202
203 /* last formac status */
204 u_short s2u ;
205 u_short s2l ;
206
207 /* calculated FORMAC+ reg.addr. */
208 HW_PTR fm_st1u ;
209 HW_PTR fm_st1l ;
210 HW_PTR fm_st2u ;
211 HW_PTR fm_st2l ;
212 HW_PTR fm_st3u ;
213 HW_PTR fm_st3l ;
214
215
216 /*
217 * multicast table
218 */
219#define FPMAX_MULTICAST 32
220#define SMT_MAX_MULTI 4
221 struct {
222 struct s_fpmc {
223 struct fddi_addr a ; /* mc address */
224 u_char n ; /* usage counter */
225 u_char perm ; /* flag: permanent */
226 } table[FPMAX_MULTICAST] ;
227 } mc ;
228 struct fddi_addr group_addr ;
229 u_long func_addr ; /* functional address */
230 int smt_slots_used ; /* count of table entries for the SMT */
231 int os_slots_used ; /* count of table entries */
232 /* used by the os-specific module */
233} ;
234
235/*
236 * modes for mac_set_rx_mode()
237 */
238#define RX_ENABLE_ALLMULTI 1 /* enable all multicasts */
239#define RX_DISABLE_ALLMULTI 2 /* disable "enable all multicasts" */
240#define RX_ENABLE_PROMISC 3 /* enable promiscuous */
241#define RX_DISABLE_PROMISC 4 /* disable promiscuous */
242#define RX_ENABLE_NSA 5 /* enable reception of NSA frames */
243#define RX_DISABLE_NSA 6 /* disable reception of NSA frames */
244
245
246/*
247 * support for byte reversal in AIX
248 * (descriptors and pointers must be byte reversed in memory
249 * CPU is big endian; M-Channel is little endian)
250 */
251#ifdef AIX
252#define MDR_REV
253#define AIX_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
254 (((x)<< 8L)&0x00ff0000L) + \
255 (((x)>> 8L)&0x0000ff00L) + \
256 (((x)>>24L)&0x000000ffL))
257#else
258#ifndef AIX_REVERSE
259#define AIX_REVERSE(x) (x)
260#endif
261#endif
262
263#ifdef MDR_REV
264#define MDR_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
265 (((x)<< 8L)&0x00ff0000L) + \
266 (((x)>> 8L)&0x0000ff00L) + \
267 (((x)>>24L)&0x000000ffL))
268#else
269#ifndef MDR_REVERSE
270#define MDR_REVERSE(x) (x)
271#endif
272#endif
273
274#endif
diff --git a/drivers/net/skfp/h/hwmtm.h b/drivers/net/skfp/h/hwmtm.h
deleted file mode 100644
index e1a7e5f683dc..000000000000
--- a/drivers/net/skfp/h/hwmtm.h
+++ /dev/null
@@ -1,399 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _HWM_
16#define _HWM_
17
18#include "h/mbuf.h"
19
20/*
21 * MACRO for DMA synchronization:
22 * The descriptor 'desc' is flushed for the device 'flag'.
23 * Devices are the CPU (DDI_DMA_SYNC_FORCPU) and the
24 * adapter (DDI_DMA_SYNC_FORDEV).
25 *
26 * 'desc' Pointer to a Rx or Tx descriptor.
27 * 'flag' Flag for direction (view for CPU or DEVICE) that
28 * should be synchronized.
29 *
30 * Empty macros and defines are specified here. The real macro
31 * is os-specific and should be defined in osdef1st.h.
32 */
33#ifndef DRV_BUF_FLUSH
34#define DRV_BUF_FLUSH(desc,flag)
35#define DDI_DMA_SYNC_FORCPU
36#define DDI_DMA_SYNC_FORDEV
37#endif
38
39 /*
40 * hardware modul dependent receive modes
41 */
42#define RX_ENABLE_PASS_SMT 21
43#define RX_DISABLE_PASS_SMT 22
44#define RX_ENABLE_PASS_NSA 23
45#define RX_DISABLE_PASS_NSA 24
46#define RX_ENABLE_PASS_DB 25
47#define RX_DISABLE_PASS_DB 26
48#define RX_DISABLE_PASS_ALL 27
49#define RX_DISABLE_LLC_PROMISC 28
50#define RX_ENABLE_LLC_PROMISC 29
51
52
53#ifndef DMA_RD
54#define DMA_RD 1 /* memory -> hw */
55#endif
56#ifndef DMA_WR
57#define DMA_WR 2 /* hw -> memory */
58#endif
59#define SMT_BUF 0x80
60
61 /*
62 * bits of the frame status byte
63 */
64#define EN_IRQ_EOF 0x02 /* get IRQ after end of frame transmission */
65#define LOC_TX 0x04 /* send frame to the local SMT */
66#define LAST_FRAG 0x08 /* last TxD of the frame */
67#define FIRST_FRAG 0x10 /* first TxD of the frame */
68#define LAN_TX 0x20 /* send frame to network if set */
69#define RING_DOWN 0x40 /* error: unable to send, ring down */
70#define OUT_OF_TXD 0x80 /* error: not enough TxDs available */
71
72
73#ifndef NULL
74#define NULL 0
75#endif
76
77#ifdef LITTLE_ENDIAN
78#define HWM_REVERSE(x) (x)
79#else
80#define HWM_REVERSE(x) ((((x)<<24L)&0xff000000L) + \
81 (((x)<< 8L)&0x00ff0000L) + \
82 (((x)>> 8L)&0x0000ff00L) + \
83 (((x)>>24L)&0x000000ffL))
84#endif
85
86#define C_INDIC (1L<<25)
87#define A_INDIC (1L<<26)
88#define RD_FS_LOCAL 0x80
89
90 /*
91 * DEBUG FLAGS
92 */
93#define DEBUG_SMTF 1
94#define DEBUG_SMT 2
95#define DEBUG_ECM 3
96#define DEBUG_RMT 4
97#define DEBUG_CFM 5
98#define DEBUG_PCM 6
99#define DEBUG_SBA 7
100#define DEBUG_ESS 8
101
102#define DB_HWM_RX 10
103#define DB_HWM_TX 11
104#define DB_HWM_GEN 12
105
106struct s_mbuf_pool {
107#ifndef MB_OUTSIDE_SMC
108 SMbuf mb[MAX_MBUF] ; /* mbuf pool */
109#endif
110 SMbuf *mb_start ; /* points to the first mb */
111 SMbuf *mb_free ; /* free queue */
112} ;
113
114struct hwm_r {
115 /*
116 * hardware modul specific receive variables
117 */
118 u_int len ; /* length of the whole frame */
119 char *mb_pos ; /* SMbuf receive position */
120} ;
121
122struct hw_modul {
123 /*
124 * All hardware modul specific variables
125 */
126 struct s_mbuf_pool mbuf_pool ;
127 struct hwm_r r ;
128
129 union s_fp_descr volatile *descr_p ; /* points to the desriptor area */
130
131 u_short pass_SMT ; /* pass SMT frames */
132 u_short pass_NSA ; /* pass all NSA frames */
133 u_short pass_DB ; /* pass Direct Beacon Frames */
134 u_short pass_llc_promisc ; /* pass all llc frames (default ON) */
135
136 SMbuf *llc_rx_pipe ; /* points to the first queued llc fr */
137 SMbuf *llc_rx_tail ; /* points to the last queued llc fr */
138 int queued_rx_frames ; /* number of queued frames */
139
140 SMbuf *txd_tx_pipe ; /* points to first mb in the txd ring */
141 SMbuf *txd_tx_tail ; /* points to last mb in the txd ring */
142 int queued_txd_mb ; /* number of SMT MBufs in txd ring */
143
144 int rx_break ; /* rev. was breaked because ind. off */
145 int leave_isr ; /* leave fddi_isr immedeately if set */
146 int isr_flag ; /* set, when HWM is entered from isr */
147 /*
148 * variables for the current transmit frame
149 */
150 struct s_smt_tx_queue *tx_p ; /* pointer to the transmit queue */
151 u_long tx_descr ; /* tx descriptor for FORMAC+ */
152 int tx_len ; /* tx frame length */
153 SMbuf *tx_mb ; /* SMT tx MBuf pointer */
154 char *tx_data ; /* data pointer to the SMT tx Mbuf */
155
156 int detec_count ; /* counter for out of RxD condition */
157 u_long rx_len_error ; /* rx len FORMAC != sum of fragments */
158} ;
159
160
161/*
162 * DEBUG structs and macros
163 */
164
165#ifdef DEBUG
166struct os_debug {
167 int hwm_rx ;
168 int hwm_tx ;
169 int hwm_gen ;
170} ;
171#endif
172
173#ifdef DEBUG
174#ifdef DEBUG_BRD
175#define DB_P smc->debug
176#else
177#define DB_P debug
178#endif
179
180#define DB_RX(a,b,c,lev) if (DB_P.d_os.hwm_rx >= (lev)) printf(a,b,c)
181#define DB_TX(a,b,c,lev) if (DB_P.d_os.hwm_tx >= (lev)) printf(a,b,c)
182#define DB_GEN(a,b,c,lev) if (DB_P.d_os.hwm_gen >= (lev)) printf(a,b,c)
183#else /* DEBUG */
184#define DB_RX(a,b,c,lev)
185#define DB_TX(a,b,c,lev)
186#define DB_GEN(a,b,c,lev)
187#endif /* DEBUG */
188
189#ifndef SK_BREAK
190#define SK_BREAK()
191#endif
192
193
194/*
195 * HWM Macros
196 */
197
198/*
199 * BEGIN_MANUAL_ENTRY(HWM_GET_TX_PHYS)
200 * u_long HWM_GET_TX_PHYS(txd)
201 *
202 * function MACRO (hardware module, hwmtm.h)
203 * This macro may be invoked by the OS-specific module to read
204 * the physical address of the specified TxD.
205 *
206 * para txd pointer to the TxD
207 *
208 * END_MANUAL_ENTRY
209 */
210#define HWM_GET_TX_PHYS(txd) (u_long)AIX_REVERSE((txd)->txd_tbadr)
211
212/*
213 * BEGIN_MANUAL_ENTRY(HWM_GET_TX_LEN)
214 * int HWM_GET_TX_LEN(txd)
215 *
216 * function MACRO (hardware module, hwmtm.h)
217 * This macro may be invoked by the OS-specific module to read
218 * the fragment length of the specified TxD
219 *
220 * para rxd pointer to the TxD
221 *
222 * return the length of the fragment in bytes
223 *
224 * END_MANUAL_ENTRY
225 */
226#define HWM_GET_TX_LEN(txd) ((int)AIX_REVERSE((txd)->txd_tbctrl)& RD_LENGTH)
227
228/*
229 * BEGIN_MANUAL_ENTRY(HWM_GET_TX_USED)
230 * txd *HWM_GET_TX_USED(smc,queue)
231 *
232 * function MACRO (hardware module, hwmtm.h)
233 * This macro may be invoked by the OS-specific module to get the
234 * number of used TxDs for the queue, specified by the index.
235 *
236 * para queue the number of the send queue: Can be specified by
237 * QUEUE_A0, QUEUE_S or (frame_status & QUEUE_A0)
238 *
239 * return number of used TxDs for this send queue
240 *
241 * END_MANUAL_ENTRY
242 */
243#define HWM_GET_TX_USED(smc,queue) (int) (smc)->hw.fp.tx_q[queue].tx_used
244
245/*
246 * BEGIN_MANUAL_ENTRY(HWM_GET_CURR_TXD)
247 * txd *HWM_GET_CURR_TXD(smc,queue)
248 *
249 * function MACRO (hardware module, hwmtm.h)
250 * This macro may be invoked by the OS-specific module to get the
251 * pointer to the TxD which points to the current queue put
252 * position.
253 *
254 * para queue the number of the send queue: Can be specified by
255 * QUEUE_A0, QUEUE_S or (frame_status & QUEUE_A0)
256 *
257 * return pointer to the current TxD
258 *
259 * END_MANUAL_ENTRY
260 */
261#define HWM_GET_CURR_TXD(smc,queue) (struct s_smt_fp_txd volatile *)\
262 (smc)->hw.fp.tx_q[queue].tx_curr_put
263
264/*
265 * BEGIN_MANUAL_ENTRY(HWM_GET_RX_FRAG_LEN)
266 * int HWM_GET_RX_FRAG_LEN(rxd)
267 *
268 * function MACRO (hardware module, hwmtm.h)
269 * This macro may be invoked by the OS-specific module to read
270 * the fragment length of the specified RxD
271 *
272 * para rxd pointer to the RxD
273 *
274 * return the length of the fragment in bytes
275 *
276 * END_MANUAL_ENTRY
277 */
278#define HWM_GET_RX_FRAG_LEN(rxd) ((int)AIX_REVERSE((rxd)->rxd_rbctrl)& \
279 RD_LENGTH)
280
281/*
282 * BEGIN_MANUAL_ENTRY(HWM_GET_RX_PHYS)
283 * u_long HWM_GET_RX_PHYS(rxd)
284 *
285 * function MACRO (hardware module, hwmtm.h)
286 * This macro may be invoked by the OS-specific module to read
287 * the physical address of the specified RxD.
288 *
289 * para rxd pointer to the RxD
290 *
291 * return the RxD's physical pointer to the data fragment
292 *
293 * END_MANUAL_ENTRY
294 */
295#define HWM_GET_RX_PHYS(rxd) (u_long)AIX_REVERSE((rxd)->rxd_rbadr)
296
297/*
298 * BEGIN_MANUAL_ENTRY(HWM_GET_RX_USED)
299 * int HWM_GET_RX_USED(smc)
300 *
301 * function MACRO (hardware module, hwmtm.h)
302 * This macro may be invoked by the OS-specific module to get
303 * the count of used RXDs in receive queue 1.
304 *
305 * return the used RXD count of receive queue 1
306 *
307 * NOTE: Remember, because of an ASIC bug at least one RXD should be unused
308 * in the descriptor ring !
309 *
310 * END_MANUAL_ENTRY
311 */
312#define HWM_GET_RX_USED(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_used)
313
314/*
315 * BEGIN_MANUAL_ENTRY(HWM_GET_RX_FREE)
316 * int HWM_GET_RX_FREE(smc)
317 *
318 * function MACRO (hardware module, hwmtm.h)
319 * This macro may be invoked by the OS-specific module to get
320 * the rxd_free count of receive queue 1.
321 *
322 * return the rxd_free count of receive queue 1
323 *
324 * END_MANUAL_ENTRY
325 */
326#define HWM_GET_RX_FREE(smc) ((int)(smc)->hw.fp.rx_q[QUEUE_R1].rx_free-1)
327
328/*
329 * BEGIN_MANUAL_ENTRY(HWM_GET_CURR_RXD)
330 * rxd *HWM_GET_CURR_RXD(smc)
331 *
332 * function MACRO (hardware module, hwmtm.h)
333 * This macro may be invoked by the OS-specific module to get the
334 * pointer to the RxD which points to the current queue put
335 * position.
336 *
337 * return pointer to the current RxD
338 *
339 * END_MANUAL_ENTRY
340 */
341#define HWM_GET_CURR_RXD(smc) (struct s_smt_fp_rxd volatile *)\
342 (smc)->hw.fp.rx_q[QUEUE_R1].rx_curr_put
343
344/*
345 * BEGIN_MANUAL_ENTRY(HWM_RX_CHECK)
346 * void HWM_RX_CHECK(smc,low_water)
347 *
348 * function MACRO (hardware module, hwmtm.h)
349 * This macro is invoked by the OS-specific before it left the
350 * function mac_drv_rx_complete. This macro calls mac_drv_fill_rxd
351 * if the number of used RxDs is equal or lower than the
352 * the given low water mark.
353 *
354 * para low_water low water mark of used RxD's
355 *
356 * END_MANUAL_ENTRY
357 */
358#ifndef HWM_NO_FLOW_CTL
359#define HWM_RX_CHECK(smc,low_water) {\
360 if ((low_water) >= (smc)->hw.fp.rx_q[QUEUE_R1].rx_used) {\
361 mac_drv_fill_rxd(smc) ;\
362 }\
363}
364#else
365#define HWM_RX_CHECK(smc,low_water) mac_drv_fill_rxd(smc)
366#endif
367
368#ifndef HWM_EBASE
369#define HWM_EBASE 500
370#endif
371
372#define HWM_E0001 HWM_EBASE + 1
373#define HWM_E0001_MSG "HWM: Wrong size of s_rxd_os struct"
374#define HWM_E0002 HWM_EBASE + 2
375#define HWM_E0002_MSG "HWM: Wrong size of s_txd_os struct"
376#define HWM_E0003 HWM_EBASE + 3
377#define HWM_E0003_MSG "HWM: smt_free_mbuf() called with NULL pointer"
378#define HWM_E0004 HWM_EBASE + 4
379#define HWM_E0004_MSG "HWM: Parity error rx queue 1"
380#define HWM_E0005 HWM_EBASE + 5
381#define HWM_E0005_MSG "HWM: Encoding error rx queue 1"
382#define HWM_E0006 HWM_EBASE + 6
383#define HWM_E0006_MSG "HWM: Encoding error async tx queue"
384#define HWM_E0007 HWM_EBASE + 7
385#define HWM_E0007_MSG "HWM: Encoding error sync tx queue"
386#define HWM_E0008 HWM_EBASE + 8
387#define HWM_E0008_MSG ""
388#define HWM_E0009 HWM_EBASE + 9
389#define HWM_E0009_MSG "HWM: Out of RxD condition detected"
390#define HWM_E0010 HWM_EBASE + 10
391#define HWM_E0010_MSG "HWM: A protocol layer has tried to send a frame with an invalid frame control"
392#define HWM_E0011 HWM_EBASE + 11
393#define HWM_E0011_MSG "HWM: mac_drv_clear_tx_queue was called although the hardware wasn't stopped"
394#define HWM_E0012 HWM_EBASE + 12
395#define HWM_E0012_MSG "HWM: mac_drv_clear_rx_queue was called although the hardware wasn't stopped"
396#define HWM_E0013 HWM_EBASE + 13
397#define HWM_E0013_MSG "HWM: mac_drv_repair_descr was called although the hardware wasn't stopped"
398
399#endif
diff --git a/drivers/net/skfp/h/mbuf.h b/drivers/net/skfp/h/mbuf.h
deleted file mode 100644
index f2aadcda9e7f..000000000000
--- a/drivers/net/skfp/h/mbuf.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _MBUF_
16#define _MBUF_
17
18#define M_SIZE 4504
19
20#ifndef MAX_MBUF
21#define MAX_MBUF 4
22#endif
23
24#ifndef NO_STD_MBUF
25#define sm_next m_next
26#define sm_off m_off
27#define sm_len m_len
28#define sm_data m_data
29#define SMbuf Mbuf
30#define mtod smtod
31#define mtodoff smtodoff
32#endif
33
34struct s_mbuf {
35 struct s_mbuf *sm_next ; /* low level linked list */
36 short sm_off ; /* offset in m_data */
37 u_int sm_len ; /* len of data */
38#ifdef PCI
39 int sm_use_count ;
40#endif
41 char sm_data[M_SIZE] ;
42} ;
43
44typedef struct s_mbuf SMbuf ;
45
46/* mbuf head, to typed data */
47#define smtod(x,t) ((t)((x)->sm_data + (x)->sm_off))
48#define smtodoff(x,t,o) ((t)((x)->sm_data + (o)))
49
50#endif /* _MBUF_ */
diff --git a/drivers/net/skfp/h/osdef1st.h b/drivers/net/skfp/h/osdef1st.h
deleted file mode 100644
index 763ca18cbea8..000000000000
--- a/drivers/net/skfp/h/osdef1st.h
+++ /dev/null
@@ -1,125 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 * Operating system-dependent definitions that have to be defined
17 * before any other header files are included.
18 */
19
20// HWM (HardWare Module) Definitions
21// -----------------------
22
23#include <asm/byteorder.h>
24
25#ifdef __LITTLE_ENDIAN
26#define LITTLE_ENDIAN
27#else
28#define BIG_ENDIAN
29#endif
30
31// this is set in the makefile
32// #define PCI /* only PCI adapters supported by this driver */
33// #define MEM_MAPPED_IO /* use memory mapped I/O */
34
35
36#define USE_CAN_ADDR /* DA and SA in MAC header are canonical. */
37
38#define MB_OUTSIDE_SMC /* SMT Mbufs outside of smc struct. */
39
40// -----------------------
41
42
43// SMT Definitions
44// -----------------------
45#define SYNC /* allow synchronous frames */
46
47// #define SBA /* Synchronous Bandwidth Allocator support */
48 /* not available as free source */
49
50#define ESS /* SBA End Station Support */
51
52#define SMT_PANIC(smc, nr, msg) printk(KERN_INFO "SMT PANIC: code: %d, msg: %s\n",nr,msg)
53
54
55#ifdef DEBUG
56#define printf(s,args...) printk(KERN_INFO s, ## args)
57#endif
58
59// #define HW_PTR u_long
60// -----------------------
61
62
63
64// HWM and OS-specific buffer definitions
65// -----------------------
66
67// default number of receive buffers.
68#define NUM_RECEIVE_BUFFERS 10
69
70// default number of transmit buffers.
71#define NUM_TRANSMIT_BUFFERS 10
72
73// Number of SMT buffers (Mbufs).
74#define NUM_SMT_BUF 4
75
76// Number of TXDs for asynchronous transmit queue.
77#define HWM_ASYNC_TXD_COUNT (NUM_TRANSMIT_BUFFERS + NUM_SMT_BUF)
78
79// Number of TXDs for synchronous transmit queue.
80#define HWM_SYNC_TXD_COUNT HWM_ASYNC_TXD_COUNT
81
82
83// Number of RXDs for receive queue #1.
84// Note: Workaround for ASIC Errata #7: One extra RXD is required.
85#if (NUM_RECEIVE_BUFFERS > 100)
86#define SMT_R1_RXD_COUNT (1 + 100)
87#else
88#define SMT_R1_RXD_COUNT (1 + NUM_RECEIVE_BUFFERS)
89#endif
90
91// Number of RXDs for receive queue #2.
92#define SMT_R2_RXD_COUNT 0 // Not used.
93// -----------------------
94
95
96
97/*
98 * OS-specific part of the transmit/receive descriptor structure (TXD/RXD).
99 *
100 * Note: The size of these structures must follow this rule:
101 *
102 * sizeof(struct) + 2*sizeof(void*) == n * 16, n >= 1
103 *
104 * We use the dma_addr fields under Linux to keep track of the
105 * DMA address of the packet data, for later pci_unmap_single. -DaveM
106 */
107
108struct s_txd_os { // os-specific part of transmit descriptor
109 struct sk_buff *skb;
110 dma_addr_t dma_addr;
111} ;
112
113struct s_rxd_os { // os-specific part of receive descriptor
114 struct sk_buff *skb;
115 dma_addr_t dma_addr;
116} ;
117
118
119/*
120 * So we do not need to make too many modifications to the generic driver
121 * parts, we take advantage of the AIX byte swapping macro interface.
122 */
123
124#define AIX_REVERSE(x) ((u32)le32_to_cpu((u32)(x)))
125#define MDR_REVERSE(x) ((u32)le32_to_cpu((u32)(x)))
diff --git a/drivers/net/skfp/h/sba.h b/drivers/net/skfp/h/sba.h
deleted file mode 100644
index 638cf0283bc4..000000000000
--- a/drivers/net/skfp/h/sba.h
+++ /dev/null
@@ -1,142 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 * Synchronous Bandwidth Allocation (SBA) structs
17 */
18
19#ifndef _SBA_
20#define _SBA_
21
22#include "h/mbuf.h"
23#include "h/sba_def.h"
24
25#ifdef SBA
26
27/* Timer Cell Template */
28struct timer_cell {
29 struct timer_cell *next_ptr ;
30 struct timer_cell *prev_ptr ;
31 u_long start_time ;
32 struct s_sba_node_vars *node_var ;
33} ;
34
35/*
36 * Node variables
37 */
38struct s_sba_node_vars {
39 u_char change_resp_flag ;
40 u_char report_resp_flag ;
41 u_char change_req_flag ;
42 u_char report_req_flag ;
43 long change_amount ;
44 long node_overhead ;
45 long node_payload ;
46 u_long node_status ;
47 u_char deallocate_status ;
48 u_char timer_state ;
49 u_short report_cnt ;
50 long lastrep_req_tranid ;
51 struct fddi_addr mac_address ;
52 struct s_sba_sessions *node_sessions ;
53 struct timer_cell timer ;
54} ;
55
56/*
57 * Session variables
58 */
59struct s_sba_sessions {
60 u_long deallocate_status ;
61 long session_overhead ;
62 u_long min_segment_size ;
63 long session_payload ;
64 u_long session_status ;
65 u_long sba_category ;
66 long lastchg_req_tranid ;
67 u_short session_id ;
68 u_char class ;
69 u_char fddi2 ;
70 u_long max_t_neg ;
71 struct s_sba_sessions *next_session ;
72} ;
73
74struct s_sba {
75
76 struct s_sba_node_vars node[MAX_NODES] ;
77 struct s_sba_sessions session[MAX_SESSIONS] ;
78
79 struct s_sba_sessions *free_session ; /* points to the first */
80 /* free session */
81
82 struct timer_cell *tail_timer ; /* points to the last timer cell */
83
84 /*
85 * variables for allocation actions
86 */
87 long total_payload ; /* Total Payload */
88 long total_overhead ; /* Total Overhead */
89 long sba_allocatable ; /* allocatable sync bandwidth */
90
91 /*
92 * RAF message receive parameters
93 */
94 long msg_path_index ; /* Path Type */
95 long msg_sba_pl_req ; /* Payload Request */
96 long msg_sba_ov_req ; /* Overhead Request */
97 long msg_mib_pl ; /* Current Payload for this Path */
98 long msg_mib_ov ; /* Current Overhead for this Path*/
99 long msg_category ; /* Category of the Allocation */
100 u_long msg_max_t_neg ; /* longest T_Neg acceptable */
101 u_long msg_min_seg_siz ; /* minimum segement size */
102 struct smt_header *sm ; /* points to the rec message */
103 struct fddi_addr *msg_alloc_addr ; /* Allocation Address */
104
105 /*
106 * SBA variables
107 */
108 u_long sba_t_neg ; /* holds the last T_NEG */
109 long sba_max_alloc ; /* the parsed value of SBAAvailable */
110
111 /*
112 * SBA state machine variables
113 */
114 short sba_next_state ; /* the next state of the SBA */
115 char sba_command ; /* holds the execuded SBA cmd */
116 u_char sba_available ; /* parsed value after possible check */
117} ;
118
119#endif /* SBA */
120
121 /*
122 * variables for the End Station Support
123 */
124struct s_ess {
125
126 /*
127 * flags and counters
128 */
129 u_char sync_bw_available ; /* is set if sync bw is allocated */
130 u_char local_sba_active ; /* set when a local sba is available */
131 char raf_act_timer_poll ; /* activate the timer to send allc req */
132 char timer_count ; /* counts every timer function call */
133
134 SMbuf *sba_reply_pend ; /* local reply for the sba is pending */
135
136 /*
137 * variables for the ess bandwidth control
138 */
139 long sync_bw ; /* holds the allocaed sync bw */
140 u_long alloc_trans_id ; /* trans id of the last alloc req */
141} ;
142#endif
diff --git a/drivers/net/skfp/h/sba_def.h b/drivers/net/skfp/h/sba_def.h
deleted file mode 100644
index 0459a095d0cd..000000000000
--- a/drivers/net/skfp/h/sba_def.h
+++ /dev/null
@@ -1,76 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#define PHYS 0 /* physical addr */
16#define PERM_ADDR 0x80 /* permanet address */
17#define SB_STATIC 0x00000001
18#define MAX_PAYLOAD 1562
19#define PRIMARY_RING 0x00000001
20#ifndef NULL
21#define NULL 0x00
22#endif
23
24/*********************** SB_Input Variable Values ***********************/
25/* may be needed when ever the SBA state machine is called */
26
27#define UNKNOWN_SYNC_SOURCE 0x0001
28#define REQ_ALLOCATION 0x0002
29#define REPORT_RESP 0x0003
30#define CHANGE_RESP 0x0004
31#define TNEG 0x0005
32#define NIF 0x0006
33#define SB_STOP 0x0007
34#define SB_START 0x0008
35#define REPORT_TIMER 0x0009
36#define CHANGE_REQUIRED 0x000A
37
38#define DEFAULT_OV 50
39
40#ifdef SBA
41/**************************** SBA STATES *****************************/
42
43#define SBA_STANDBY 0x00000000
44#define SBA_ACTIVE 0x00000001
45#define SBA_RECOVERY 0x00000002
46#define SBA_REPORT 0x00000003
47#define SBA_CHANGE 0x00000004
48
49/**************************** OTHERS *********************************/
50
51#define FIFTY_PERCENT 50 /* bytes per second */
52#define MAX_SESSIONS 150
53#define TWO_MINUTES 13079 /* 9.175 ms/tick */
54#define FIFTY_BYTES 50
55#define SBA_DENIED 0x0000000D
56#define I_NEED_ONE 0x00000000
57#define MAX_NODES 50
58/*#define T_REPORT 0x59682F00L*/ /* 120s/80ns in Hex */
59#define TWO_MIN 120 /* seconds */
60#define SBA_ST_UNKNOWN 0x00000002
61#define SBA_ST_ACTIVE 0x00000001
62#define S_CLEAR 0x00000000L
63#define ZERO 0x00000000
64#define FULL 0x00000000 /* old: 0xFFFFFFFFF */
65#define S_SET 0x00000001L
66#define LOW_PRIO 0x02 /* ??????? */
67#define OK 0x01 /* ??????? */
68#define NOT_OK 0x00 /* ??????? */
69
70/****************************************/
71/* deallocate_status[ni][si] values */
72/****************************************/
73#define TX_CHANGE 0X00000001L
74#define PENDING 0x00000002L
75#define NONE 0X00000000L
76#endif
diff --git a/drivers/net/skfp/h/skfbi.h b/drivers/net/skfp/h/skfbi.h
deleted file mode 100644
index c1ba26c06d73..000000000000
--- a/drivers/net/skfp/h/skfbi.h
+++ /dev/null
@@ -1,1133 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _SKFBI_H_
16#define _SKFBI_H_
17
18/*
19 * FDDI-Fx (x := {I(SA), P(CI)})
20 * address calculation & function defines
21 */
22
23/*--------------------------------------------------------------------------*/
24#ifdef PCI
25
26/*
27 * (DV) = only defined for Da Vinci
28 * (ML) = only defined for Monalisa
29 */
30
31/*
32 * Configuration Space header
33 */
34#define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
35#define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
36#define PCI_COMMAND 0x04 /* 16 bit Command */
37#define PCI_STATUS 0x06 /* 16 bit Status */
38#define PCI_REV_ID 0x08 /* 8 bit Revision ID */
39#define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
40#define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
41#define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
42#define PCI_HEADER_T 0x0e /* 8 bit Header Type */
43#define PCI_BIST 0x0f /* 8 bit Built-in selftest */
44#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
45#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
46/* Byte 18..2b: Reserved */
47#define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
48#define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
49#define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
50/* Byte 34..33: Reserved */
51#define PCI_CAP_PTR 0x34 /* 8 bit (ML) Capabilities Ptr */
52/* Byte 35..3b: Reserved */
53#define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
54#define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
55#define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
56#define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
57/* Device Dependent Region */
58#define PCI_OUR_REG 0x40 /* 32 bit (DV) Our Register */
59#define PCI_OUR_REG_1 0x40 /* 32 bit (ML) Our Register 1 */
60#define PCI_OUR_REG_2 0x44 /* 32 bit (ML) Our Register 2 */
61/* Power Management Region */
62#define PCI_PM_CAP_ID 0x48 /* 8 bit (ML) Power Management Cap. ID */
63#define PCI_PM_NITEM 0x49 /* 8 bit (ML) Next Item Ptr */
64#define PCI_PM_CAP_REG 0x4a /* 16 bit (ML) Power Management Capabilities */
65#define PCI_PM_CTL_STS 0x4c /* 16 bit (ML) Power Manag. Control/Status */
66/* Byte 0x4e: Reserved */
67#define PCI_PM_DAT_REG 0x4f /* 8 bit (ML) Power Manag. Data Register */
68/* VPD Region */
69#define PCI_VPD_CAP_ID 0x50 /* 8 bit (ML) VPD Cap. ID */
70#define PCI_VPD_NITEM 0x51 /* 8 bit (ML) Next Item Ptr */
71#define PCI_VPD_ADR_REG 0x52 /* 16 bit (ML) VPD Address Register */
72#define PCI_VPD_DAT_REG 0x54 /* 32 bit (ML) VPD Data Register */
73/* Byte 58..ff: Reserved */
74
75/*
76 * I2C Address (PCI Config)
77 *
78 * Note: The temperature and voltage sensors are relocated on a different
79 * I2C bus.
80 */
81#define I2C_ADDR_VPD 0xA0 /* I2C address for the VPD EEPROM */
82
83/*
84 * Define Bits and Values of the registers
85 */
86/* PCI_VENDOR_ID 16 bit Vendor ID */
87/* PCI_DEVICE_ID 16 bit Device ID */
88/* Values for Vendor ID and Device ID shall be patched into the code */
89/* PCI_COMMAND 16 bit Command */
90#define PCI_FBTEN 0x0200 /* Bit 9: Fast Back-To-Back enable */
91#define PCI_SERREN 0x0100 /* Bit 8: SERR enable */
92#define PCI_ADSTEP 0x0080 /* Bit 7: Address Stepping */
93#define PCI_PERREN 0x0040 /* Bit 6: Parity Report Response enable */
94#define PCI_VGA_SNOOP 0x0020 /* Bit 5: VGA palette snoop */
95#define PCI_MWIEN 0x0010 /* Bit 4: Memory write an inv cycl ena */
96#define PCI_SCYCEN 0x0008 /* Bit 3: Special Cycle enable */
97#define PCI_BMEN 0x0004 /* Bit 2: Bus Master enable */
98#define PCI_MEMEN 0x0002 /* Bit 1: Memory Space Access enable */
99#define PCI_IOEN 0x0001 /* Bit 0: IO Space Access enable */
100
101/* PCI_STATUS 16 bit Status */
102#define PCI_PERR 0x8000 /* Bit 15: Parity Error */
103#define PCI_SERR 0x4000 /* Bit 14: Signaled SERR */
104#define PCI_RMABORT 0x2000 /* Bit 13: Received Master Abort */
105#define PCI_RTABORT 0x1000 /* Bit 12: Received Target Abort */
106#define PCI_STABORT 0x0800 /* Bit 11: Sent Target Abort */
107#define PCI_DEVSEL 0x0600 /* Bit 10..9: DEVSEL Timing */
108#define PCI_DEV_FAST (0<<9) /* fast */
109#define PCI_DEV_MEDIUM (1<<9) /* medium */
110#define PCI_DEV_SLOW (2<<9) /* slow */
111#define PCI_DATAPERR 0x0100 /* Bit 8: DATA Parity error detected */
112#define PCI_FB2BCAP 0x0080 /* Bit 7: Fast Back-to-Back Capability */
113#define PCI_UDF 0x0040 /* Bit 6: User Defined Features */
114#define PCI_66MHZCAP 0x0020 /* Bit 5: 66 MHz PCI bus clock capable */
115#define PCI_NEWCAP 0x0010 /* Bit 4: New cap. list implemented */
116
117#define PCI_ERRBITS (PCI_PERR|PCI_SERR|PCI_RMABORT|PCI_STABORT|PCI_DATAPERR)
118
119/* PCI_REV_ID 8 bit Revision ID */
120/* PCI_CLASS_CODE 24 bit Class Code */
121/* Byte 2: Base Class (02) */
122/* Byte 1: SubClass (02) */
123/* Byte 0: Programming Interface (00) */
124
125/* PCI_CACHE_LSZ 8 bit Cache Line Size */
126/* Possible values: 0,2,4,8,16 */
127
128/* PCI_LAT_TIM 8 bit Latency Timer */
129
130/* PCI_HEADER_T 8 bit Header Type */
131#define PCI_HD_MF_DEV 0x80 /* Bit 7: 0= single, 1= multi-func dev */
132#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
133
134/* PCI_BIST 8 bit Built-in selftest */
135#define PCI_BIST_CAP 0x80 /* Bit 7: BIST Capable */
136#define PCI_BIST_ST 0x40 /* Bit 6: Start BIST */
137#define PCI_BIST_RET 0x0f /* Bit 3..0: Completion Code */
138
139/* PCI_BASE_1ST 32 bit 1st Base address */
140#define PCI_MEMSIZE 0x800L /* use 2 kB Memory Base */
141#define PCI_MEMBASE_BITS 0xfffff800L /* Bit 31..11: Memory Base Address */
142#define PCI_MEMSIZE_BIIS 0x000007f0L /* Bit 10..4: Memory Size Req. */
143#define PCI_PREFEN 0x00000008L /* Bit 3: Prefetchable */
144#define PCI_MEM_TYP 0x00000006L /* Bit 2..1: Memory Type */
145#define PCI_MEM32BIT (0<<1) /* Base addr anywhere in 32 Bit range */
146#define PCI_MEM1M (1<<1) /* Base addr below 1 MegaByte */
147#define PCI_MEM64BIT (2<<1) /* Base addr anywhere in 64 Bit range */
148#define PCI_MEMSPACE 0x00000001L /* Bit 0: Memory Space Indic. */
149
150/* PCI_BASE_2ND 32 bit 2nd Base address */
151#define PCI_IOBASE 0xffffff00L /* Bit 31..8: I/O Base address */
152#define PCI_IOSIZE 0x000000fcL /* Bit 7..2: I/O Size Requirements */
153#define PCI_IOSPACE 0x00000001L /* Bit 0: I/O Space Indicator */
154
155/* PCI_SUB_VID 16 bit Subsystem Vendor ID */
156/* PCI_SUB_ID 16 bit Subsystem ID */
157
158/* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
159#define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st) */
160#define PCI_ROMBASZ 0x0001c000L /* Bit 16..14: Treat as BASE or SIZE */
161#define PCI_ROMSIZE 0x00003800L /* Bit 13..11: ROM Size Requirements */
162#define PCI_ROMEN 0x00000001L /* Bit 0: Address Decode enable */
163
164/* PCI_CAP_PTR 8 bit New Capabilities Pointers */
165/* PCI_IRQ_LINE 8 bit Interrupt Line */
166/* PCI_IRQ_PIN 8 bit Interrupt Pin */
167/* PCI_MIN_GNT 8 bit Min_Gnt */
168/* PCI_MAX_LAT 8 bit Max_Lat */
169/* Device Dependent Region */
170/* PCI_OUR_REG (DV) 32 bit Our Register */
171/* PCI_OUR_REG_1 (ML) 32 bit Our Register 1 */
172 /* Bit 31..29: reserved */
173#define PCI_PATCH_DIR (3L<<27) /*(DV) Bit 28..27: Ext Patchs direction */
174#define PCI_PATCH_DIR_0 (1L<<27) /*(DV) Type of the pins EXT_PATCHS<1..0> */
175#define PCI_PATCH_DIR_1 (1L<<28) /* 0 = input */
176 /* 1 = output */
177#define PCI_EXT_PATCHS (3L<<25) /*(DV) Bit 26..25: Extended Patches */
178#define PCI_EXT_PATCH_0 (1L<<25) /*(DV) */
179#define PCI_EXT_PATCH_1 (1L<<26) /* CLK for MicroWire (ML) */
180#define PCI_VIO (1L<<25) /*(ML) */
181#define PCI_EN_BOOT (1L<<24) /* Bit 24: Enable BOOT via ROM */
182 /* 1 = Don't boot with ROM */
183 /* 0 = Boot with ROM */
184#define PCI_EN_IO (1L<<23) /* Bit 23: Mapping to IO space */
185#define PCI_EN_FPROM (1L<<22) /* Bit 22: FLASH mapped to mem? */
186 /* 1 = Map Flash to Memory */
187 /* 0 = Disable all addr. decoding */
188#define PCI_PAGESIZE (3L<<20) /* Bit 21..20: FLASH Page Size */
189#define PCI_PAGE_16 (0L<<20) /* 16 k pages */
190#define PCI_PAGE_32K (1L<<20) /* 32 k pages */
191#define PCI_PAGE_64K (2L<<20) /* 64 k pages */
192#define PCI_PAGE_128K (3L<<20) /* 128 k pages */
193 /* Bit 19: reserved (ML) and (DV) */
194#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
195 /* Bit 15: reserved */
196#define PCI_FORCE_BE (1L<<14) /* Bit 14: Assert all BEs on MR */
197#define PCI_DIS_MRL (1L<<13) /* Bit 13: Disable Mem R Line */
198#define PCI_DIS_MRM (1L<<12) /* Bit 12: Disable Mem R multip */
199#define PCI_DIS_MWI (1L<<11) /* Bit 11: Disable Mem W & inv */
200#define PCI_DISC_CLS (1L<<10) /* Bit 10: Disc: cacheLsz bound */
201#define PCI_BURST_DIS (1L<<9) /* Bit 9: Burst Disable */
202#define PCI_BYTE_SWAP (1L<<8) /*(DV) Bit 8: Byte Swap in DATA */
203#define PCI_SKEW_DAS (0xfL<<4) /* Bit 7..4: Skew Ctrl, DAS Ext */
204#define PCI_SKEW_BASE (0xfL<<0) /* Bit 3..0: Skew Ctrl, Base */
205
206/* PCI_OUR_REG_2 (ML) 32 bit Our Register 2 (Monalisa only) */
207#define PCI_VPD_WR_TH (0xffL<<24) /* Bit 24..31 VPD Write Threshold */
208#define PCI_DEV_SEL (0x7fL<<17) /* Bit 17..23 EEPROM Device Select */
209#define PCI_VPD_ROM_SZ (7L<<14) /* Bit 14..16 VPD ROM Size */
210 /* Bit 12..13 reserved */
211#define PCI_PATCH_DIR2 (0xfL<<8) /* Bit 8..11 Ext Patchs dir 2..5 */
212#define PCI_PATCH_DIR_2 (1L<<8) /* Bit 8 CS for MicroWire */
213#define PCI_PATCH_DIR_3 (1L<<9)
214#define PCI_PATCH_DIR_4 (1L<<10)
215#define PCI_PATCH_DIR_5 (1L<<11)
216#define PCI_EXT_PATCHS2 (0xfL<<4) /* Bit 4..7 Extended Patches */
217#define PCI_EXT_PATCH_2 (1L<<4) /* Bit 4 CS for MicroWire */
218#define PCI_EXT_PATCH_3 (1L<<5)
219#define PCI_EXT_PATCH_4 (1L<<6)
220#define PCI_EXT_PATCH_5 (1L<<7)
221#define PCI_EN_DUMMY_RD (1L<<3) /* Bit 3 Enable Dummy Read */
222#define PCI_REV_DESC (1L<<2) /* Bit 2 Reverse Desc. Bytes */
223#define PCI_USEADDR64 (1L<<1) /* Bit 1 Use 64 Bit Addresse */
224#define PCI_USEDATA64 (1L<<0) /* Bit 0 Use 64 Bit Data bus ext*/
225
226/* Power Management Region */
227/* PCI_PM_CAP_ID 8 bit (ML) Power Management Cap. ID */
228/* PCI_PM_NITEM 8 bit (ML) Next Item Ptr */
229/* PCI_PM_CAP_REG 16 bit (ML) Power Management Capabilities*/
230#define PCI_PME_SUP (0x1f<<11) /* Bit 11..15 PM Manag. Event Support*/
231#define PCI_PM_D2_SUB (1<<10) /* Bit 10 D2 Support Bit */
232#define PCI_PM_D1_SUB (1<<9) /* Bit 9 D1 Support Bit */
233 /* Bit 6..8 reserved */
234#define PCI_PM_DSI (1<<5) /* Bit 5 Device Specific Init.*/
235#define PCI_PM_APS (1<<4) /* Bit 4 Auxialiary Power Src */
236#define PCI_PME_CLOCK (1<<3) /* Bit 3 PM Event Clock */
237#define PCI_PM_VER (7<<0) /* Bit 0..2 PM PCI Spec. version */
238
239/* PCI_PM_CTL_STS 16 bit (ML) Power Manag. Control/Status */
240#define PCI_PME_STATUS (1<<15) /* Bit 15 PFA doesn't sup. PME#*/
241#define PCI_PM_DAT_SCL (3<<13) /* Bit 13..14 dat reg Scaling factor */
242#define PCI_PM_DAT_SEL (0xf<<9) /* Bit 9..12 PM data selector field */
243 /* Bit 7.. 2 reserved */
244#define PCI_PM_STATE (3<<0) /* Bit 0.. 1 Power Management State */
245#define PCI_PM_STATE_D0 (0<<0) /* D0: Operational (default) */
246#define PCI_PM_STATE_D1 (1<<0) /* D1: not supported */
247#define PCI_PM_STATE_D2 (2<<0) /* D2: not supported */
248#define PCI_PM_STATE_D3 (3<<0) /* D3: HOT, Power Down and Reset */
249
250/* PCI_PM_DAT_REG 8 bit (ML) Power Manag. Data Register */
251/* VPD Region */
252/* PCI_VPD_CAP_ID 8 bit (ML) VPD Cap. ID */
253/* PCI_VPD_NITEM 8 bit (ML) Next Item Ptr */
254/* PCI_VPD_ADR_REG 16 bit (ML) VPD Address Register */
255#define PCI_VPD_FLAG (1<<15) /* Bit 15 starts VPD rd/wd cycle*/
256
257/* PCI_VPD_DAT_REG 32 bit (ML) VPD Data Register */
258
259/*
260 * Control Register File:
261 * Bank 0
262 */
263#define B0_RAP 0x0000 /* 8 bit register address port */
264 /* 0x0001 - 0x0003: reserved */
265#define B0_CTRL 0x0004 /* 8 bit control register */
266#define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
267#define B0_LED 0x0006 /* 8 Bit LED register */
268#define B0_TST_CTRL 0x0007 /* 8 bit test control register */
269#define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
270#define B0_IMSK 0x000c /* 32 bit Interrupt mask register */
271
272/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
273#define B0_CMDREG1 0x0010 /* write command reg 1 instruction */
274#define B0_CMDREG2 0x0014 /* write command reg 2 instruction */
275#define B0_ST1U 0x0010 /* read upper 16-bit of status reg 1 */
276#define B0_ST1L 0x0014 /* read lower 16-bit of status reg 1 */
277#define B0_ST2U 0x0018 /* read upper 16-bit of status reg 2 */
278#define B0_ST2L 0x001c /* read lower 16-bit of status reg 2 */
279
280#define B0_MARR 0x0020 /* r/w the memory read addr register */
281#define B0_MARW 0x0024 /* r/w the memory write addr register*/
282#define B0_MDRU 0x0028 /* r/w upper 16-bit of mem. data reg */
283#define B0_MDRL 0x002c /* r/w lower 16-bit of mem. data reg */
284
285#define B0_MDREG3 0x0030 /* r/w Mode Register 3 */
286#define B0_ST3U 0x0034 /* read upper 16-bit of status reg 3 */
287#define B0_ST3L 0x0038 /* read lower 16-bit of status reg 3 */
288#define B0_IMSK3U 0x003c /* r/w upper 16-bit of IMSK reg 3 */
289#define B0_IMSK3L 0x0040 /* r/w lower 16-bit of IMSK reg 3 */
290#define B0_IVR 0x0044 /* read Interrupt Vector register */
291#define B0_IMR 0x0048 /* r/w Interrupt mask register */
292/* 0x4c Hidden */
293
294#define B0_CNTRL_A 0x0050 /* control register A (r/w) */
295#define B0_CNTRL_B 0x0054 /* control register B (r/w) */
296#define B0_INTR_MASK 0x0058 /* interrupt mask (r/w) */
297#define B0_XMIT_VECTOR 0x005c /* transmit vector register (r/w) */
298
299#define B0_STATUS_A 0x0060 /* status register A (read only) */
300#define B0_STATUS_B 0x0064 /* status register B (read only) */
301#define B0_CNTRL_C 0x0068 /* control register C (r/w) */
302#define B0_MDREG1 0x006c /* r/w Mode Register 1 */
303
304#define B0_R1_CSR 0x0070 /* 32 bit BMU control/status reg (rec q 1) */
305#define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/
306#define B0_XA_CSR 0x0078 /* 32 bit BMU control/status reg (a xmit q) */
307#define B0_XS_CSR 0x007c /* 32 bit BMU control/status reg (s xmit q) */
308
309/*
310 * Bank 1
311 * - completely empty (this is the RAP Block window)
312 * Note: if RAP = 1 this page is reserved
313 */
314
315/*
316 * Bank 2
317 */
318#define B2_MAC_0 0x0100 /* 8 bit MAC address Byte 0 */
319#define B2_MAC_1 0x0101 /* 8 bit MAC address Byte 1 */
320#define B2_MAC_2 0x0102 /* 8 bit MAC address Byte 2 */
321#define B2_MAC_3 0x0103 /* 8 bit MAC address Byte 3 */
322#define B2_MAC_4 0x0104 /* 8 bit MAC address Byte 4 */
323#define B2_MAC_5 0x0105 /* 8 bit MAC address Byte 5 */
324#define B2_MAC_6 0x0106 /* 8 bit MAC address Byte 6 (== 0) (DV) */
325#define B2_MAC_7 0x0107 /* 8 bit MAC address Byte 7 (== 0) (DV) */
326
327#define B2_CONN_TYP 0x0108 /* 8 bit Connector type */
328#define B2_PMD_TYP 0x0109 /* 8 bit PMD type */
329 /* 0x010a - 0x010b: reserved */
330 /* Eprom registers are currently of no use */
331#define B2_E_0 0x010c /* 8 bit EPROM Byte 0 */
332#define B2_E_1 0x010d /* 8 bit EPROM Byte 1 */
333#define B2_E_2 0x010e /* 8 bit EPROM Byte 2 */
334#define B2_E_3 0x010f /* 8 bit EPROM Byte 3 */
335#define B2_FAR 0x0110 /* 32 bit Flash-Prom Address Register/Counter */
336#define B2_FDP 0x0114 /* 8 bit Flash-Prom Data Port */
337 /* 0x0115 - 0x0117: reserved */
338#define B2_LD_CRTL 0x0118 /* 8 bit loader control */
339#define B2_LD_TEST 0x0119 /* 8 bit loader test */
340 /* 0x011a - 0x011f: reserved */
341#define B2_TI_INI 0x0120 /* 32 bit Timer init value */
342#define B2_TI_VAL 0x0124 /* 32 bit Timer value */
343#define B2_TI_CRTL 0x0128 /* 8 bit Timer control */
344#define B2_TI_TEST 0x0129 /* 8 Bit Timer Test */
345 /* 0x012a - 0x012f: reserved */
346#define B2_WDOG_INI 0x0130 /* 32 bit Watchdog init value */
347#define B2_WDOG_VAL 0x0134 /* 32 bit Watchdog value */
348#define B2_WDOG_CRTL 0x0138 /* 8 bit Watchdog control */
349#define B2_WDOG_TEST 0x0139 /* 8 Bit Watchdog Test */
350 /* 0x013a - 0x013f: reserved */
351#define B2_RTM_INI 0x0140 /* 32 bit RTM init value */
352#define B2_RTM_VAL 0x0144 /* 32 bit RTM value */
353#define B2_RTM_CRTL 0x0148 /* 8 bit RTM control */
354#define B2_RTM_TEST 0x0149 /* 8 Bit RTM Test */
355
356#define B2_TOK_COUNT 0x014c /* (ML) 32 bit Token Counter */
357#define B2_DESC_ADDR_H 0x0150 /* (ML) 32 bit Desciptor Base Addr Reg High */
358#define B2_CTRL_2 0x0154 /* (ML) 8 bit Control Register 2 */
359#define B2_IFACE_REG 0x0155 /* (ML) 8 bit Interface Register */
360 /* 0x0156: reserved */
361#define B2_TST_CTRL_2 0x0157 /* (ML) 8 bit Test Control Register 2 */
362#define B2_I2C_CTRL 0x0158 /* (ML) 32 bit I2C Control Register */
363#define B2_I2C_DATA 0x015c /* (ML) 32 bit I2C Data Register */
364
365#define B2_IRQ_MOD_INI 0x0160 /* (ML) 32 bit IRQ Moderation Timer Init Reg. */
366#define B2_IRQ_MOD_VAL 0x0164 /* (ML) 32 bit IRQ Moderation Timer Value */
367#define B2_IRQ_MOD_CTRL 0x0168 /* (ML) 8 bit IRQ Moderation Timer Control */
368#define B2_IRQ_MOD_TEST 0x0169 /* (ML) 8 bit IRQ Moderation Timer Test */
369 /* 0x016a - 0x017f: reserved */
370
371/*
372 * Bank 3
373 */
374/*
375 * This is a copy of the Configuration register file (lower half)
376 */
377#define B3_CFG_SPC 0x180
378
379/*
380 * Bank 4
381 */
382#define B4_R1_D 0x0200 /* 4*32 bit current receive Descriptor */
383#define B4_R1_DA 0x0210 /* 32 bit current rec desc address */
384#define B4_R1_AC 0x0214 /* 32 bit current receive Address Count */
385#define B4_R1_BC 0x0218 /* 32 bit current receive Byte Counter */
386#define B4_R1_CSR 0x021c /* 32 bit BMU Control/Status Register */
387#define B4_R1_F 0x0220 /* 32 bit flag register */
388#define B4_R1_T1 0x0224 /* 32 bit Test Register 1 */
389#define B4_R1_T1_TR 0x0224 /* 8 bit Test Register 1 TR */
390#define B4_R1_T1_WR 0x0225 /* 8 bit Test Register 1 WR */
391#define B4_R1_T1_RD 0x0226 /* 8 bit Test Register 1 RD */
392#define B4_R1_T1_SV 0x0227 /* 8 bit Test Register 1 SV */
393#define B4_R1_T2 0x0228 /* 32 bit Test Register 2 */
394#define B4_R1_T3 0x022c /* 32 bit Test Register 3 */
395#define B4_R1_DA_H 0x0230 /* (ML) 32 bit Curr Rx Desc Address High */
396#define B4_R1_AC_H 0x0234 /* (ML) 32 bit Curr Addr Counter High dword */
397 /* 0x0238 - 0x023f: reserved */
398 /* Receive queue 2 is removed on Monalisa */
399#define B4_R2_D 0x0240 /* 4*32 bit current receive Descriptor (q2) */
400#define B4_R2_DA 0x0250 /* 32 bit current rec desc address (q2) */
401#define B4_R2_AC 0x0254 /* 32 bit current receive Address Count (q2) */
402#define B4_R2_BC 0x0258 /* 32 bit current receive Byte Counter (q2) */
403#define B4_R2_CSR 0x025c /* 32 bit BMU Control/Status Register (q2) */
404#define B4_R2_F 0x0260 /* 32 bit flag register (q2) */
405#define B4_R2_T1 0x0264 /* 32 bit Test Register 1 (q2) */
406#define B4_R2_T1_TR 0x0264 /* 8 bit Test Register 1 TR (q2) */
407#define B4_R2_T1_WR 0x0265 /* 8 bit Test Register 1 WR (q2) */
408#define B4_R2_T1_RD 0x0266 /* 8 bit Test Register 1 RD (q2) */
409#define B4_R2_T1_SV 0x0267 /* 8 bit Test Register 1 SV (q2) */
410#define B4_R2_T2 0x0268 /* 32 bit Test Register 2 (q2) */
411#define B4_R2_T3 0x026c /* 32 bit Test Register 3 (q2) */
412 /* 0x0270 - 0x027c: reserved */
413
414/*
415 * Bank 5
416 */
417#define B5_XA_D 0x0280 /* 4*32 bit current transmit Descriptor (xa) */
418#define B5_XA_DA 0x0290 /* 32 bit current tx desc address (xa) */
419#define B5_XA_AC 0x0294 /* 32 bit current tx Address Count (xa) */
420#define B5_XA_BC 0x0298 /* 32 bit current tx Byte Counter (xa) */
421#define B5_XA_CSR 0x029c /* 32 bit BMU Control/Status Register (xa) */
422#define B5_XA_F 0x02a0 /* 32 bit flag register (xa) */
423#define B5_XA_T1 0x02a4 /* 32 bit Test Register 1 (xa) */
424#define B5_XA_T1_TR 0x02a4 /* 8 bit Test Register 1 TR (xa) */
425#define B5_XA_T1_WR 0x02a5 /* 8 bit Test Register 1 WR (xa) */
426#define B5_XA_T1_RD 0x02a6 /* 8 bit Test Register 1 RD (xa) */
427#define B5_XA_T1_SV 0x02a7 /* 8 bit Test Register 1 SV (xa) */
428#define B5_XA_T2 0x02a8 /* 32 bit Test Register 2 (xa) */
429#define B5_XA_T3 0x02ac /* 32 bit Test Register 3 (xa) */
430#define B5_XA_DA_H 0x02b0 /* (ML) 32 bit Curr Tx Desc Address High */
431#define B5_XA_AC_H 0x02b4 /* (ML) 32 bit Curr Addr Counter High dword */
432 /* 0x02b8 - 0x02bc: reserved */
433#define B5_XS_D 0x02c0 /* 4*32 bit current transmit Descriptor (xs) */
434#define B5_XS_DA 0x02d0 /* 32 bit current tx desc address (xs) */
435#define B5_XS_AC 0x02d4 /* 32 bit current transmit Address Count(xs) */
436#define B5_XS_BC 0x02d8 /* 32 bit current transmit Byte Counter (xs) */
437#define B5_XS_CSR 0x02dc /* 32 bit BMU Control/Status Register (xs) */
438#define B5_XS_F 0x02e0 /* 32 bit flag register (xs) */
439#define B5_XS_T1 0x02e4 /* 32 bit Test Register 1 (xs) */
440#define B5_XS_T1_TR 0x02e4 /* 8 bit Test Register 1 TR (xs) */
441#define B5_XS_T1_WR 0x02e5 /* 8 bit Test Register 1 WR (xs) */
442#define B5_XS_T1_RD 0x02e6 /* 8 bit Test Register 1 RD (xs) */
443#define B5_XS_T1_SV 0x02e7 /* 8 bit Test Register 1 SV (xs) */
444#define B5_XS_T2 0x02e8 /* 32 bit Test Register 2 (xs) */
445#define B5_XS_T3 0x02ec /* 32 bit Test Register 3 (xs) */
446#define B5_XS_DA_H 0x02f0 /* (ML) 32 bit Curr Tx Desc Address High */
447#define B5_XS_AC_H 0x02f4 /* (ML) 32 bit Curr Addr Counter High dword */
448 /* 0x02f8 - 0x02fc: reserved */
449
450/*
451 * Bank 6
452 */
453/* External PLC-S registers (SN2 compatibility for DV) */
454/* External registers (ML) */
455#define B6_EXT_REG 0x300
456
457/*
458 * Bank 7
459 */
460/* DAS PLC-S Registers */
461
462/*
463 * Bank 8 - 15
464 */
465/* IFCP registers */
466
467/*---------------------------------------------------------------------------*/
468/* Definitions of the Bits in the registers */
469
470/* B0_RAP 16 bit register address port */
471#define RAP_RAP 0x0f /* Bit 3..0: 0 = block0, .., f = block15 */
472
473/* B0_CTRL 8 bit control register */
474#define CTRL_FDDI_CLR (1<<7) /* Bit 7: (ML) Clear FDDI Reset */
475#define CTRL_FDDI_SET (1<<6) /* Bit 6: (ML) Set FDDI Reset */
476#define CTRL_HPI_CLR (1<<5) /* Bit 5: Clear HPI SM reset */
477#define CTRL_HPI_SET (1<<4) /* Bit 4: Set HPI SM reset */
478#define CTRL_MRST_CLR (1<<3) /* Bit 3: Clear Master reset */
479#define CTRL_MRST_SET (1<<2) /* Bit 2: Set Master reset */
480#define CTRL_RST_CLR (1<<1) /* Bit 1: Clear Software reset */
481#define CTRL_RST_SET (1<<0) /* Bit 0: Set Software reset */
482
483/* B0_DAS 8 Bit control register (DAS) */
484#define BUS_CLOCK (1<<7) /* Bit 7: (ML) Bus Clock 0/1 = 33/66MHz */
485#define BUS_SLOT_SZ (1<<6) /* Bit 6: (ML) Slot Size 0/1 = 32/64 bit slot*/
486 /* Bit 5..4: reserved */
487#define DAS_AVAIL (1<<3) /* Bit 3: 1 = DAS, 0 = SAS */
488#define DAS_BYP_ST (1<<2) /* Bit 2: 1 = avail,SAS, 0 = not avail */
489#define DAS_BYP_INS (1<<1) /* Bit 1: 1 = insert Bypass */
490#define DAS_BYP_RMV (1<<0) /* Bit 0: 1 = remove Bypass */
491
492/* B0_LED 8 Bit LED register */
493 /* Bit 7..6: reserved */
494#define LED_2_ON (1<<5) /* Bit 5: 1 = switch LED_2 on (left,gn)*/
495#define LED_2_OFF (1<<4) /* Bit 4: 1 = switch LED_2 off */
496#define LED_1_ON (1<<3) /* Bit 3: 1 = switch LED_1 on (mid,yel)*/
497#define LED_1_OFF (1<<2) /* Bit 2: 1 = switch LED_1 off */
498#define LED_0_ON (1<<1) /* Bit 1: 1 = switch LED_0 on (rght,gn)*/
499#define LED_0_OFF (1<<0) /* Bit 0: 1 = switch LED_0 off */
500/* This hardware defines are very ugly therefore we define some others */
501
502#define LED_GA_ON LED_2_ON /* S port = A port */
503#define LED_GA_OFF LED_2_OFF /* S port = A port */
504#define LED_MY_ON LED_1_ON
505#define LED_MY_OFF LED_1_OFF
506#define LED_GB_ON LED_0_ON
507#define LED_GB_OFF LED_0_OFF
508
509/* B0_TST_CTRL 8 bit test control register */
510#define TST_FRC_DPERR_MR (1<<7) /* Bit 7: force DATAPERR on MST RE. */
511#define TST_FRC_DPERR_MW (1<<6) /* Bit 6: force DATAPERR on MST WR. */
512#define TST_FRC_DPERR_TR (1<<5) /* Bit 5: force DATAPERR on TRG RE. */
513#define TST_FRC_DPERR_TW (1<<4) /* Bit 4: force DATAPERR on TRG WR. */
514#define TST_FRC_APERR_M (1<<3) /* Bit 3: force ADDRPERR on MST */
515#define TST_FRC_APERR_T (1<<2) /* Bit 2: force ADDRPERR on TRG */
516#define TST_CFG_WRITE_ON (1<<1) /* Bit 1: ena configuration reg. WR */
517#define TST_CFG_WRITE_OFF (1<<0) /* Bit 0: dis configuration reg. WR */
518
519/* B0_ISRC 32 bit Interrupt source register */
520 /* Bit 31..28: reserved */
521#define IS_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
522#define IS_IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
523#define IS_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
524#define IS_IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
525 /* PERR, RMABORT, RTABORT DATAPERR */
526#define IS_IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
527 /* RMABORT, RTABORT, DATAPERR */
528#define IS_TIMINT (1L<<22) /* Bit 22: IRQ_TIMER */
529#define IS_TOKEN (1L<<21) /* Bit 21: IRQ_RTM */
530/*
531 * Note: The DAS is our First Port (!=PA)
532 */
533#define IS_PLINT1 (1L<<20) /* Bit 20: IRQ_PHY_DAS */
534#define IS_PLINT2 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
535#define IS_MINTR3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
536#define IS_MINTR2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
537#define IS_MINTR1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
538/* Receive Queue 1 */
539#define IS_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
540#define IS_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
541#define IS_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
542#define IS_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
543/* Receive Queue 2 */
544#define IS_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
545#define IS_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
546#define IS_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
547#define IS_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
548/* Asynchronous Transmit queue */
549 /* Bit 7: reserved */
550#define IS_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
551#define IS_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
552#define IS_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
553/* Synchronous Transmit queue */
554 /* Bit 3: reserved */
555#define IS_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
556#define IS_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
557#define IS_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
558
559/*
560 * Define all valid interrupt source Bits from GET_ISR ()
561 */
562#define ALL_IRSR 0x01ffff77L /* (DV) */
563#define ALL_IRSR_ML 0x0ffff077L /* (ML) */
564
565
566/* B0_IMSK 32 bit Interrupt mask register */
567/*
568 * The Bit definnition of this register are the same as of the interrupt
569 * source register. These definition are directly derived from the Hardware
570 * spec.
571 */
572 /* Bit 31..28: reserved */
573#define IRQ_I2C_READY (1L<<27) /* Bit 27: (ML) IRQ on end of I2C tx */
574#define IRQ_SW (1L<<26) /* Bit 26: (ML) SW forced IRQ */
575#define IRQ_EXT_REG (1L<<25) /* Bit 25: (ML) IRQ from external reg*/
576#define IRQ_STAT (1L<<24) /* Bit 24: IRQ status exception */
577 /* PERR, RMABORT, RTABORT DATAPERR */
578#define IRQ_MST_ERR (1L<<23) /* Bit 23: IRQ master error */
579 /* RMABORT, RTABORT, DATAPERR */
580#define IRQ_TIMER (1L<<22) /* Bit 22: IRQ_TIMER */
581#define IRQ_RTM (1L<<21) /* Bit 21: IRQ_RTM */
582#define IRQ_DAS (1L<<20) /* Bit 20: IRQ_PHY_DAS */
583#define IRQ_IFCP_4 (1L<<19) /* Bit 19: IRQ_IFCP_4 */
584#define IRQ_IFCP_3 (1L<<18) /* Bit 18: IRQ_IFCP_3/IRQ_PHY */
585#define IRQ_IFCP_2 (1L<<17) /* Bit 17: IRQ_IFCP_2/IRQ_MAC_2 */
586#define IRQ_IFCP_1 (1L<<16) /* Bit 16: IRQ_IFCP_1/IRQ_MAC_1 */
587/* Receive Queue 1 */
588#define IRQ_R1_P (1L<<15) /* Bit 15: Parity Error (q1) */
589#define IRQ_R1_B (1L<<14) /* Bit 14: End of Buffer (q1) */
590#define IRQ_R1_F (1L<<13) /* Bit 13: End of Frame (q1) */
591#define IRQ_R1_C (1L<<12) /* Bit 12: Encoding Error (q1) */
592/* Receive Queue 2 */
593#define IRQ_R2_P (1L<<11) /* Bit 11: (DV) Parity Error (q2) */
594#define IRQ_R2_B (1L<<10) /* Bit 10: (DV) End of Buffer (q2) */
595#define IRQ_R2_F (1L<<9) /* Bit 9: (DV) End of Frame (q2) */
596#define IRQ_R2_C (1L<<8) /* Bit 8: (DV) Encoding Error (q2) */
597/* Asynchronous Transmit queue */
598 /* Bit 7: reserved */
599#define IRQ_XA_B (1L<<6) /* Bit 6: End of Buffer (xa) */
600#define IRQ_XA_F (1L<<5) /* Bit 5: End of Frame (xa) */
601#define IRQ_XA_C (1L<<4) /* Bit 4: Encoding Error (xa) */
602/* Synchronous Transmit queue */
603 /* Bit 3: reserved */
604#define IRQ_XS_B (1L<<2) /* Bit 2: End of Buffer (xs) */
605#define IRQ_XS_F (1L<<1) /* Bit 1: End of Frame (xs) */
606#define IRQ_XS_C (1L<<0) /* Bit 0: Encoding Error (xs) */
607
608/* 0x0010 - 0x006b: formac+ (supernet_3) fequently used registers */
609/* B0_R1_CSR 32 bit BMU control/status reg (rec q 1 ) */
610/* B0_R2_CSR 32 bit BMU control/status reg (rec q 2 ) */
611/* B0_XA_CSR 32 bit BMU control/status reg (a xmit q ) */
612/* B0_XS_CSR 32 bit BMU control/status reg (s xmit q ) */
613/* The registers are the same as B4_R1_CSR, B4_R2_CSR, B5_Xa_CSR, B5_XS_CSR */
614
615/* B2_MAC_0 8 bit MAC address Byte 0 */
616/* B2_MAC_1 8 bit MAC address Byte 1 */
617/* B2_MAC_2 8 bit MAC address Byte 2 */
618/* B2_MAC_3 8 bit MAC address Byte 3 */
619/* B2_MAC_4 8 bit MAC address Byte 4 */
620/* B2_MAC_5 8 bit MAC address Byte 5 */
621/* B2_MAC_6 8 bit MAC address Byte 6 (== 0) (DV) */
622/* B2_MAC_7 8 bit MAC address Byte 7 (== 0) (DV) */
623
624/* B2_CONN_TYP 8 bit Connector type */
625/* B2_PMD_TYP 8 bit PMD type */
626/* Values of connector and PMD type comply to SysKonnect internal std */
627
628/* The EPROM register are currently of no use */
629/* B2_E_0 8 bit EPROM Byte 0 */
630/* B2_E_1 8 bit EPROM Byte 1 */
631/* B2_E_2 8 bit EPROM Byte 2 */
632/* B2_E_3 8 bit EPROM Byte 3 */
633
634/* B2_FAR 32 bit Flash-Prom Address Register/Counter */
635#define FAR_ADDR 0x1ffffL /* Bit 16..0: FPROM Address mask */
636
637/* B2_FDP 8 bit Flash-Prom Data Port */
638
639/* B2_LD_CRTL 8 bit loader control */
640/* Bits are currently reserved */
641
642/* B2_LD_TEST 8 bit loader test */
643#define LD_T_ON (1<<3) /* Bit 3: Loader Testmode on */
644#define LD_T_OFF (1<<2) /* Bit 2: Loader Testmode off */
645#define LD_T_STEP (1<<1) /* Bit 1: Decrement FPROM addr. Counter */
646#define LD_START (1<<0) /* Bit 0: Start loading FPROM */
647
648/* B2_TI_INI 32 bit Timer init value */
649/* B2_TI_VAL 32 bit Timer value */
650/* B2_TI_CRTL 8 bit Timer control */
651/* B2_TI_TEST 8 Bit Timer Test */
652/* B2_WDOG_INI 32 bit Watchdog init value */
653/* B2_WDOG_VAL 32 bit Watchdog value */
654/* B2_WDOG_CRTL 8 bit Watchdog control */
655/* B2_WDOG_TEST 8 Bit Watchdog Test */
656/* B2_RTM_INI 32 bit RTM init value */
657/* B2_RTM_VAL 32 bit RTM value */
658/* B2_RTM_CRTL 8 bit RTM control */
659/* B2_RTM_TEST 8 Bit RTM Test */
660/* B2_<TIM>_CRTL 8 bit <TIM> control */
661/* B2_IRQ_MOD_INI 32 bit IRQ Moderation Timer Init Reg. (ML) */
662/* B2_IRQ_MOD_VAL 32 bit IRQ Moderation Timer Value (ML) */
663/* B2_IRQ_MOD_CTRL 8 bit IRQ Moderation Timer Control (ML) */
664/* B2_IRQ_MOD_TEST 8 bit IRQ Moderation Timer Test (ML) */
665#define GET_TOK_CT (1<<4) /* Bit 4: Get the Token Counter (RTM) */
666#define TIM_RES_TOK (1<<3) /* Bit 3: RTM Status: 1 == restricted */
667#define TIM_ALARM (1<<3) /* Bit 3: Timer Alarm (WDOG) */
668#define TIM_START (1<<2) /* Bit 2: Start Timer (TI,WDOG,RTM,IRQ_MOD)*/
669#define TIM_STOP (1<<1) /* Bit 1: Stop Timer (TI,WDOG,RTM,IRQ_MOD) */
670#define TIM_CL_IRQ (1<<0) /* Bit 0: Clear Timer IRQ (TI,WDOG,RTM) */
671/* B2_<TIM>_TEST 8 Bit <TIM> Test */
672#define TIM_T_ON (1<<2) /* Bit 2: Test mode on (TI,WDOG,RTM,IRQ_MOD) */
673#define TIM_T_OFF (1<<1) /* Bit 1: Test mode off (TI,WDOG,RTM,IRQ_MOD) */
674#define TIM_T_STEP (1<<0) /* Bit 0: Test step (TI,WDOG,RTM,IRQ_MOD) */
675
676/* B2_TOK_COUNT 0x014c (ML) 32 bit Token Counter */
677/* B2_DESC_ADDR_H 0x0150 (ML) 32 bit Desciptor Base Addr Reg High */
678/* B2_CTRL_2 0x0154 (ML) 8 bit Control Register 2 */
679 /* Bit 7..5: reserved */
680#define CTRL_CL_I2C_IRQ (1<<4) /* Bit 4: Clear I2C IRQ */
681#define CTRL_ST_SW_IRQ (1<<3) /* Bit 3: Set IRQ SW Request */
682#define CTRL_CL_SW_IRQ (1<<2) /* Bit 2: Clear IRQ SW Request */
683#define CTRL_STOP_DONE (1<<1) /* Bit 1: Stop Master is finished */
684#define CTRL_STOP_MAST (1<<0) /* Bit 0: Command Bit to stop the master*/
685
686/* B2_IFACE_REG 0x0155 (ML) 8 bit Interface Register */
687 /* Bit 7..3: reserved */
688#define IF_I2C_DATA_DIR (1<<2) /* Bit 2: direction of IF_I2C_DATA*/
689#define IF_I2C_DATA (1<<1) /* Bit 1: I2C Data Port */
690#define IF_I2C_CLK (1<<0) /* Bit 0: I2C Clock Port */
691
692 /* 0x0156: reserved */
693/* B2_TST_CTRL_2 0x0157 (ML) 8 bit Test Control Register 2 */
694 /* Bit 7..4: reserved */
695 /* force the following error on */
696 /* the next master read/write */
697#define TST_FRC_DPERR_MR64 (1<<3) /* Bit 3: DataPERR RD 64 */
698#define TST_FRC_DPERR_MW64 (1<<2) /* Bit 2: DataPERR WR 64 */
699#define TST_FRC_APERR_1M64 (1<<1) /* Bit 1: AddrPERR on 1. phase */
700#define TST_FRC_APERR_2M64 (1<<0) /* Bit 0: AddrPERR on 2. phase */
701
702/* B2_I2C_CTRL 0x0158 (ML) 32 bit I2C Control Register */
703#define I2C_FLAG (1L<<31) /* Bit 31: Start read/write if WR */
704#define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be read/written*/
705#define I2C_DEV_SEL (0x7fL<<9) /* Bit 9..15: I2C Device Select */
706 /* Bit 5.. 8: reserved */
707#define I2C_BURST_LEN (1L<<4) /* Bit 4 Burst Len, 1/4 bytes */
708#define I2C_DEV_SIZE (7L<<1) /* Bit 1.. 3: I2C Device Size */
709#define I2C_025K_DEV (0L<<1) /* 0: 256 Bytes or smaller*/
710#define I2C_05K_DEV (1L<<1) /* 1: 512 Bytes */
711#define I2C_1K_DEV (2L<<1) /* 2: 1024 Bytes */
712#define I2C_2K_DEV (3L<<1) /* 3: 2048 Bytes */
713#define I2C_4K_DEV (4L<<1) /* 4: 4096 Bytes */
714#define I2C_8K_DEV (5L<<1) /* 5: 8192 Bytes */
715#define I2C_16K_DEV (6L<<1) /* 6: 16384 Bytes */
716#define I2C_32K_DEV (7L<<1) /* 7: 32768 Bytes */
717#define I2C_STOP_BIT (1<<0) /* Bit 0: Interrupt I2C transfer */
718
719/*
720 * I2C Addresses
721 *
722 * The temperature sensor and the voltage sensor are on the same I2C bus.
723 * Note: The voltage sensor (Micorwire) will be selected by PCI_EXT_PATCH_1
724 * in PCI_OUR_REG 1.
725 */
726#define I2C_ADDR_TEMP 0x90 /* I2C Address Temperature Sensor */
727
728/* B2_I2C_DATA 0x015c (ML) 32 bit I2C Data Register */
729
730/* B4_R1_D 4*32 bit current receive Descriptor (q1) */
731/* B4_R1_DA 32 bit current rec desc address (q1) */
732/* B4_R1_AC 32 bit current receive Address Count (q1) */
733/* B4_R1_BC 32 bit current receive Byte Counter (q1) */
734/* B4_R1_CSR 32 bit BMU Control/Status Register (q1) */
735/* B4_R1_F 32 bit flag register (q1) */
736/* B4_R1_T1 32 bit Test Register 1 (q1) */
737/* B4_R1_T2 32 bit Test Register 2 (q1) */
738/* B4_R1_T3 32 bit Test Register 3 (q1) */
739/* B4_R2_D 4*32 bit current receive Descriptor (q2) */
740/* B4_R2_DA 32 bit current rec desc address (q2) */
741/* B4_R2_AC 32 bit current receive Address Count (q2) */
742/* B4_R2_BC 32 bit current receive Byte Counter (q2) */
743/* B4_R2_CSR 32 bit BMU Control/Status Register (q2) */
744/* B4_R2_F 32 bit flag register (q2) */
745/* B4_R2_T1 32 bit Test Register 1 (q2) */
746/* B4_R2_T2 32 bit Test Register 2 (q2) */
747/* B4_R2_T3 32 bit Test Register 3 (q2) */
748/* B5_XA_D 4*32 bit current receive Descriptor (xa) */
749/* B5_XA_DA 32 bit current rec desc address (xa) */
750/* B5_XA_AC 32 bit current receive Address Count (xa) */
751/* B5_XA_BC 32 bit current receive Byte Counter (xa) */
752/* B5_XA_CSR 32 bit BMU Control/Status Register (xa) */
753/* B5_XA_F 32 bit flag register (xa) */
754/* B5_XA_T1 32 bit Test Register 1 (xa) */
755/* B5_XA_T2 32 bit Test Register 2 (xa) */
756/* B5_XA_T3 32 bit Test Register 3 (xa) */
757/* B5_XS_D 4*32 bit current receive Descriptor (xs) */
758/* B5_XS_DA 32 bit current rec desc address (xs) */
759/* B5_XS_AC 32 bit current receive Address Count (xs) */
760/* B5_XS_BC 32 bit current receive Byte Counter (xs) */
761/* B5_XS_CSR 32 bit BMU Control/Status Register (xs) */
762/* B5_XS_F 32 bit flag register (xs) */
763/* B5_XS_T1 32 bit Test Register 1 (xs) */
764/* B5_XS_T2 32 bit Test Register 2 (xs) */
765/* B5_XS_T3 32 bit Test Register 3 (xs) */
766/* B5_<xx>_CSR 32 bit BMU Control/Status Register (xx) */
767#define CSR_DESC_CLEAR (1L<<21) /* Bit 21: Clear Reset for Descr */
768#define CSR_DESC_SET (1L<<20) /* Bit 20: Set Reset for Descr */
769#define CSR_FIFO_CLEAR (1L<<19) /* Bit 19: Clear Reset for FIFO */
770#define CSR_FIFO_SET (1L<<18) /* Bit 18: Set Reset for FIFO */
771#define CSR_HPI_RUN (1L<<17) /* Bit 17: Release HPI SM */
772#define CSR_HPI_RST (1L<<16) /* Bit 16: Reset HPI SM to Idle */
773#define CSR_SV_RUN (1L<<15) /* Bit 15: Release Supervisor SM */
774#define CSR_SV_RST (1L<<14) /* Bit 14: Reset Supervisor SM */
775#define CSR_DREAD_RUN (1L<<13) /* Bit 13: Release Descr Read SM */
776#define CSR_DREAD_RST (1L<<12) /* Bit 12: Reset Descr Read SM */
777#define CSR_DWRITE_RUN (1L<<11) /* Bit 11: Rel. Descr Write SM */
778#define CSR_DWRITE_RST (1L<<10) /* Bit 10: Reset Descr Write SM */
779#define CSR_TRANS_RUN (1L<<9) /* Bit 9: Release Transfer SM */
780#define CSR_TRANS_RST (1L<<8) /* Bit 8: Reset Transfer SM */
781 /* Bit 7..5: reserved */
782#define CSR_START (1L<<4) /* Bit 4: Start Rec/Xmit Queue */
783#define CSR_IRQ_CL_P (1L<<3) /* Bit 3: Clear Parity IRQ, Rcv */
784#define CSR_IRQ_CL_B (1L<<2) /* Bit 2: Clear EOB IRQ */
785#define CSR_IRQ_CL_F (1L<<1) /* Bit 1: Clear EOF IRQ */
786#define CSR_IRQ_CL_C (1L<<0) /* Bit 0: Clear ERR IRQ */
787
788#define CSR_SET_RESET (CSR_DESC_SET|CSR_FIFO_SET|CSR_HPI_RST|CSR_SV_RST|\
789 CSR_DREAD_RST|CSR_DWRITE_RST|CSR_TRANS_RST)
790#define CSR_CLR_RESET (CSR_DESC_CLEAR|CSR_FIFO_CLEAR|CSR_HPI_RUN|CSR_SV_RUN|\
791 CSR_DREAD_RUN|CSR_DWRITE_RUN|CSR_TRANS_RUN)
792
793
794/* B5_<xx>_F 32 bit flag register (xx) */
795 /* Bit 28..31: reserved */
796#define F_ALM_FULL (1L<<27) /* Bit 27: (ML) FIFO almost full */
797#define F_FIFO_EOF (1L<<26) /* Bit 26: (ML) Fag bit in FIFO */
798#define F_WM_REACHED (1L<<25) /* Bit 25: (ML) Watermark reached */
799#define F_UP_DW_USED (1L<<24) /* Bit 24: (ML) Upper Dword used (bug)*/
800 /* Bit 23: reserved */
801#define F_FIFO_LEVEL (0x1fL<<16) /* Bit 16..22:(ML) # of Qwords in FIFO*/
802 /* Bit 8..15: reserved */
803#define F_ML_WATER_M 0x0000ffL /* Bit 0.. 7:(ML) Watermark */
804#define FLAG_WATER 0x00001fL /* Bit 4..0:(DV) Level of req data tr.*/
805
806/* B5_<xx>_T1 32 bit Test Register 1 (xx) */
807/* Holds four State Machine control Bytes */
808#define SM_CRTL_SV (0xffL<<24) /* Bit 31..24: Control Supervisor SM */
809#define SM_CRTL_RD (0xffL<<16) /* Bit 23..16: Control Read Desc SM */
810#define SM_CRTL_WR (0xffL<<8) /* Bit 15..8: Control Write Desc SM */
811#define SM_CRTL_TR (0xffL<<0) /* Bit 7..0: Control Transfer SM */
812
813/* B4_<xx>_T1_TR 8 bit Test Register 1 TR (xx) */
814/* B4_<xx>_T1_WR 8 bit Test Register 1 WR (xx) */
815/* B4_<xx>_T1_RD 8 bit Test Register 1 RD (xx) */
816/* B4_<xx>_T1_SV 8 bit Test Register 1 SV (xx) */
817/* The control status byte of each machine looks like ... */
818#define SM_STATE 0xf0 /* Bit 7..4: State which shall be loaded */
819#define SM_LOAD 0x08 /* Bit 3: Load the SM with SM_STATE */
820#define SM_TEST_ON 0x04 /* Bit 2: Switch on SM Test Mode */
821#define SM_TEST_OFF 0x02 /* Bit 1: Go off the Test Mode */
822#define SM_STEP 0x01 /* Bit 0: Step the State Machine */
823
824/* The coding of the states */
825#define SM_SV_IDLE 0x0 /* Supervisor Idle Tr/Re */
826#define SM_SV_RES_START 0x1 /* Supervisor Res_Start Tr/Re */
827#define SM_SV_GET_DESC 0x3 /* Supervisor Get_Desc Tr/Re */
828#define SM_SV_CHECK 0x2 /* Supervisor Check Tr/Re */
829#define SM_SV_MOV_DATA 0x6 /* Supervisor Move_Data Tr/Re */
830#define SM_SV_PUT_DESC 0x7 /* Supervisor Put_Desc Tr/Re */
831#define SM_SV_SET_IRQ 0x5 /* Supervisor Set_Irq Tr/Re */
832
833#define SM_RD_IDLE 0x0 /* Read Desc. Idle Tr/Re */
834#define SM_RD_LOAD 0x1 /* Read Desc. Load Tr/Re */
835#define SM_RD_WAIT_TC 0x3 /* Read Desc. Wait_TC Tr/Re */
836#define SM_RD_RST_EOF 0x6 /* Read Desc. Reset_EOF Re */
837#define SM_RD_WDONE_R 0x2 /* Read Desc. Wait_Done Re */
838#define SM_RD_WDONE_T 0x4 /* Read Desc. Wait_Done Tr */
839
840#define SM_TR_IDLE 0x0 /* Trans. Data Idle Tr/Re */
841#define SM_TR_LOAD 0x3 /* Trans. Data Load Tr/Re */
842#define SM_TR_LOAD_R_ML 0x1 /* Trans. Data Load /Re (ML) */
843#define SM_TR_WAIT_TC 0x2 /* Trans. Data Wait_TC Tr/Re */
844#define SM_TR_WDONE 0x4 /* Trans. Data Wait_Done Tr/Re */
845
846#define SM_WR_IDLE 0x0 /* Write Desc. Idle Tr/Re */
847#define SM_WR_ABLEN 0x1 /* Write Desc. Act_Buf_Length Tr/Re */
848#define SM_WR_LD_A4 0x2 /* Write Desc. Load_A4 Re */
849#define SM_WR_RES_OWN 0x2 /* Write Desc. Res_OWN Tr */
850#define SM_WR_WAIT_EOF 0x3 /* Write Desc. Wait_EOF Re */
851#define SM_WR_LD_N2C_R 0x4 /* Write Desc. Load_N2C Re */
852#define SM_WR_WAIT_TC_R 0x5 /* Write Desc. Wait_TC Re */
853#define SM_WR_WAIT_TC4 0x6 /* Write Desc. Wait_TC4 Re */
854#define SM_WR_LD_A_T 0x6 /* Write Desc. Load_A Tr */
855#define SM_WR_LD_A_R 0x7 /* Write Desc. Load_A Re */
856#define SM_WR_WAIT_TC_T 0x7 /* Write Desc. Wait_TC Tr */
857#define SM_WR_LD_N2C_T 0xc /* Write Desc. Load_N2C Tr */
858#define SM_WR_WDONE_T 0x9 /* Write Desc. Wait_Done Tr */
859#define SM_WR_WDONE_R 0xc /* Write Desc. Wait_Done Re */
860#define SM_WR_LD_D_AD 0xe /* Write Desc. Load_Dumr_A Re (ML) */
861#define SM_WR_WAIT_D_TC 0xf /* Write Desc. Wait_Dumr_TC Re (ML) */
862
863/* B5_<xx>_T2 32 bit Test Register 2 (xx) */
864/* Note: This register is only defined for the transmit queues */
865 /* Bit 31..8: reserved */
866#define AC_TEST_ON (1<<7) /* Bit 7: Address Counter Test Mode on */
867#define AC_TEST_OFF (1<<6) /* Bit 6: Address Counter Test Mode off*/
868#define BC_TEST_ON (1<<5) /* Bit 5: Byte Counter Test Mode on */
869#define BC_TEST_OFF (1<<4) /* Bit 4: Byte Counter Test Mode off */
870#define TEST_STEP04 (1<<3) /* Bit 3: Inc AC/Dec BC by 4 */
871#define TEST_STEP03 (1<<2) /* Bit 2: Inc AC/Dec BC by 3 */
872#define TEST_STEP02 (1<<1) /* Bit 1: Inc AC/Dec BC by 2 */
873#define TEST_STEP01 (1<<0) /* Bit 0: Inc AC/Dec BC by 1 */
874
875/* B5_<xx>_T3 32 bit Test Register 3 (xx) */
876/* Note: This register is only defined for the transmit queues */
877 /* Bit 31..8: reserved */
878#define T3_MUX_2 (1<<7) /* Bit 7: (ML) Mux position MSB */
879#define T3_VRAM_2 (1<<6) /* Bit 6: (ML) Virtual RAM buffer addr MSB */
880#define T3_LOOP (1<<5) /* Bit 5: Set Loopback (Xmit) */
881#define T3_UNLOOP (1<<4) /* Bit 4: Unset Loopback (Xmit) */
882#define T3_MUX (3<<2) /* Bit 3..2: Mux position */
883#define T3_VRAM (3<<0) /* Bit 1..0: Virtual RAM buffer Address */
884
885/* PCI card IDs */
886/*
887 * Note: The following 4 byte definitions shall not be used! Use OEM Concept!
888 */
889#define PCI_VEND_ID0 0x48 /* PCI vendor ID (SysKonnect) */
890#define PCI_VEND_ID1 0x11 /* PCI vendor ID (SysKonnect) */
891 /* (High byte) */
892#define PCI_DEV_ID0 0x00 /* PCI device ID */
893#define PCI_DEV_ID1 0x40 /* PCI device ID (High byte) */
894
895/*#define PCI_CLASS 0x02*/ /* PCI class code: network device */
896#define PCI_NW_CLASS 0x02 /* PCI class code: network device */
897#define PCI_SUB_CLASS 0x02 /* PCI subclass ID: FDDI device */
898#define PCI_PROG_INTFC 0x00 /* PCI programming Interface (=0) */
899
900/*
901 * address transmission from logical to physical offset address on board
902 */
903#define FMA(a) (0x0400|((a)<<2)) /* FORMAC+ (r/w) (SN3) */
904#define P1(a) (0x0380|((a)<<2)) /* PLC1 (r/w) (DAS) */
905#define P2(a) (0x0600|((a)<<2)) /* PLC2 (r/w) (covered by the SN3) */
906#define PRA(a) (B2_MAC_0 + (a)) /* configuration PROM (MAC address) */
907
908/*
909 * FlashProm specification
910 */
911#define MAX_PAGES 0x20000L /* Every byte has a single page */
912#define MAX_FADDR 1 /* 1 byte per page */
913
914/*
915 * Receive / Transmit Buffer Control word
916 */
917#define BMU_OWN (1UL<<31) /* OWN bit: 0 == host, 1 == adapter */
918#define BMU_STF (1L<<30) /* Start of Frame ? */
919#define BMU_EOF (1L<<29) /* End of Frame ? */
920#define BMU_EN_IRQ_EOB (1L<<28) /* Enable "End of Buffer" IRQ */
921#define BMU_EN_IRQ_EOF (1L<<27) /* Enable "End of Frame" IRQ */
922#define BMU_DEV_0 (1L<<26) /* RX: don't transfer to system mem */
923#define BMU_SMT_TX (1L<<25) /* TX: if set, buffer type SMT_MBuf */
924#define BMU_ST_BUF (1L<<25) /* RX: copy of start of frame */
925#define BMU_UNUSED (1L<<24) /* Set if the Descr is curr unused */
926#define BMU_SW (3L<<24) /* 2 Bits reserved for SW usage */
927#define BMU_CHECK 0x00550000L /* To identify the control word */
928#define BMU_BBC 0x0000FFFFL /* R/T Buffer Byte Count */
929
930/*
931 * physical address offset + IO-Port base address
932 */
933#ifdef MEM_MAPPED_IO
934#define ADDR(a) (char far *) smc->hw.iop+(a)
935#define ADDRS(smc,a) (char far *) (smc)->hw.iop+(a)
936#else
937#define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), \
938 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
939 (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
940#define ADDRS(smc,a) (((a)>>7) ? (outp((smc)->hw.iop+B0_RAP,(a)>>7), \
941 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0)))) : \
942 ((smc)->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
943#endif
944
945/*
946 * Define a macro to access the configuration space
947 */
948#define PCI_C(a) ADDR(B3_CFG_SPC + (a)) /* PCI Config Space */
949
950#define EXT_R(a) ADDR(B6_EXT_REG + (a)) /* External Registers */
951
952/*
953 * Define some values needed for the MAC address (PROM)
954 */
955#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
956#define PRA_OFF (0) /* offset correction when 4th byte reading */
957
958#define SKFDDI_PSZ 8 /* address PROM size */
959
960#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */
961#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */
962#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */
963#define PR_A(a) ADDR(PRA(a)) /* config. PROM (MAC address) */
964
965/*
966 * Macro to read the PROM
967 */
968#define READ_PROM(a) ((u_char)inp(a))
969
970#define GET_PAGE(bank) outpd(ADDR(B2_FAR),bank)
971#define VPP_ON()
972#define VPP_OFF()
973
974/*
975 * Note: Values of the Interrupt Source Register are defined above
976 */
977#define ISR_A ADDR(B0_ISRC)
978#define GET_ISR() inpd(ISR_A)
979#define GET_ISR_SMP(iop) inpd((iop)+B0_ISRC)
980#define CHECK_ISR() (inpd(ISR_A) & inpd(ADDR(B0_IMSK)))
981#define CHECK_ISR_SMP(iop) (inpd((iop)+B0_ISRC) & inpd((iop)+B0_IMSK))
982
983#define BUS_CHECK()
984
985/*
986 * CLI_FBI: Disable Board Interrupts
987 * STI_FBI: Enable Board Interrupts
988 */
989#ifndef UNIX
990#define CLI_FBI() outpd(ADDR(B0_IMSK),0)
991#else
992#define CLI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),0)
993#endif
994
995#ifndef UNIX
996#define STI_FBI() outpd(ADDR(B0_IMSK),smc->hw.is_imask)
997#else
998#define STI_FBI(smc) outpd(ADDRS((smc),B0_IMSK),(smc)->hw.is_imask)
999#endif
1000
1001#define CLI_FBI_SMP(iop) outpd((iop)+B0_IMSK,0)
1002#define STI_FBI_SMP(smc,iop) outpd((iop)+B0_IMSK,(smc)->hw.is_imask)
1003
1004#endif /* PCI */
1005/*--------------------------------------------------------------------------*/
1006
1007/*
1008 * 12 bit transfer (dword) counter:
1009 * (ISA: 2*trc = number of byte)
1010 * (EISA: 4*trc = number of byte)
1011 * (MCA: 4*trc = number of byte)
1012 */
1013#define MAX_TRANS (0x0fff)
1014
1015/*
1016 * PC PIC
1017 */
1018#define MST_8259 (0x20)
1019#define SLV_8259 (0xA0)
1020
1021#define TPS (18) /* ticks per second */
1022
1023/*
1024 * error timer defs
1025 */
1026#define TN (4) /* number of supported timer = TN+1 */
1027#define SNPPND_TIME (5) /* buffer memory access over mem. data reg. */
1028
1029#define MAC_AD 0x405a0000
1030
1031#define MODR1 FM_A(FM_MDREG1) /* mode register 1 */
1032#define MODR2 FM_A(FM_MDREG2) /* mode register 2 */
1033
1034#define CMDR1 FM_A(FM_CMDREG1) /* command register 1 */
1035#define CMDR2 FM_A(FM_CMDREG2) /* command register 2 */
1036
1037
1038/*
1039 * function defines
1040 */
1041#define CLEAR(io,mask) outpw((io),inpw(io)&(~(mask)))
1042#define SET(io,mask) outpw((io),inpw(io)|(mask))
1043#define GET(io,mask) (inpw(io)&(mask))
1044#define SETMASK(io,val,mask) outpw((io),(inpw(io) & ~(mask)) | (val))
1045
1046/*
1047 * PHY Port A (PA) = PLC 1
1048 * With SuperNet 3 PHY-A and PHY S are identical.
1049 */
1050#define PLC(np,reg) (((np) == PA) ? P2_A(reg) : P1_A(reg))
1051
1052/*
1053 * set memory address register for write and read
1054 */
1055#define MARW(ma) outpw(FM_A(FM_MARW),(unsigned int)(ma))
1056#define MARR(ma) outpw(FM_A(FM_MARR),(unsigned int)(ma))
1057
1058/*
1059 * read/write from/to memory data register
1060 */
1061/* write double word */
1062#define MDRW(dd) outpw(FM_A(FM_MDRU),(unsigned int)((dd)>>16)) ;\
1063 outpw(FM_A(FM_MDRL),(unsigned int)(dd))
1064
1065#ifndef WINNT
1066/* read double word */
1067#define MDRR() (((long)inpw(FM_A(FM_MDRU))<<16) + inpw(FM_A(FM_MDRL)))
1068
1069/* read FORMAC+ 32-bit status register */
1070#define GET_ST1() (((long)inpw(FM_A(FM_ST1U))<<16) + inpw(FM_A(FM_ST1L)))
1071#define GET_ST2() (((long)inpw(FM_A(FM_ST2U))<<16) + inpw(FM_A(FM_ST2L)))
1072#ifdef SUPERNET_3
1073#define GET_ST3() (((long)inpw(FM_A(FM_ST3U))<<16) + inpw(FM_A(FM_ST3L)))
1074#endif
1075#else
1076/* read double word */
1077#define MDRR() inp2w((FM_A(FM_MDRU)),(FM_A(FM_MDRL)))
1078
1079/* read FORMAC+ 32-bit status register */
1080#define GET_ST1() inp2w((FM_A(FM_ST1U)),(FM_A(FM_ST1L)))
1081#define GET_ST2() inp2w((FM_A(FM_ST2U)),(FM_A(FM_ST2L)))
1082#ifdef SUPERNET_3
1083#define GET_ST3() inp2w((FM_A(FM_ST3U)),(FM_A(FM_ST3L)))
1084#endif
1085#endif
1086
1087/* Special timer macro for 82c54 */
1088 /* timer access over data bus bit 8..15 */
1089#define OUT_82c54_TIMER(port,val) outpw(TI_A(port),(val)<<8)
1090#define IN_82c54_TIMER(port) ((inpw(TI_A(port))>>8) & 0xff)
1091
1092
1093#ifdef DEBUG
1094#define DB_MAC(mac,st) {if (debug_mac & 0x1)\
1095 printf("M") ;\
1096 if (debug_mac & 0x2)\
1097 printf("\tMAC %d status 0x%08lx\n",mac,st) ;\
1098 if (debug_mac & 0x4)\
1099 dp_mac(mac,st) ;\
1100}
1101
1102#define DB_PLC(p,iev) { if (debug_plc & 0x1)\
1103 printf("P") ;\
1104 if (debug_plc & 0x2)\
1105 printf("\tPLC %s Int 0x%04x\n", \
1106 (p == PA) ? "A" : "B", iev) ;\
1107 if (debug_plc & 0x4)\
1108 dp_plc(p,iev) ;\
1109}
1110
1111#define DB_TIMER() { if (debug_timer & 0x1)\
1112 printf("T") ;\
1113 if (debug_timer & 0x2)\
1114 printf("\tTimer ISR\n") ;\
1115}
1116
1117#else /* no DEBUG */
1118
1119#define DB_MAC(mac,st)
1120#define DB_PLC(p,iev)
1121#define DB_TIMER()
1122
1123#endif /* no DEBUG */
1124
1125#define INC_PTR(sp,cp,ep) if (++cp == ep) cp = sp
1126/*
1127 * timer defs
1128 */
1129#define COUNT(t) ((t)<<6) /* counter */
1130#define RW_OP(o) ((o)<<4) /* read/write operation */
1131#define TMODE(m) ((m)<<1) /* timer mode */
1132
1133#endif
diff --git a/drivers/net/skfp/h/skfbiinc.h b/drivers/net/skfp/h/skfbiinc.h
deleted file mode 100644
index ac2d7192f1ca..000000000000
--- a/drivers/net/skfp/h/skfbiinc.h
+++ /dev/null
@@ -1,97 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _SKFBIINC_
16#define _SKFBIINC_
17
18#include "h/supern_2.h"
19
20/*
21 * special defines for use into .asm files
22 */
23#define ERR_FLAGS (FS_MSRABT | FS_SEAC2 | FS_SFRMERR | FS_SFRMTY1)
24
25#ifdef PCI
26#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
27 IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
28 IS_R1_C | IS_XA_C | IS_XS_C)
29#endif
30
31#ifdef PCI
32#define ISR_MASK (IS_MINTR1 | IS_R1_F | IS_XS_F| IS_XA_F | IMASK_FAST)
33#else
34#define ISR_MASK (IS_MINTR1 | IS_MINTR2 | IMASK_FAST)
35#endif
36
37#define FMA_FM_CMDREG1 FMA(FM_CMDREG1)
38#define FMA_FM_CMDREG2 FMA(FM_CMDREG2)
39#define FMA_FM_STMCHN FMA(FM_STMCHN)
40#define FMA_FM_RPR FMA(FM_RPR)
41#define FMA_FM_WPXA0 FMA(FM_WPXA0)
42#define FMA_FM_WPXA2 FMA(FM_WPXA2)
43#define FMA_FM_MARR FMA(FM_MARR)
44#define FMA_FM_MARW FMA(FM_MARW)
45#define FMA_FM_MDRU FMA(FM_MDRU)
46#define FMA_FM_MDRL FMA(FM_MDRL)
47#define FMA_ST1L FMA(FM_ST1L)
48#define FMA_ST1U FMA(FM_ST1U)
49#define FMA_ST2L FMA(FM_ST2L)
50#define FMA_ST2U FMA(FM_ST2U)
51#ifdef SUPERNET_3
52#define FMA_ST3L FMA(FM_ST3L)
53#define FMA_ST3U FMA(FM_ST3U)
54#endif
55
56#define TMODE_RRQ RQ_RRQ
57#define TMODE_WAQ2 RQ_WA2
58#define HSRA HSR(0)
59
60
61#define FMA_FM_ST1L FMA_ST1L
62#define FMA_FM_ST1U FMA_ST1U
63#define FMA_FM_ST2L FMA_ST2L
64#define FMA_FM_ST2U FMA_ST2U
65#ifdef SUPERNET_3
66#define FMA_FM_ST3L FMA_ST3L
67#define FMA_FM_ST3U FMA_ST3U
68#endif
69
70#define FMA_FM_SWPR FMA(FM_SWPR)
71
72#define FMA_FM_RPXA0 FMA(FM_RPXA0)
73
74#define FMA_FM_RPXS FMA(FM_RPXS)
75#define FMA_FM_WPXS FMA(FM_WPXS)
76
77#define FMA_FM_IMSK1U FMA(FM_IMSK1U)
78#define FMA_FM_IMSK1L FMA(FM_IMSK1L)
79
80#define FMA_FM_EAS FMA(FM_EAS)
81#define FMA_FM_EAA0 FMA(FM_EAA0)
82
83#define TMODE_WAQ0 RQ_WA0
84#define TMODE_WSQ RQ_WSQ
85
86/* Define default for DRV_PCM_STATE_CHANGE */
87#ifndef DRV_PCM_STATE_CHANGE
88#define DRV_PCM_STATE_CHANGE(smc,plc,p_state) /* nothing */
89#endif
90
91/* Define default for DRV_RMT_INDICATION */
92#ifndef DRV_RMT_INDICATION
93#define DRV_RMT_INDICATION(smc,i) /* nothing */
94#endif
95
96#endif /* n_SKFBIINC_ */
97
diff --git a/drivers/net/skfp/h/smc.h b/drivers/net/skfp/h/smc.h
deleted file mode 100644
index c774a95902f5..000000000000
--- a/drivers/net/skfp/h/smc.h
+++ /dev/null
@@ -1,488 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _SCMECM_
16#define _SCMECM_
17
18#if defined(PCI) && !defined(OSDEF)
19/*
20 * In the case of the PCI bus the file osdef1st.h must be present
21 */
22#define OSDEF
23#endif
24
25#ifdef PCI
26#ifndef SUPERNET_3
27#define SUPERNET_3
28#endif
29#ifndef TAG_MODE
30#define TAG_MODE
31#endif
32#endif
33
34/*
35 * include all other files in required order
36 * the following files must have been included before:
37 * types.h
38 * fddi.h
39 */
40#ifdef OSDEF
41#include "h/osdef1st.h"
42#endif /* OSDEF */
43#ifdef OEM_CONCEPT
44#include "oemdef.h"
45#endif /* OEM_CONCEPT */
46#include "h/smt.h"
47#include "h/cmtdef.h"
48#include "h/fddimib.h"
49#include "h/targethw.h" /* all target hw dependencies */
50#include "h/targetos.h" /* all target os dependencies */
51#ifdef ESS
52#include "h/sba.h"
53#endif
54
55/*
56 * Event Queue
57 * queue.c
58 * events are class/value pairs
59 * class is addressee, e.g. RMT, PCM etc.
60 * value is command, e.g. line state change, ring op change etc.
61 */
62struct event_queue {
63 u_short class ; /* event class */
64 u_short event ; /* event value */
65} ;
66
67/*
68 * define event queue as circular buffer
69 */
70#ifdef CONCENTRATOR
71#define MAX_EVENT 128
72#else /* nCONCENTRATOR */
73#define MAX_EVENT 64
74#endif /* nCONCENTRATOR */
75
76struct s_queue {
77
78 struct event_queue ev_queue[MAX_EVENT];
79 struct event_queue *ev_put ;
80 struct event_queue *ev_get ;
81} ;
82
83/*
84 * ECM - Entity Coordination Management
85 * ecm.c
86 */
87struct s_ecm {
88 u_char path_test ; /* ECM path test variable */
89 u_char sb_flag ; /* ECM stuck bypass */
90 u_char DisconnectFlag ; /* jd 05-Aug-1999 Bug #10419
91 * ECM disconnected */
92 u_char ecm_line_state ; /* flag to dispatcher : line states */
93 u_long trace_prop ; /* ECM Trace_Prop flag >= 16 bits !! */
94 /* NUMPHYS note:
95 * this variable must have enough bits to hold all entiies in
96 * the station. So NUMPHYS may not be greater than 31.
97 */
98 char ec_pad[2] ;
99 struct smt_timer ecm_timer ; /* timer */
100} ;
101
102
103/*
104 * RMT - Ring Management
105 * rmt.c
106 */
107struct s_rmt {
108 u_char dup_addr_test ; /* state of dupl. addr. test */
109 u_char da_flag ; /* flag : duplicate address det. */
110 u_char loop_avail ; /* flag : MAC available for loopback */
111 u_char sm_ma_avail ; /* flag : MAC available for SMT */
112 u_char no_flag ; /* flag : ring not operational */
113 u_char bn_flag ; /* flag : MAC reached beacon state */
114 u_char jm_flag ; /* flag : jamming in NON_OP_DUP */
115 u_char rm_join ; /* CFM flag RM_Join */
116 u_char rm_loop ; /* CFM flag RM_Loop */
117
118 long fast_rm_join ; /* bit mask of active ports */
119 /*
120 * timer and flags
121 */
122 struct smt_timer rmt_timer0 ; /* timer 0 */
123 struct smt_timer rmt_timer1 ; /* timer 1 */
124 struct smt_timer rmt_timer2 ; /* timer 2 */
125 u_char timer0_exp ; /* flag : timer 0 expired */
126 u_char timer1_exp ; /* flag : timer 1 expired */
127 u_char timer2_exp ; /* flag : timer 2 expired */
128
129 u_char rm_pad1[1] ;
130} ;
131
132/*
133 * CFM - Configuration Management
134 * cfm.c
135 * used for SAS and DAS
136 */
137struct s_cfm {
138 u_char cf_state; /* CFM state machine current state */
139 u_char cf_pad[3] ;
140} ;
141
142/*
143 * CEM - Configuration Element Management
144 * cem.c
145 * used for Concentrator
146 */
147#ifdef CONCENTRATOR
148struct s_cem {
149 int ce_state ; /* CEM state */
150 int ce_port ; /* PA PB PM PM+1 .. */
151 int ce_type ; /* TA TB TS TM */
152} ;
153
154/*
155 * linked list of CCEs in current token path
156 */
157struct s_c_ring {
158 struct s_c_ring *c_next ;
159 char c_entity ;
160} ;
161
162struct mib_path_config {
163 u_long fddimibPATHConfigSMTIndex;
164 u_long fddimibPATHConfigPATHIndex;
165 u_long fddimibPATHConfigTokenOrder;
166 u_long fddimibPATHConfigResourceType;
167#define SNMP_RES_TYPE_MAC 2 /* Resource is a MAC */
168#define SNMP_RES_TYPE_PORT 4 /* Resource is a PORT */
169 u_long fddimibPATHConfigResourceIndex;
170 u_long fddimibPATHConfigCurrentPath;
171#define SNMP_PATH_ISOLATED 1 /* Current path is isolated */
172#define SNMP_PATH_LOCAL 2 /* Current path is local */
173#define SNMP_PATH_SECONDARY 3 /* Current path is secondary */
174#define SNMP_PATH_PRIMARY 4 /* Current path is primary */
175#define SNMP_PATH_CONCATENATED 5 /* Current path is concatenated */
176#define SNMP_PATH_THRU 6 /* Current path is thru */
177};
178
179
180#endif
181
182/*
183 * PCM connect states
184 */
185#define PCM_DISABLED 0
186#define PCM_CONNECTING 1
187#define PCM_STANDBY 2
188#define PCM_ACTIVE 3
189
190struct s_pcm {
191 u_char pcm_pad[3] ;
192} ;
193
194/*
195 * PHY struct
196 * one per physical port
197 */
198struct s_phy {
199 /* Inter Module Globals */
200 struct fddi_mib_p *mib ;
201
202 u_char np ; /* index 0 .. NUMPHYS */
203 u_char cf_join ;
204 u_char cf_loop ;
205 u_char wc_flag ; /* withhold connection flag */
206 u_char pc_mode ; /* Holds the negotiated mode of the PCM */
207 u_char pc_lem_fail ; /* flag : LCT failed */
208 u_char lc_test ;
209 u_char scrub ; /* CFM flag Scrub -> PCM */
210 char phy_name ;
211 u_char pmd_type[2] ; /* SK connector/transceiver type codes */
212#define PMD_SK_CONN 0 /* pmd_type[PMD_SK_CONN] = Connector */
213#define PMD_SK_PMD 1 /* pmd_type[PMD_SK_PMD] = Xver */
214 u_char pmd_scramble ; /* scrambler on/off */
215
216 /* inner Module Globals */
217 u_char curr_ls ; /* current line state */
218 u_char ls_flag ;
219 u_char rc_flag ;
220 u_char tc_flag ;
221 u_char td_flag ;
222 u_char bitn ;
223 u_char tr_flag ; /* trace recvd while in active */
224 u_char twisted ; /* flag to indicate an A-A or B-B connection */
225 u_char t_val[NUMBITS] ; /* transmit bits for signaling */
226 u_char r_val[NUMBITS] ; /* receive bits for signaling */
227 u_long t_next[NUMBITS] ;
228 struct smt_timer pcm_timer0 ;
229 struct smt_timer pcm_timer1 ;
230 struct smt_timer pcm_timer2 ;
231 u_char timer0_exp ;
232 u_char timer1_exp ;
233 u_char timer2_exp ;
234 u_char pcm_pad1[1] ;
235 int cem_pst ; /* CEM privae state; used for dual homing */
236 struct lem_counter lem ;
237#ifdef AMDPLC
238 struct s_plc plc ;
239#endif
240} ;
241
242/*
243 * timer package
244 * smttimer.c
245 */
246struct s_timer {
247 struct smt_timer *st_queue ;
248 struct smt_timer st_fast ;
249} ;
250
251/*
252 * SRF types and data
253 */
254#define SMT_EVENT_BASE 1
255#define SMT_EVENT_MAC_PATH_CHANGE (SMT_EVENT_BASE+0)
256#define SMT_EVENT_MAC_NEIGHBOR_CHANGE (SMT_EVENT_BASE+1)
257#define SMT_EVENT_PORT_PATH_CHANGE (SMT_EVENT_BASE+2)
258#define SMT_EVENT_PORT_CONNECTION (SMT_EVENT_BASE+3)
259
260#define SMT_IS_CONDITION(x) ((x)>=SMT_COND_BASE)
261
262#define SMT_COND_BASE (SMT_EVENT_PORT_CONNECTION+1)
263#define SMT_COND_SMT_PEER_WRAP (SMT_COND_BASE+0)
264#define SMT_COND_SMT_HOLD (SMT_COND_BASE+1)
265#define SMT_COND_MAC_FRAME_ERROR (SMT_COND_BASE+2)
266#define SMT_COND_MAC_DUP_ADDR (SMT_COND_BASE+3)
267#define SMT_COND_MAC_NOT_COPIED (SMT_COND_BASE+4)
268#define SMT_COND_PORT_EB_ERROR (SMT_COND_BASE+5)
269#define SMT_COND_PORT_LER (SMT_COND_BASE+6)
270
271#define SR0_WAIT 0
272#define SR1_HOLDOFF 1
273#define SR2_DISABLED 2
274
275struct s_srf {
276 u_long SRThreshold ; /* threshold value */
277 u_char RT_Flag ; /* report transmitted flag */
278 u_char sr_state ; /* state-machine */
279 u_char any_report ; /* any report required */
280 u_long TSR ; /* timer */
281 u_short ring_status ; /* IBM ring status */
282} ;
283
284/*
285 * IBM token ring status
286 */
287#define RS_RES15 (1<<15) /* reserved */
288#define RS_HARDERROR (1<<14) /* ring down */
289#define RS_SOFTERROR (1<<13) /* sent SRF */
290#define RS_BEACON (1<<12) /* transmitted beacon */
291#define RS_PATHTEST (1<<11) /* path test failed */
292#define RS_SELFTEST (1<<10) /* selftest required */
293#define RS_RES9 (1<< 9) /* reserved */
294#define RS_DISCONNECT (1<< 8) /* remote disconnect */
295#define RS_RES7 (1<< 7) /* reserved */
296#define RS_DUPADDR (1<< 6) /* duplicate address */
297#define RS_NORINGOP (1<< 5) /* no ring op */
298#define RS_VERSION (1<< 4) /* SMT version mismatch */
299#define RS_STUCKBYPASSS (1<< 3) /* stuck bypass */
300#define RS_EVENT (1<< 2) /* FDDI event occurred */
301#define RS_RINGOPCHANGE (1<< 1) /* ring op changed */
302#define RS_RES0 (1<< 0) /* reserved */
303
304#define RS_SET(smc,bit) \
305 ring_status_indication(smc,smc->srf.ring_status |= bit)
306#define RS_CLEAR(smc,bit) \
307 ring_status_indication(smc,smc->srf.ring_status &= ~bit)
308
309#define RS_CLEAR_EVENT (0xffff & ~(RS_NORINGOP))
310
311/* Define the AIX-event-Notification as null function if it isn't defined */
312/* in the targetos.h file */
313#ifndef AIX_EVENT
314#define AIX_EVENT(smc,opt0,opt1,opt2,opt3) /* nothing */
315#endif
316
317struct s_srf_evc {
318 u_char evc_code ; /* event code type */
319 u_char evc_index ; /* index for mult. instances */
320 u_char evc_rep_required ; /* report required */
321 u_short evc_para ; /* SMT Para Number */
322 u_char *evc_cond_state ; /* condition state */
323 u_char *evc_multiple ; /* multiple occurrence */
324} ;
325
326/*
327 * Values used by frame based services
328 * smt.c
329 */
330#define SMT_MAX_TEST 5
331#define SMT_TID_NIF 0 /* pending NIF request */
332#define SMT_TID_NIF_TEST 1 /* pending NIF test */
333#define SMT_TID_ECF_UNA 2 /* pending ECF UNA test */
334#define SMT_TID_ECF_DNA 3 /* pending ECF DNA test */
335#define SMT_TID_ECF 4 /* pending ECF test */
336
337struct smt_values {
338 u_long smt_tvu ; /* timer valid una */
339 u_long smt_tvd ; /* timer valid dna */
340 u_long smt_tid ; /* transaction id */
341 u_long pend[SMT_MAX_TEST] ; /* TID of requests */
342 u_long uniq_time ; /* unique time stamp */
343 u_short uniq_ticks ; /* unique time stamp */
344 u_short please_reconnect ; /* flag : reconnect */
345 u_long smt_last_lem ;
346 u_long smt_last_notify ;
347 struct smt_timer smt_timer ; /* SMT NIF timer */
348 u_long last_tok_time[NUMMACS]; /* token cnt emulation */
349} ;
350
351/*
352 * SMT/CMT configurable parameters
353 */
354#define SMT_DAS 0 /* dual attach */
355#define SMT_SAS 1 /* single attach */
356#define SMT_NAC 2 /* null attach concentrator */
357
358struct smt_config {
359 u_char attach_s ; /* CFM attach to secondary path */
360 u_char sas ; /* SMT_DAS/SAS/NAC */
361 u_char build_ring_map ; /* build ringmap if TRUE */
362 u_char numphys ; /* number of active phys */
363 u_char sc_pad[1] ;
364
365 u_long pcm_tb_min ; /* PCM : TB_Min timer value */
366 u_long pcm_tb_max ; /* PCM : TB_Max timer value */
367 u_long pcm_c_min ; /* PCM : C_Min timer value */
368 u_long pcm_t_out ; /* PCM : T_Out timer value */
369 u_long pcm_tl_min ; /* PCM : TL_min timer value */
370 u_long pcm_lc_short ; /* PCM : LC_Short timer value */
371 u_long pcm_lc_medium ; /* PCM : LC_Medium timer value */
372 u_long pcm_lc_long ; /* PCM : LC_Long timer value */
373 u_long pcm_lc_extended ; /* PCM : LC_Extended timer value */
374 u_long pcm_t_next_9 ; /* PCM : T_Next[9] timer value */
375 u_long pcm_ns_max ; /* PCM : NS_Max timer value */
376
377 u_long ecm_i_max ; /* ECM : I_Max timer value */
378 u_long ecm_in_max ; /* ECM : IN_Max timer value */
379 u_long ecm_td_min ; /* ECM : TD_Min timer */
380 u_long ecm_test_done ; /* ECM : path test done timer */
381 u_long ecm_check_poll ; /* ECM : check bypass poller */
382
383 u_long rmt_t_non_op ; /* RMT : T_Non_OP timer value */
384 u_long rmt_t_stuck ; /* RMT : T_Stuck timer value */
385 u_long rmt_t_direct ; /* RMT : T_Direct timer value */
386 u_long rmt_t_jam ; /* RMT : T_Jam timer value */
387 u_long rmt_t_announce ; /* RMT : T_Announce timer value */
388 u_long rmt_t_poll ; /* RMT : claim/beacon poller */
389 u_long rmt_dup_mac_behavior ; /* Flag for the beavior of SMT if
390 * a Duplicate MAC Address was detected.
391 * FALSE: SMT will leave finally the ring
392 * TRUE: SMT will reinstert into the ring
393 */
394 u_long mac_d_max ; /* MAC : D_Max timer value */
395
396 u_long lct_short ; /* LCT : error threshold */
397 u_long lct_medium ; /* LCT : error threshold */
398 u_long lct_long ; /* LCT : error threshold */
399 u_long lct_extended ; /* LCT : error threshold */
400} ;
401
402#ifdef DEBUG
403/*
404 * Debugging struct sometimes used in smc
405 */
406struct smt_debug {
407 int d_smtf ;
408 int d_smt ;
409 int d_ecm ;
410 int d_rmt ;
411 int d_cfm ;
412 int d_pcm ;
413 int d_plc ;
414#ifdef ESS
415 int d_ess ;
416#endif
417#ifdef SBA
418 int d_sba ;
419#endif
420 struct os_debug d_os; /* Include specific OS DEBUG struct */
421} ;
422
423#ifndef DEBUG_BRD
424/* all boards shall be debugged with one debug struct */
425extern struct smt_debug debug; /* Declaration of debug struct */
426#endif /* DEBUG_BRD */
427
428#endif /* DEBUG */
429
430/*
431 * the SMT Context Struct SMC
432 * this struct contains ALL global variables of SMT
433 */
434struct s_smc {
435 struct s_smt_os os ; /* os specific */
436 struct s_smt_hw hw ; /* hardware */
437
438/*
439 * NOTE: os and hw MUST BE the first two structs
440 * anything beyond hw WILL BE SET TO ZERO in smt_set_defaults()
441 */
442 struct smt_config s ; /* smt constants */
443 struct smt_values sm ; /* smt variables */
444 struct s_ecm e ; /* ecm */
445 struct s_rmt r ; /* rmt */
446 struct s_cfm cf ; /* cfm/cem */
447#ifdef CONCENTRATOR
448 struct s_cem ce[NUMPHYS] ; /* cem */
449 struct s_c_ring cr[NUMPHYS+NUMMACS] ;
450#endif
451 struct s_pcm p ; /* pcm */
452 struct s_phy y[NUMPHYS] ; /* phy */
453 struct s_queue q ; /* queue */
454 struct s_timer t ; /* timer */
455 struct s_srf srf ; /* SRF */
456 struct s_srf_evc evcs[6+NUMPHYS*4] ;
457 struct fddi_mib mib ; /* __THE_MIB__ */
458#ifdef SBA
459 struct s_sba sba ; /* SBA variables */
460#endif
461#ifdef ESS
462 struct s_ess ess ; /* Ess variables */
463#endif
464#if defined(DEBUG) && defined(DEBUG_BRD)
465 /* If you want all single board to be debugged separately */
466 struct smt_debug debug; /* Declaration of debug struct */
467#endif /* DEBUG_BRD && DEBUG */
468} ;
469
470extern const struct fddi_addr fddi_broadcast;
471
472extern void all_selection_criteria(struct s_smc *smc);
473extern void card_stop(struct s_smc *smc);
474extern void init_board(struct s_smc *smc, u_char *mac_addr);
475extern int init_fplus(struct s_smc *smc);
476extern void init_plc(struct s_smc *smc);
477extern int init_smt(struct s_smc *smc, u_char * mac_addr);
478extern void mac1_irq(struct s_smc *smc, u_short stu, u_short stl);
479extern void mac2_irq(struct s_smc *smc, u_short code_s2u, u_short code_s2l);
480extern void mac3_irq(struct s_smc *smc, u_short code_s3u, u_short code_s3l);
481extern int pcm_status_twisted(struct s_smc *smc);
482extern void plc1_irq(struct s_smc *smc);
483extern void plc2_irq(struct s_smc *smc);
484extern void read_address(struct s_smc *smc, u_char * mac_addr);
485extern void timer_irq(struct s_smc *smc);
486
487#endif /* _SCMECM_ */
488
diff --git a/drivers/net/skfp/h/smt.h b/drivers/net/skfp/h/smt.h
deleted file mode 100644
index 2030f9cbb24b..000000000000
--- a/drivers/net/skfp/h/smt.h
+++ /dev/null
@@ -1,882 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 * SMT 7.2 frame definitions
17 */
18
19#ifndef _SMT_
20#define _SMT_
21
22/* #define SMT5_10 */
23#define SMT6_10
24#define SMT7_20
25
26#define OPT_PMF /* if parameter management is supported */
27#define OPT_SRF /* if status report is supported */
28
29/*
30 * SMT frame version 5.1
31 */
32
33#define SMT_VID 0x0001 /* V 5.1 .. 6.1 */
34#define SMT_VID_2 0x0002 /* V 7.2 */
35
36struct smt_sid {
37 u_char sid_oem[2] ; /* implementation spec. */
38 struct fddi_addr sid_node ; /* node address */
39} ;
40
41typedef u_char t_station_id[8] ;
42
43/*
44 * note on alignment :
45 * sizeof(struct smt_header) = 32
46 * all parameters are long aligned
47 * if struct smt_header starts at offset 0, all longs are aligned correctly
48 * (FC starts at offset 3)
49 */
50_packed struct smt_header {
51 struct fddi_addr smt_dest ; /* destination address */
52 struct fddi_addr smt_source ; /* source address */
53 u_char smt_class ; /* NIF, SIF ... */
54 u_char smt_type ; /* req., response .. */
55 u_short smt_version ; /* version id */
56 u_int smt_tid ; /* transaction ID */
57 struct smt_sid smt_sid ; /* station ID */
58 u_short smt_pad ; /* pad with 0 */
59 u_short smt_len ; /* length of info field */
60} ;
61#define SWAP_SMTHEADER "662sl8ss"
62
63#if 0
64/*
65 * MAC FC values
66 */
67#define FC_SMT_INFO 0x41 /* SMT info */
68#define FC_SMT_NSA 0x4f /* SMT Next Station Addressing */
69#endif
70
71
72/*
73 * type codes
74 */
75#define SMT_ANNOUNCE 0x01 /* announcement */
76#define SMT_REQUEST 0x02 /* request */
77#define SMT_REPLY 0x03 /* reply */
78
79/*
80 * class codes
81 */
82#define SMT_NIF 0x01 /* neighbor information frames */
83#define SMT_SIF_CONFIG 0x02 /* station information configuration */
84#define SMT_SIF_OPER 0x03 /* station information operation */
85#define SMT_ECF 0x04 /* echo frames */
86#define SMT_RAF 0x05 /* resource allocation */
87#define SMT_RDF 0x06 /* request denied */
88#define SMT_SRF 0x07 /* status report */
89#define SMT_PMF_GET 0x08 /* parameter management get */
90#define SMT_PMF_SET 0x09 /* parameter management set */
91#define SMT_ESF 0xff /* extended service */
92
93#define SMT_MAX_ECHO_LEN 4458 /* max length of SMT Echo */
94#if defined(CONC) || defined(CONC_II)
95#define SMT_TEST_ECHO_LEN 50 /* test length of SMT Echo */
96#else
97#define SMT_TEST_ECHO_LEN SMT_MAX_ECHO_LEN /* test length */
98#endif
99
100#define SMT_MAX_INFO_LEN (4352-20) /* max length for SMT info */
101
102
103/*
104 * parameter types
105 */
106
107struct smt_para {
108 u_short p_type ; /* type */
109 u_short p_len ; /* length of parameter */
110} ;
111
112#define PARA_LEN (sizeof(struct smt_para))
113
114#define SMTSETPARA(p,t) (p)->para.p_type = (t),\
115 (p)->para.p_len = sizeof(*(p)) - PARA_LEN
116
117/*
118 * P01 : Upstream Neighbor Address, UNA
119 */
120#define SMT_P_UNA 0x0001 /* upstream neighbor address */
121#define SWAP_SMT_P_UNA "s6"
122
123struct smt_p_una {
124 struct smt_para para ; /* generic parameter header */
125 u_short una_pad ;
126 struct fddi_addr una_node ; /* node address, zero if unknown */
127} ;
128
129/*
130 * P02 : Station Descriptor
131 */
132#define SMT_P_SDE 0x0002 /* station descriptor */
133#define SWAP_SMT_P_SDE "1111"
134
135#define SMT_SDE_STATION 0 /* end node */
136#define SMT_SDE_CONCENTRATOR 1 /* concentrator */
137
138struct smt_p_sde {
139 struct smt_para para ; /* generic parameter header */
140 u_char sde_type ; /* station type */
141 u_char sde_mac_count ; /* number of MACs */
142 u_char sde_non_master ; /* number of A,B or S ports */
143 u_char sde_master ; /* number of S ports on conc. */
144} ;
145
146/*
147 * P03 : Station State
148 */
149#define SMT_P_STATE 0x0003 /* station state */
150#define SWAP_SMT_P_STATE "scc"
151
152struct smt_p_state {
153 struct smt_para para ; /* generic parameter header */
154 u_short st_pad ;
155 u_char st_topology ; /* topology */
156 u_char st_dupl_addr ; /* duplicate address detected */
157} ;
158#define SMT_ST_WRAPPED (1<<0) /* station wrapped */
159#define SMT_ST_UNATTACHED (1<<1) /* unattached concentrator */
160#define SMT_ST_TWISTED_A (1<<2) /* A-A connection, twisted ring */
161#define SMT_ST_TWISTED_B (1<<3) /* B-B connection, twisted ring */
162#define SMT_ST_ROOTED_S (1<<4) /* rooted station */
163#define SMT_ST_SRF (1<<5) /* SRF protocol supported */
164#define SMT_ST_SYNC_SERVICE (1<<6) /* use synchronous bandwidth */
165
166#define SMT_ST_MY_DUPA (1<<0) /* my station detected dupl. */
167#define SMT_ST_UNA_DUPA (1<<1) /* my UNA detected duplicate */
168
169/*
170 * P04 : timestamp
171 */
172#define SMT_P_TIMESTAMP 0x0004 /* time stamp */
173#define SWAP_SMT_P_TIMESTAMP "8"
174struct smt_p_timestamp {
175 struct smt_para para ; /* generic parameter header */
176 u_char ts_time[8] ; /* time, resolution 80nS, unique */
177} ;
178
179/*
180 * P05 : station policies
181 */
182#define SMT_P_POLICY 0x0005 /* station policies */
183#define SWAP_SMT_P_POLICY "ss"
184
185struct smt_p_policy {
186 struct smt_para para ; /* generic parameter header */
187 u_short pl_config ;
188 u_short pl_connect ; /* bit string POLICY_AA ... */
189} ;
190#define SMT_PL_HOLD 1 /* hold policy supported (Dual MAC) */
191
192/*
193 * P06 : latency equivalent
194 */
195#define SMT_P_LATENCY 0x0006 /* latency */
196#define SWAP_SMT_P_LATENCY "ssss"
197
198/*
199 * note: latency has two phy entries by definition
200 * for a SAS, the 2nd one is null
201 */
202struct smt_p_latency {
203 struct smt_para para ; /* generic parameter header */
204 u_short lt_phyout_idx1 ; /* index */
205 u_short lt_latency1 ; /* latency , unit : byte clock */
206 u_short lt_phyout_idx2 ; /* 0 if SAS */
207 u_short lt_latency2 ; /* 0 if SAS */
208} ;
209
210/*
211 * P07 : MAC neighbors
212 */
213#define SMT_P_NEIGHBORS 0x0007 /* MAC neighbor description */
214#define SWAP_SMT_P_NEIGHBORS "ss66"
215
216struct smt_p_neighbor {
217 struct smt_para para ; /* generic parameter header */
218 u_short nb_mib_index ; /* MIB index */
219 u_short nb_mac_index ; /* n+1 .. n+m, m = #MACs, n = #PHYs */
220 struct fddi_addr nb_una ; /* UNA , 0 for unknown */
221 struct fddi_addr nb_dna ; /* DNA , 0 for unknown */
222} ;
223
224/*
225 * PHY record
226 */
227#define SMT_PHY_A 0 /* A port */
228#define SMT_PHY_B 1 /* B port */
229#define SMT_PHY_S 2 /* slave port */
230#define SMT_PHY_M 3 /* master port */
231
232#define SMT_CS_DISABLED 0 /* connect state : disabled */
233#define SMT_CS_CONNECTING 1 /* connect state : connecting */
234#define SMT_CS_STANDBY 2 /* connect state : stand by */
235#define SMT_CS_ACTIVE 3 /* connect state : active */
236
237#define SMT_RM_NONE 0
238#define SMT_RM_MAC 1
239
240struct smt_phy_rec {
241 u_short phy_mib_index ; /* MIB index */
242 u_char phy_type ; /* A/B/S/M */
243 u_char phy_connect_state ; /* disabled/connecting/active */
244 u_char phy_remote_type ; /* A/B/S/M */
245 u_char phy_remote_mac ; /* none/remote */
246 u_short phy_resource_idx ; /* 1 .. n */
247} ;
248
249/*
250 * MAC record
251 */
252struct smt_mac_rec {
253 struct fddi_addr mac_addr ; /* MAC address */
254 u_short mac_resource_idx ; /* n+1 .. n+m */
255} ;
256
257/*
258 * P08 : path descriptors
259 * should be really an array ; however our environment has a fixed number of
260 * PHYs and MACs
261 */
262#define SMT_P_PATH 0x0008 /* path descriptor */
263#define SWAP_SMT_P_PATH "[6s]"
264
265struct smt_p_path {
266 struct smt_para para ; /* generic parameter header */
267 struct smt_phy_rec pd_phy[2] ; /* PHY A */
268 struct smt_mac_rec pd_mac ; /* MAC record */
269} ;
270
271/*
272 * P09 : MAC status
273 */
274#define SMT_P_MAC_STATUS 0x0009 /* MAC status */
275#define SWAP_SMT_P_MAC_STATUS "sslllllllll"
276
277struct smt_p_mac_status {
278 struct smt_para para ; /* generic parameter header */
279 u_short st_mib_index ; /* MIB index */
280 u_short st_mac_index ; /* n+1 .. n+m */
281 u_int st_t_req ; /* T_Req */
282 u_int st_t_neg ; /* T_Neg */
283 u_int st_t_max ; /* T_Max */
284 u_int st_tvx_value ; /* TVX_Value */
285 u_int st_t_min ; /* T_Min */
286 u_int st_sba ; /* synchr. bandwidth alloc */
287 u_int st_frame_ct ; /* frame counter */
288 u_int st_error_ct ; /* error counter */
289 u_int st_lost_ct ; /* lost frames counter */
290} ;
291
292/*
293 * P0A : PHY link error rate monitoring
294 */
295#define SMT_P_LEM 0x000a /* link error monitor */
296#define SWAP_SMT_P_LEM "ssccccll"
297/*
298 * units of lem_cutoff,lem_alarm,lem_estimate : 10**-x
299 */
300struct smt_p_lem {
301 struct smt_para para ; /* generic parameter header */
302 u_short lem_mib_index ; /* MIB index */
303 u_short lem_phy_index ; /* 1 .. n */
304 u_char lem_pad2 ; /* be nice and make it even . */
305 u_char lem_cutoff ; /* 0x4 .. 0xf, default 0x7 */
306 u_char lem_alarm ; /* 0x4 .. 0xf, default 0x8 */
307 u_char lem_estimate ; /* 0x0 .. 0xff */
308 u_int lem_reject_ct ; /* 0x00000000 .. 0xffffffff */
309 u_int lem_ct ; /* 0x00000000 .. 0xffffffff */
310} ;
311
312/*
313 * P0B : MAC frame counters
314 */
315#define SMT_P_MAC_COUNTER 0x000b /* MAC frame counters */
316#define SWAP_SMT_P_MAC_COUNTER "ssll"
317
318struct smt_p_mac_counter {
319 struct smt_para para ; /* generic parameter header */
320 u_short mc_mib_index ; /* MIB index */
321 u_short mc_index ; /* mac index */
322 u_int mc_receive_ct ; /* receive counter */
323 u_int mc_transmit_ct ; /* transmit counter */
324} ;
325
326/*
327 * P0C : MAC frame not copied counter
328 */
329#define SMT_P_MAC_FNC 0x000c /* MAC frame not copied counter */
330#define SWAP_SMT_P_MAC_FNC "ssl"
331
332struct smt_p_mac_fnc {
333 struct smt_para para ; /* generic parameter header */
334 u_short nc_mib_index ; /* MIB index */
335 u_short nc_index ; /* mac index */
336 u_int nc_counter ; /* not copied counter */
337} ;
338
339
340/*
341 * P0D : MAC priority values
342 */
343#define SMT_P_PRIORITY 0x000d /* MAC priority values */
344#define SWAP_SMT_P_PRIORITY "ssl"
345
346struct smt_p_priority {
347 struct smt_para para ; /* generic parameter header */
348 u_short pr_mib_index ; /* MIB index */
349 u_short pr_index ; /* mac index */
350 u_int pr_priority[7] ; /* priority values */
351} ;
352
353/*
354 * P0E : PHY elasticity buffer status
355 */
356#define SMT_P_EB 0x000e /* PHY EB status */
357#define SWAP_SMT_P_EB "ssl"
358
359struct smt_p_eb {
360 struct smt_para para ; /* generic parameter header */
361 u_short eb_mib_index ; /* MIB index */
362 u_short eb_index ; /* phy index */
363 u_int eb_error_ct ; /* # of eb overflows */
364} ;
365
366/*
367 * P0F : manufacturer field
368 */
369#define SMT_P_MANUFACTURER 0x000f /* manufacturer field */
370#define SWAP_SMT_P_MANUFACTURER ""
371
372struct smp_p_manufacturer {
373 struct smt_para para ; /* generic parameter header */
374 u_char mf_data[32] ; /* OUI + arbitrary data */
375} ;
376
377/*
378 * P10 : user field
379 */
380#define SMT_P_USER 0x0010 /* manufacturer field */
381#define SWAP_SMT_P_USER ""
382
383struct smp_p_user {
384 struct smt_para para ; /* generic parameter header */
385 u_char us_data[32] ; /* arbitrary data */
386} ;
387
388
389
390/*
391 * P11 : echo data
392 */
393#define SMT_P_ECHODATA 0x0011 /* echo data */
394#define SWAP_SMT_P_ECHODATA ""
395
396struct smt_p_echo {
397 struct smt_para para ; /* generic parameter header */
398 u_char ec_data[SMT_MAX_ECHO_LEN-4] ; /* echo data */
399} ;
400
401/*
402 * P12 : reason code
403 */
404#define SMT_P_REASON 0x0012 /* reason code */
405#define SWAP_SMT_P_REASON "l"
406
407struct smt_p_reason {
408 struct smt_para para ; /* generic parameter header */
409 u_int rdf_reason ; /* CLASS/VERSION */
410} ;
411#define SMT_RDF_CLASS 0x00000001 /* class not supported */
412#define SMT_RDF_VERSION 0x00000002 /* version not supported */
413#define SMT_RDF_SUCCESS 0x00000003 /* success (PMF) */
414#define SMT_RDF_BADSET 0x00000004 /* bad set count (PMF) */
415#define SMT_RDF_ILLEGAL 0x00000005 /* read only (PMF) */
416#define SMT_RDF_NOPARAM 0x6 /* parameter not supported (PMF) */
417#define SMT_RDF_RANGE 0x8 /* out of range */
418#define SMT_RDF_AUTHOR 0x9 /* not autohorized */
419#define SMT_RDF_LENGTH 0x0a /* length error */
420#define SMT_RDF_TOOLONG 0x0b /* length error */
421#define SMT_RDF_SBA 0x0d /* SBA denied */
422
423/*
424 * P13 : refused frame beginning
425 */
426#define SMT_P_REFUSED 0x0013 /* refused frame beginning */
427#define SWAP_SMT_P_REFUSED "l"
428
429struct smt_p_refused {
430 struct smt_para para ; /* generic parameter header */
431 u_int ref_fc ; /* 3 bytes 0 + FC */
432 struct smt_header ref_header ; /* refused header */
433} ;
434
435/*
436 * P14 : supported SMT versions
437 */
438#define SMT_P_VERSION 0x0014 /* SMT supported versions */
439#define SWAP_SMT_P_VERSION "sccss"
440
441struct smt_p_version {
442 struct smt_para para ; /* generic parameter header */
443 u_short v_pad ;
444 u_char v_n ; /* 1 .. 0xff, #versions */
445 u_char v_index ; /* 1 .. 0xff, index of op. v. */
446 u_short v_version[1] ; /* list of min. 1 version */
447 u_short v_pad2 ; /* pad if necessary */
448} ;
449
450/*
451 * P15 : Resource Type
452 */
453#define SWAP_SMT_P0015 "l"
454
455struct smt_p_0015 {
456 struct smt_para para ; /* generic parameter header */
457 u_int res_type ; /* recsource type */
458} ;
459
460#define SYNC_BW 0x00000001L /* Synchronous Bandwidth */
461
462/*
463 * P16 : SBA Command
464 */
465#define SWAP_SMT_P0016 "l"
466
467struct smt_p_0016 {
468 struct smt_para para ; /* generic parameter header */
469 u_int sba_cmd ; /* command for the SBA */
470} ;
471
472#define REQUEST_ALLOCATION 0x1 /* req allocation of sync bandwidth */
473#define REPORT_ALLOCATION 0x2 /* rep of sync bandwidth allocation */
474#define CHANGE_ALLOCATION 0x3 /* forces a station using sync band-*/
475 /* width to change its current allo-*/
476 /* cation */
477
478/*
479 * P17 : SBA Payload Request
480 */
481#define SWAP_SMT_P0017 "l"
482
483struct smt_p_0017 {
484 struct smt_para para ; /* generic parameter header */
485 int sba_pl_req ; /* total sync bandwidth measured in */
486} ; /* bytes per 125 us */
487
488/*
489 * P18 : SBA Overhead Request
490 */
491#define SWAP_SMT_P0018 "l"
492
493struct smt_p_0018 {
494 struct smt_para para ; /* generic parameter header */
495 int sba_ov_req ; /* total sync bandwidth req for overhead*/
496} ; /* measuered in bytes per T_Neg */
497
498/*
499 * P19 : SBA Allocation Address
500 */
501#define SWAP_SMT_P0019 "s6"
502
503struct smt_p_0019 {
504 struct smt_para para ; /* generic parameter header */
505 u_short sba_pad ;
506 struct fddi_addr alloc_addr ; /* Allocation Address */
507} ;
508
509/*
510 * P1A : SBA Category
511 */
512#define SWAP_SMT_P001A "l"
513
514struct smt_p_001a {
515 struct smt_para para ; /* generic parameter header */
516 u_int category ; /* Allocator defined classification */
517} ;
518
519/*
520 * P1B : Maximum T_Neg
521 */
522#define SWAP_SMT_P001B "l"
523
524struct smt_p_001b {
525 struct smt_para para ; /* generic parameter header */
526 u_int max_t_neg ; /* longest T_NEG for the sync service*/
527} ;
528
529/*
530 * P1C : Minimum SBA Segment Size
531 */
532#define SWAP_SMT_P001C "l"
533
534struct smt_p_001c {
535 struct smt_para para ; /* generic parameter header */
536 u_int min_seg_siz ; /* smallest number of bytes per frame*/
537} ;
538
539/*
540 * P1D : SBA Allocatable
541 */
542#define SWAP_SMT_P001D "l"
543
544struct smt_p_001d {
545 struct smt_para para ; /* generic parameter header */
546 u_int allocatable ; /* total sync bw available for alloc */
547} ;
548
549/*
550 * P20 0B : frame status capabilities
551 * NOTE: not in swap table, is used by smt.c AND PMF table
552 */
553#define SMT_P_FSC 0x200b
554/* #define SWAP_SMT_P_FSC "ssss" */
555
556struct smt_p_fsc {
557 struct smt_para para ; /* generic parameter header */
558 u_short fsc_pad0 ;
559 u_short fsc_mac_index ; /* mac index 1 .. ff */
560 u_short fsc_pad1 ;
561 u_short fsc_value ; /* FSC_TYPE[0-2] */
562} ;
563
564#define FSC_TYPE0 0 /* "normal" node (A/C handling) */
565#define FSC_TYPE1 1 /* Special A/C indicator forwarding */
566#define FSC_TYPE2 2 /* Special A/C indicator forwarding */
567
568/*
569 * P00 21 : user defined authoriziation (see pmf.c)
570 */
571#define SMT_P_AUTHOR 0x0021
572
573/*
574 * notification parameters
575 */
576#define SWAP_SMT_P1048 "ll"
577struct smt_p_1048 {
578 u_int p1048_flag ;
579 u_int p1048_cf_state ;
580} ;
581
582/*
583 * NOTE: all 2xxx 3xxx and 4xxx must include the INDEX in the swap string,
584 * even so the INDEX is NOT part of the struct.
585 * INDEX is already swapped in pmf.c, format in string is '4'
586 */
587#define SWAP_SMT_P208C "4lss66"
588struct smt_p_208c {
589 u_int p208c_flag ;
590 u_short p208c_pad ;
591 u_short p208c_dupcondition ;
592 struct fddi_addr p208c_fddilong ;
593 struct fddi_addr p208c_fddiunalong ;
594} ;
595
596#define SWAP_SMT_P208D "4lllll"
597struct smt_p_208d {
598 u_int p208d_flag ;
599 u_int p208d_frame_ct ;
600 u_int p208d_error_ct ;
601 u_int p208d_lost_ct ;
602 u_int p208d_ratio ;
603} ;
604
605#define SWAP_SMT_P208E "4llll"
606struct smt_p_208e {
607 u_int p208e_flag ;
608 u_int p208e_not_copied ;
609 u_int p208e_copied ;
610 u_int p208e_not_copied_ratio ;
611} ;
612
613#define SWAP_SMT_P208F "4ll6666s6"
614
615struct smt_p_208f {
616 u_int p208f_multiple ;
617 u_int p208f_nacondition ;
618 struct fddi_addr p208f_old_una ;
619 struct fddi_addr p208f_new_una ;
620 struct fddi_addr p208f_old_dna ;
621 struct fddi_addr p208f_new_dna ;
622 u_short p208f_curren_path ;
623 struct fddi_addr p208f_smt_address ;
624} ;
625
626#define SWAP_SMT_P2090 "4lssl"
627
628struct smt_p_2090 {
629 u_int p2090_multiple ;
630 u_short p2090_availablepaths ;
631 u_short p2090_currentpath ;
632 u_int p2090_requestedpaths ;
633} ;
634
635/*
636 * NOTE:
637 * special kludge for parameters 320b,320f,3210
638 * these parameters are part of RAF frames
639 * RAF frames are parsed in SBA.C and must be swapped
640 * PMF.C has special code to avoid double swapping
641 */
642#ifdef LITTLE_ENDIAN
643#define SBAPATHINDEX (0x01000000L)
644#else
645#define SBAPATHINDEX (0x01L)
646#endif
647
648#define SWAP_SMT_P320B "42s"
649
650struct smt_p_320b {
651 struct smt_para para ; /* generic parameter header */
652 u_int mib_index ;
653 u_short path_pad ;
654 u_short path_index ;
655} ;
656
657#define SWAP_SMT_P320F "4l"
658
659struct smt_p_320f {
660 struct smt_para para ; /* generic parameter header */
661 u_int mib_index ;
662 u_int mib_payload ;
663} ;
664
665#define SWAP_SMT_P3210 "4l"
666
667struct smt_p_3210 {
668 struct smt_para para ; /* generic parameter header */
669 u_int mib_index ;
670 u_int mib_overhead ;
671} ;
672
673#define SWAP_SMT_P4050 "4l1111ll"
674
675struct smt_p_4050 {
676 u_int p4050_flag ;
677 u_char p4050_pad ;
678 u_char p4050_cutoff ;
679 u_char p4050_alarm ;
680 u_char p4050_estimate ;
681 u_int p4050_reject_ct ;
682 u_int p4050_ct ;
683} ;
684
685#define SWAP_SMT_P4051 "4lssss"
686struct smt_p_4051 {
687 u_int p4051_multiple ;
688 u_short p4051_porttype ;
689 u_short p4051_connectstate ;
690 u_short p4051_pc_neighbor ;
691 u_short p4051_pc_withhold ;
692} ;
693
694#define SWAP_SMT_P4052 "4ll"
695struct smt_p_4052 {
696 u_int p4052_flag ;
697 u_int p4052_eberrorcount ;
698} ;
699
700#define SWAP_SMT_P4053 "4lsslss"
701
702struct smt_p_4053 {
703 u_int p4053_multiple ;
704 u_short p4053_availablepaths ;
705 u_short p4053_currentpath ;
706 u_int p4053_requestedpaths ;
707 u_short p4053_mytype ;
708 u_short p4053_neighbortype ;
709} ;
710
711
712#define SMT_P_SETCOUNT 0x1035
713#define SWAP_SMT_P_SETCOUNT "l8"
714
715struct smt_p_setcount {
716 struct smt_para para ; /* generic parameter header */
717 u_int count ;
718 u_char timestamp[8] ;
719} ;
720
721/*
722 * SMT FRAMES
723 */
724
725/*
726 * NIF : neighbor information frames
727 */
728struct smt_nif {
729 struct smt_header smt ; /* generic header */
730 struct smt_p_una una ; /* UNA */
731 struct smt_p_sde sde ; /* station descriptor */
732 struct smt_p_state state ; /* station state */
733#ifdef SMT6_10
734 struct smt_p_fsc fsc ; /* frame status cap. */
735#endif
736} ;
737
738/*
739 * SIF : station information frames
740 */
741struct smt_sif_config {
742 struct smt_header smt ; /* generic header */
743 struct smt_p_timestamp ts ; /* time stamp */
744 struct smt_p_sde sde ; /* station descriptor */
745 struct smt_p_version version ; /* supported versions */
746 struct smt_p_state state ; /* station state */
747 struct smt_p_policy policy ; /* station policy */
748 struct smt_p_latency latency ; /* path latency */
749 struct smt_p_neighbor neighbor ; /* neighbors, we have only one*/
750#ifdef OPT_PMF
751 struct smt_p_setcount setcount ; /* Set Count mandatory */
752#endif
753 /* WARNING : path MUST BE LAST FIELD !!! (see smt.c:smt_fill_path) */
754 struct smt_p_path path ; /* path descriptor */
755} ;
756#define SIZEOF_SMT_SIF_CONFIG (sizeof(struct smt_sif_config)- \
757 sizeof(struct smt_p_path))
758
759struct smt_sif_operation {
760 struct smt_header smt ; /* generic header */
761 struct smt_p_timestamp ts ; /* time stamp */
762 struct smt_p_mac_status status ; /* mac status */
763 struct smt_p_mac_counter mc ; /* MAC counter */
764 struct smt_p_mac_fnc fnc ; /* MAC frame not copied */
765 struct smp_p_manufacturer man ; /* manufacturer field */
766 struct smp_p_user user ; /* user field */
767#ifdef OPT_PMF
768 struct smt_p_setcount setcount ; /* Set Count mandatory */
769#endif
770 /* must be last */
771 struct smt_p_lem lem[1] ; /* phy lem status */
772} ;
773#define SIZEOF_SMT_SIF_OPERATION (sizeof(struct smt_sif_operation)- \
774 sizeof(struct smt_p_lem))
775
776/*
777 * ECF : echo frame
778 */
779struct smt_ecf {
780 struct smt_header smt ; /* generic header */
781 struct smt_p_echo ec_echo ; /* echo parameter */
782} ;
783#define SMT_ECF_LEN (sizeof(struct smt_header)+sizeof(struct smt_para))
784
785/*
786 * RDF : request denied frame
787 */
788struct smt_rdf {
789 struct smt_header smt ; /* generic header */
790 struct smt_p_reason reason ; /* reason code */
791 struct smt_p_version version ; /* supported versions */
792 struct smt_p_refused refused ; /* refused frame fragment */
793} ;
794
795/*
796 * SBA Request Allocation Response Frame
797 */
798struct smt_sba_alc_res {
799 struct smt_header smt ; /* generic header */
800 struct smt_p_0015 s_type ; /* resource type */
801 struct smt_p_0016 cmd ; /* SBA command */
802 struct smt_p_reason reason ; /* reason code */
803 struct smt_p_320b path ; /* path type */
804 struct smt_p_320f payload ; /* current SBA payload */
805 struct smt_p_3210 overhead ; /* current SBA overhead */
806 struct smt_p_0019 a_addr ; /* Allocation Address */
807 struct smt_p_001a cat ; /* Category - from the request */
808 struct smt_p_001d alloc ; /* SBA Allocatable */
809} ;
810
811/*
812 * SBA Request Allocation Request Frame
813 */
814struct smt_sba_alc_req {
815 struct smt_header smt ; /* generic header */
816 struct smt_p_0015 s_type ; /* resource type */
817 struct smt_p_0016 cmd ; /* SBA command */
818 struct smt_p_320b path ; /* path type */
819 struct smt_p_0017 pl_req ; /* requested payload */
820 struct smt_p_0018 ov_req ; /* requested SBA overhead */
821 struct smt_p_320f payload ; /* current SBA payload */
822 struct smt_p_3210 overhead ; /* current SBA overhead */
823 struct smt_p_0019 a_addr ; /* Allocation Address */
824 struct smt_p_001a cat ; /* Category - from the request */
825 struct smt_p_001b tneg ; /* max T-NEG */
826 struct smt_p_001c segm ; /* minimum segment size */
827} ;
828
829/*
830 * SBA Change Allocation Request Frame
831 */
832struct smt_sba_chg {
833 struct smt_header smt ; /* generic header */
834 struct smt_p_0015 s_type ; /* resource type */
835 struct smt_p_0016 cmd ; /* SBA command */
836 struct smt_p_320b path ; /* path type */
837 struct smt_p_320f payload ; /* current SBA payload */
838 struct smt_p_3210 overhead ; /* current SBA overhead */
839 struct smt_p_001a cat ; /* Category - from the request */
840} ;
841
842/*
843 * SBA Report Allocation Request Frame
844 */
845struct smt_sba_rep_req {
846 struct smt_header smt ; /* generic header */
847 struct smt_p_0015 s_type ; /* resource type */
848 struct smt_p_0016 cmd ; /* SBA command */
849} ;
850
851/*
852 * SBA Report Allocation Response Frame
853 */
854struct smt_sba_rep_res {
855 struct smt_header smt ; /* generic header */
856 struct smt_p_0015 s_type ; /* resource type */
857 struct smt_p_0016 cmd ; /* SBA command */
858 struct smt_p_320b path ; /* path type */
859 struct smt_p_320f payload ; /* current SBA payload */
860 struct smt_p_3210 overhead ; /* current SBA overhead */
861} ;
862
863/*
864 * actions
865 */
866#define SMT_STATION_ACTION 1
867#define SMT_STATION_ACTION_CONNECT 0
868#define SMT_STATION_ACTION_DISCONNECT 1
869#define SMT_STATION_ACTION_PATHTEST 2
870#define SMT_STATION_ACTION_SELFTEST 3
871#define SMT_STATION_ACTION_DISABLE_A 4
872#define SMT_STATION_ACTION_DISABLE_B 5
873#define SMT_STATION_ACTION_DISABLE_M 6
874
875#define SMT_PORT_ACTION 2
876#define SMT_PORT_ACTION_MAINT 0
877#define SMT_PORT_ACTION_ENABLE 1
878#define SMT_PORT_ACTION_DISABLE 2
879#define SMT_PORT_ACTION_START 3
880#define SMT_PORT_ACTION_STOP 4
881
882#endif /* _SMT_ */
diff --git a/drivers/net/skfp/h/smt_p.h b/drivers/net/skfp/h/smt_p.h
deleted file mode 100644
index 99f9be9552bb..000000000000
--- a/drivers/net/skfp/h/smt_p.h
+++ /dev/null
@@ -1,326 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 * defines for all SMT attributes
17 */
18
19/*
20 * this boring file was produced by perl
21 * thanks Larry !
22 */
23#define SMT_P0012 0x0012
24
25#define SMT_P0015 0x0015
26#define SMT_P0016 0x0016
27#define SMT_P0017 0x0017
28#define SMT_P0018 0x0018
29#define SMT_P0019 0x0019
30
31#define SMT_P001A 0x001a
32#define SMT_P001B 0x001b
33#define SMT_P001C 0x001c
34#define SMT_P001D 0x001d
35
36#define SMT_P100A 0x100a
37#define SMT_P100B 0x100b
38#define SMT_P100C 0x100c
39#define SMT_P100D 0x100d
40#define SMT_P100E 0x100e
41#define SMT_P100F 0x100f
42#define SMT_P1010 0x1010
43#define SMT_P1011 0x1011
44#define SMT_P1012 0x1012
45#define SMT_P1013 0x1013
46#define SMT_P1014 0x1014
47#define SMT_P1015 0x1015
48#define SMT_P1016 0x1016
49#define SMT_P1017 0x1017
50#define SMT_P1018 0x1018
51#define SMT_P1019 0x1019
52#define SMT_P101A 0x101a
53#define SMT_P101B 0x101b
54#define SMT_P101C 0x101c
55#define SMT_P101D 0x101d
56#define SMT_P101E 0x101e
57#define SMT_P101F 0x101f
58#define SMT_P1020 0x1020
59#define SMT_P1021 0x1021
60#define SMT_P1022 0x1022
61#define SMT_P1023 0x1023
62#define SMT_P1024 0x1024
63#define SMT_P1025 0x1025
64#define SMT_P1026 0x1026
65#define SMT_P1027 0x1027
66#define SMT_P1028 0x1028
67#define SMT_P1029 0x1029
68#define SMT_P102A 0x102a
69#define SMT_P102B 0x102b
70#define SMT_P102C 0x102c
71#define SMT_P102D 0x102d
72#define SMT_P102E 0x102e
73#define SMT_P102F 0x102f
74#define SMT_P1030 0x1030
75#define SMT_P1031 0x1031
76#define SMT_P1032 0x1032
77#define SMT_P1033 0x1033
78#define SMT_P1034 0x1034
79#define SMT_P1035 0x1035
80#define SMT_P1036 0x1036
81#define SMT_P1037 0x1037
82#define SMT_P1038 0x1038
83#define SMT_P1039 0x1039
84#define SMT_P103A 0x103a
85#define SMT_P103B 0x103b
86#define SMT_P103C 0x103c
87#define SMT_P103D 0x103d
88#define SMT_P103E 0x103e
89#define SMT_P103F 0x103f
90#define SMT_P1040 0x1040
91#define SMT_P1041 0x1041
92#define SMT_P1042 0x1042
93#define SMT_P1043 0x1043
94#define SMT_P1044 0x1044
95#define SMT_P1045 0x1045
96#define SMT_P1046 0x1046
97#define SMT_P1047 0x1047
98#define SMT_P1048 0x1048
99#define SMT_P1049 0x1049
100#define SMT_P104A 0x104a
101#define SMT_P104B 0x104b
102#define SMT_P104C 0x104c
103#define SMT_P104D 0x104d
104#define SMT_P104E 0x104e
105#define SMT_P104F 0x104f
106#define SMT_P1050 0x1050
107#define SMT_P1051 0x1051
108#define SMT_P1052 0x1052
109#define SMT_P1053 0x1053
110#define SMT_P1054 0x1054
111
112#define SMT_P10F0 0x10f0
113#define SMT_P10F1 0x10f1
114#ifdef ESS
115#define SMT_P10F2 0x10f2
116#define SMT_P10F3 0x10f3
117#define SMT_P10F4 0x10f4
118#define SMT_P10F5 0x10f5
119#define SMT_P10F6 0x10f6
120#define SMT_P10F7 0x10f7
121#endif
122#ifdef SBA
123#define SMT_P10F8 0x10f8
124#define SMT_P10F9 0x10f9
125#endif
126
127#define SMT_P200A 0x200a
128#define SMT_P200B 0x200b
129#define SMT_P200C 0x200c
130#define SMT_P200D 0x200d
131#define SMT_P200E 0x200e
132#define SMT_P200F 0x200f
133#define SMT_P2010 0x2010
134#define SMT_P2011 0x2011
135#define SMT_P2012 0x2012
136#define SMT_P2013 0x2013
137#define SMT_P2014 0x2014
138#define SMT_P2015 0x2015
139#define SMT_P2016 0x2016
140#define SMT_P2017 0x2017
141#define SMT_P2018 0x2018
142#define SMT_P2019 0x2019
143#define SMT_P201A 0x201a
144#define SMT_P201B 0x201b
145#define SMT_P201C 0x201c
146#define SMT_P201D 0x201d
147#define SMT_P201E 0x201e
148#define SMT_P201F 0x201f
149#define SMT_P2020 0x2020
150#define SMT_P2021 0x2021
151#define SMT_P2022 0x2022
152#define SMT_P2023 0x2023
153#define SMT_P2024 0x2024
154#define SMT_P2025 0x2025
155#define SMT_P2026 0x2026
156#define SMT_P2027 0x2027
157#define SMT_P2028 0x2028
158#define SMT_P2029 0x2029
159#define SMT_P202A 0x202a
160#define SMT_P202B 0x202b
161#define SMT_P202C 0x202c
162#define SMT_P202D 0x202d
163#define SMT_P202E 0x202e
164#define SMT_P202F 0x202f
165#define SMT_P2030 0x2030
166#define SMT_P2031 0x2031
167#define SMT_P2032 0x2032
168#define SMT_P2033 0x2033
169#define SMT_P2034 0x2034
170#define SMT_P2035 0x2035
171#define SMT_P2036 0x2036
172#define SMT_P2037 0x2037
173#define SMT_P2038 0x2038
174#define SMT_P2039 0x2039
175#define SMT_P203A 0x203a
176#define SMT_P203B 0x203b
177#define SMT_P203C 0x203c
178#define SMT_P203D 0x203d
179#define SMT_P203E 0x203e
180#define SMT_P203F 0x203f
181#define SMT_P2040 0x2040
182#define SMT_P2041 0x2041
183#define SMT_P2042 0x2042
184#define SMT_P2043 0x2043
185#define SMT_P2044 0x2044
186#define SMT_P2045 0x2045
187#define SMT_P2046 0x2046
188#define SMT_P2047 0x2047
189#define SMT_P2048 0x2048
190#define SMT_P2049 0x2049
191#define SMT_P204A 0x204a
192#define SMT_P204B 0x204b
193#define SMT_P204C 0x204c
194#define SMT_P204D 0x204d
195#define SMT_P204E 0x204e
196#define SMT_P204F 0x204f
197#define SMT_P2050 0x2050
198#define SMT_P2051 0x2051
199#define SMT_P2052 0x2052
200#define SMT_P2053 0x2053
201#define SMT_P2054 0x2054
202#define SMT_P2055 0x2055
203#define SMT_P2056 0x2056
204#define SMT_P2057 0x2057
205#define SMT_P2058 0x2058
206#define SMT_P2059 0x2059
207#define SMT_P205A 0x205a
208#define SMT_P205B 0x205b
209#define SMT_P205C 0x205c
210#define SMT_P205D 0x205d
211#define SMT_P205E 0x205e
212#define SMT_P205F 0x205f
213#define SMT_P2060 0x2060
214#define SMT_P2061 0x2061
215#define SMT_P2062 0x2062
216#define SMT_P2063 0x2063
217#define SMT_P2064 0x2064
218#define SMT_P2065 0x2065
219#define SMT_P2066 0x2066
220#define SMT_P2067 0x2067
221#define SMT_P2068 0x2068
222#define SMT_P2069 0x2069
223#define SMT_P206A 0x206a
224#define SMT_P206B 0x206b
225#define SMT_P206C 0x206c
226#define SMT_P206D 0x206d
227#define SMT_P206E 0x206e
228#define SMT_P206F 0x206f
229#define SMT_P2070 0x2070
230#define SMT_P2071 0x2071
231#define SMT_P2072 0x2072
232#define SMT_P2073 0x2073
233#define SMT_P2074 0x2074
234#define SMT_P2075 0x2075
235#define SMT_P2076 0x2076
236
237#define SMT_P208C 0x208c
238#define SMT_P208D 0x208d
239#define SMT_P208E 0x208e
240#define SMT_P208F 0x208f
241#define SMT_P2090 0x2090
242
243#define SMT_P20F0 0x20F0
244#define SMT_P20F1 0x20F1
245
246#define SMT_P320A 0x320a
247#define SMT_P320B 0x320b
248#define SMT_P320C 0x320c
249#define SMT_P320D 0x320d
250#define SMT_P320E 0x320e
251#define SMT_P320F 0x320f
252#define SMT_P3210 0x3210
253#define SMT_P3211 0x3211
254#define SMT_P3212 0x3212
255#define SMT_P3213 0x3213
256#define SMT_P3214 0x3214
257#define SMT_P3215 0x3215
258#define SMT_P3216 0x3216
259#define SMT_P3217 0x3217
260
261#define SMT_P400A 0x400a
262#define SMT_P400B 0x400b
263#define SMT_P400C 0x400c
264#define SMT_P400D 0x400d
265#define SMT_P400E 0x400e
266#define SMT_P400F 0x400f
267#define SMT_P4010 0x4010
268#define SMT_P4011 0x4011
269#define SMT_P4012 0x4012
270#define SMT_P4013 0x4013
271#define SMT_P4014 0x4014
272#define SMT_P4015 0x4015
273#define SMT_P4016 0x4016
274#define SMT_P4017 0x4017
275#define SMT_P4018 0x4018
276#define SMT_P4019 0x4019
277#define SMT_P401A 0x401a
278#define SMT_P401B 0x401b
279#define SMT_P401C 0x401c
280#define SMT_P401D 0x401d
281#define SMT_P401E 0x401e
282#define SMT_P401F 0x401f
283#define SMT_P4020 0x4020
284#define SMT_P4021 0x4021
285#define SMT_P4022 0x4022
286#define SMT_P4023 0x4023
287#define SMT_P4024 0x4024
288#define SMT_P4025 0x4025
289#define SMT_P4026 0x4026
290#define SMT_P4027 0x4027
291#define SMT_P4028 0x4028
292#define SMT_P4029 0x4029
293#define SMT_P402A 0x402a
294#define SMT_P402B 0x402b
295#define SMT_P402C 0x402c
296#define SMT_P402D 0x402d
297#define SMT_P402E 0x402e
298#define SMT_P402F 0x402f
299#define SMT_P4030 0x4030
300#define SMT_P4031 0x4031
301#define SMT_P4032 0x4032
302#define SMT_P4033 0x4033
303#define SMT_P4034 0x4034
304#define SMT_P4035 0x4035
305#define SMT_P4036 0x4036
306#define SMT_P4037 0x4037
307#define SMT_P4038 0x4038
308#define SMT_P4039 0x4039
309#define SMT_P403A 0x403a
310#define SMT_P403B 0x403b
311#define SMT_P403C 0x403c
312#define SMT_P403D 0x403d
313#define SMT_P403E 0x403e
314#define SMT_P403F 0x403f
315#define SMT_P4040 0x4040
316#define SMT_P4041 0x4041
317#define SMT_P4042 0x4042
318#define SMT_P4043 0x4043
319#define SMT_P4044 0x4044
320#define SMT_P4045 0x4045
321#define SMT_P4046 0x4046
322
323#define SMT_P4050 0x4050
324#define SMT_P4051 0x4051
325#define SMT_P4052 0x4052
326#define SMT_P4053 0x4053
diff --git a/drivers/net/skfp/h/smtstate.h b/drivers/net/skfp/h/smtstate.h
deleted file mode 100644
index 62fe695077a9..000000000000
--- a/drivers/net/skfp/h/smtstate.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _SKFP_H_SMTSTATE_H_
16#define _SKFP_H_SMTSTATE_H_
17
18/*
19 * SMT state definitions
20 */
21
22#ifndef KERNEL
23/*
24 * PCM states
25 */
26#define PC0_OFF 0
27#define PC1_BREAK 1
28#define PC2_TRACE 2
29#define PC3_CONNECT 3
30#define PC4_NEXT 4
31#define PC5_SIGNAL 5
32#define PC6_JOIN 6
33#define PC7_VERIFY 7
34#define PC8_ACTIVE 8
35#define PC9_MAINT 9
36
37/*
38 * PCM modes
39 */
40#define PM_NONE 0
41#define PM_PEER 1
42#define PM_TREE 2
43
44/*
45 * PCM type
46 */
47#define TA 0
48#define TB 1
49#define TS 2
50#define TM 3
51#define TNONE 4
52
53/*
54 * CFM states
55 */
56#define SC0_ISOLATED 0 /* isolated */
57#define SC1_WRAP_A 5 /* wrap A */
58#define SC2_WRAP_B 6 /* wrap B */
59#define SC4_THRU_A 12 /* through A */
60#define SC5_THRU_B 7 /* through B (SMt 6.2) */
61#define SC7_WRAP_S 8 /* SAS */
62
63/*
64 * ECM states
65 */
66#define EC0_OUT 0
67#define EC1_IN 1
68#define EC2_TRACE 2
69#define EC3_LEAVE 3
70#define EC4_PATH_TEST 4
71#define EC5_INSERT 5
72#define EC6_CHECK 6
73#define EC7_DEINSERT 7
74
75/*
76 * RMT states
77 */
78#define RM0_ISOLATED 0
79#define RM1_NON_OP 1 /* not operational */
80#define RM2_RING_OP 2 /* ring operational */
81#define RM3_DETECT 3 /* detect dupl addresses */
82#define RM4_NON_OP_DUP 4 /* dupl. addr detected */
83#define RM5_RING_OP_DUP 5 /* ring oper. with dupl. addr */
84#define RM6_DIRECTED 6 /* sending directed beacons */
85#define RM7_TRACE 7 /* trace initiated */
86#endif
87
88struct pcm_state {
89 unsigned char pcm_type ; /* TA TB TS TM */
90 unsigned char pcm_state ; /* state PC[0-9]_* */
91 unsigned char pcm_mode ; /* PM_{NONE,PEER,TREE} */
92 unsigned char pcm_neighbor ; /* TA TB TS TM */
93 unsigned char pcm_bsf ; /* flag bs : TRUE/FALSE */
94 unsigned char pcm_lsf ; /* flag ls : TRUE/FALSE */
95 unsigned char pcm_lct_fail ; /* counter lct_fail */
96 unsigned char pcm_ls_rx ; /* rx line state */
97 short pcm_r_val ; /* signaling bits */
98 short pcm_t_val ; /* signaling bits */
99} ;
100
101struct smt_state {
102 struct pcm_state pcm_state[NUMPHYS] ; /* port A & port B */
103} ;
104
105#endif
106
diff --git a/drivers/net/skfp/h/supern_2.h b/drivers/net/skfp/h/supern_2.h
deleted file mode 100644
index 0b73690280f6..000000000000
--- a/drivers/net/skfp/h/supern_2.h
+++ /dev/null
@@ -1,1059 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 defines for AMD Supernet II chip set
17 the chips are referred to as
18 FPLUS Formac Plus
19 PLC Physical Layer
20
21 added defines for AMD Supernet III chip set
22 added comments on differences between Supernet II and Supernet III
23 added defines for the Motorola ELM (MOT_ELM)
24*/
25
26#ifndef _SUPERNET_
27#define _SUPERNET_
28
29/*
30 * Define Supernet 3 when used
31 */
32#ifdef PCI
33#ifndef SUPERNET_3
34#define SUPERNET_3
35#endif
36#define TAG
37#endif
38
39#define MB 0xff
40#define MW 0xffff
41#define MD 0xffffffff
42
43/*
44 * FORMAC frame status (rx_msext)
45 */
46#define FS_EI (1<<2)
47#define FS_AI (1<<1)
48#define FS_CI (1<<0)
49
50#define FS_MSVALID (1<<15) /* end of queue */
51#define FS_MSRABT (1<<14) /* frame was aborted during reception*/
52#define FS_SSRCRTG (1<<12) /* if SA has set MSB (source-routing)*/
53#define FS_SEAC2 (FS_EI<<9) /* error indicator */
54#define FS_SEAC1 (FS_AI<<9) /* address indicator */
55#define FS_SEAC0 (FS_CI<<9) /* copy indicator */
56#define FS_SFRMERR (1<<8) /* error detected (CRC or length) */
57#define FS_SADRRG (1<<7) /* address recognized */
58#define FS_SFRMTY2 (1<<6) /* frame-class bit */
59#define FS_SFRMTY1 (1<<5) /* frame-type bit (impementor) */
60#define FS_SFRMTY0 (1<<4) /* frame-type bit (LLC) */
61#define FS_ERFBB1 (1<<1) /* byte offset (depends on LSB bit) */
62#define FS_ERFBB0 (1<<0) /* - " - */
63
64/*
65 * status frame type
66 */
67#define FRM_SMT (0) /* asynchr. frames */
68#define FRM_LLCA (1)
69#define FRM_IMPA (2)
70#define FRM_MAC (4) /* synchr. frames */
71#define FRM_LLCS (5)
72#define FRM_IMPS (6)
73
74/*
75 * bits in rx_descr.i (receive frame status word)
76 */
77#define RX_MSVALID ((long)1<<31) /* memory status valid */
78#define RX_MSRABT ((long)1<<30) /* memory status receive abort */
79#define RX_FS_E ((long)FS_SEAC2<<16) /* error indicator */
80#define RX_FS_A ((long)FS_SEAC1<<16) /* address indicator */
81#define RX_FS_C ((long)FS_SEAC0<<16) /* copy indicator */
82#define RX_FS_CRC ((long)FS_SFRMERR<<16)/* error detected */
83#define RX_FS_ADDRESS ((long)FS_SADRRG<<16) /* address recognized */
84#define RX_FS_MAC ((long)FS_SFRMTY2<<16)/* MAC frame */
85#define RX_FS_SMT ((long)0<<16) /* SMT frame */
86#define RX_FS_IMPL ((long)FS_SFRMTY1<<16)/* implementer frame */
87#define RX_FS_LLC ((long)FS_SFRMTY0<<16)/* LLC frame */
88
89/*
90 * receive frame descriptor
91 */
92union rx_descr {
93 struct {
94#ifdef LITTLE_ENDIAN
95 unsigned rx_length :16 ; /* frame length lower/upper byte */
96 unsigned rx_erfbb :2 ; /* received frame byte boundary */
97 unsigned rx_reserv2:2 ; /* reserved */
98 unsigned rx_sfrmty :3 ; /* frame type bits */
99 unsigned rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
100 unsigned rx_sfrmerr:1 ; /* received frame not valid */
101 unsigned rx_seac0 :1 ; /* frame-copied C-indicator */
102 unsigned rx_seac1 :1 ; /* address-match A-indicator */
103 unsigned rx_seac2 :1 ; /* frame-error E-indicator */
104 unsigned rx_ssrcrtg:1 ; /* == 1 SA has MSB set */
105 unsigned rx_reserv1:1 ; /* reserved */
106 unsigned rx_msrabt :1 ; /* memory status receive abort */
107 unsigned rx_msvalid:1 ; /* memory status valid */
108#else
109 unsigned rx_msvalid:1 ; /* memory status valid */
110 unsigned rx_msrabt :1 ; /* memory status receive abort */
111 unsigned rx_reserv1:1 ; /* reserved */
112 unsigned rx_ssrcrtg:1 ; /* == 1 SA has MSB set */
113 unsigned rx_seac2 :1 ; /* frame-error E-indicator */
114 unsigned rx_seac1 :1 ; /* address-match A-indicator */
115 unsigned rx_seac0 :1 ; /* frame-copied C-indicator */
116 unsigned rx_sfrmerr:1 ; /* received frame not valid */
117 unsigned rx_sadrrg :1 ; /* DA == MA or broad-/multicast */
118 unsigned rx_sfrmty :3 ; /* frame type bits */
119 unsigned rx_erfbb :2 ; /* received frame byte boundary */
120 unsigned rx_reserv2:2 ; /* reserved */
121 unsigned rx_length :16 ; /* frame length lower/upper byte */
122#endif
123 } r ;
124 long i ;
125} ;
126
127/* defines for Receive Frame Descriptor access */
128#define RD_S_ERFBB 0x00030000L /* received frame byte boundary */
129#define RD_S_RES2 0x000c0000L /* reserved */
130#define RD_S_SFRMTY 0x00700000L /* frame type bits */
131#define RD_S_SADRRG 0x00800000L /* DA == MA or broad-/multicast */
132#define RD_S_SFRMERR 0x01000000L /* received frame not valid */
133#define RD_S_SEAC 0x0e000000L /* frame status indicators */
134#define RD_S_SEAC0 0x02000000L /* frame-copied case-indicator */
135#define RD_S_SEAC1 0x04000000L /* address-match A-indicator */
136#define RD_S_SEAC2 0x08000000L /* frame-error E-indicator */
137#define RD_S_SSRCRTG 0x10000000L /* == 1 SA has MSB set */
138#define RD_S_RES1 0x20000000L /* reserved */
139#define RD_S_MSRABT 0x40000000L /* memory status receive abort */
140#define RD_S_MSVALID 0x80000000L /* memory status valid */
141
142#define RD_STATUS 0xffff0000L
143#define RD_LENGTH 0x0000ffffL
144
145/* defines for Receive Frames Status Word values */
146/*RD_S_SFRMTY*/
147#define RD_FRM_SMT (unsigned long)(0<<20) /* asynchr. frames */
148#define RD_FRM_LLCA (unsigned long)(1<<20)
149#define RD_FRM_IMPA (unsigned long)(2<<20)
150#define RD_FRM_MAC (unsigned long)(4<<20) /* synchr. frames */
151#define RD_FRM_LLCS (unsigned long)(5<<20)
152#define RD_FRM_IMPS (unsigned long)(6<<20)
153
154#define TX_DESCRIPTOR 0x40000000L
155#define TX_OFFSET_3 0x18000000L
156
157#define TXP1 2
158
159/*
160 * transmit frame descriptor
161 */
162union tx_descr {
163 struct {
164#ifdef LITTLE_ENDIAN
165 unsigned tx_length:16 ; /* frame length lower/upper byte */
166 unsigned tx_res :8 ; /* reserved (bit 16..23) */
167 unsigned tx_xmtabt:1 ; /* transmit abort */
168 unsigned tx_nfcs :1 ; /* no frame check sequence */
169 unsigned tx_xdone :1 ; /* give up token */
170 unsigned tx_rpxm :2 ; /* byte offset */
171 unsigned tx_pat1 :2 ; /* must be TXP1 */
172 unsigned tx_more :1 ; /* more frame in chain */
173#else
174 unsigned tx_more :1 ; /* more frame in chain */
175 unsigned tx_pat1 :2 ; /* must be TXP1 */
176 unsigned tx_rpxm :2 ; /* byte offset */
177 unsigned tx_xdone :1 ; /* give up token */
178 unsigned tx_nfcs :1 ; /* no frame check sequence */
179 unsigned tx_xmtabt:1 ; /* transmit abort */
180 unsigned tx_res :8 ; /* reserved (bit 16..23) */
181 unsigned tx_length:16 ; /* frame length lower/upper byte */
182#endif
183 } t ;
184 long i ;
185} ;
186
187/* defines for Transmit Descriptor access */
188#define TD_C_MORE 0x80000000L /* more frame in chain */
189#define TD_C_DESCR 0x60000000L /* must be TXP1 */
190#define TD_C_TXFBB 0x18000000L /* byte offset */
191#define TD_C_XDONE 0x04000000L /* give up token */
192#define TD_C_NFCS 0x02000000L /* no frame check sequence */
193#define TD_C_XMTABT 0x01000000L /* transmit abort */
194
195#define TD_C_LNCNU 0x0000ff00L
196#define TD_C_LNCNL 0x000000ffL
197#define TD_C_LNCN 0x0000ffffL /* frame length lower/upper byte */
198
199/*
200 * transmit pointer
201 */
202union tx_pointer {
203 struct t {
204#ifdef LITTLE_ENDIAN
205 unsigned tp_pointer:16 ; /* pointer to tx_descr (low/high) */
206 unsigned tp_res :8 ; /* reserved (bit 16..23) */
207 unsigned tp_pattern:8 ; /* fixed pattern (bit 24..31) */
208#else
209 unsigned tp_pattern:8 ; /* fixed pattern (bit 24..31) */
210 unsigned tp_res :8 ; /* reserved (bit 16..23) */
211 unsigned tp_pointer:16 ; /* pointer to tx_descr (low/high) */
212#endif
213 } t ;
214 long i ;
215} ;
216
217/* defines for Nontag Mode Pointer access */
218#define TD_P_CNTRL 0xff000000L
219#define TD_P_RPXU 0x0000ff00L
220#define TD_P_RPXL 0x000000ffL
221#define TD_P_RPX 0x0000ffffL
222
223
224#define TX_PATTERN 0xa0
225#define TX_POINTER_END 0xa0000000L
226#define TX_INT_PATTERN 0xa0000000L
227
228struct tx_queue {
229 struct tx_queue *tq_next ;
230 u_short tq_pack_offset ; /* offset buffer memory */
231 u_char tq_pad[2] ;
232} ;
233
234/*
235 defines for FORMAC Plus (Am79C830)
236*/
237
238/*
239 * FORMAC+ read/write (r/w) registers
240 */
241#define FM_CMDREG1 0x00 /* write command reg 1 instruction */
242#define FM_CMDREG2 0x01 /* write command reg 2 instruction */
243#define FM_ST1U 0x00 /* read upper 16-bit of status reg 1 */
244#define FM_ST1L 0x01 /* read lower 16-bit of status reg 1 */
245#define FM_ST2U 0x02 /* read upper 16-bit of status reg 2 */
246#define FM_ST2L 0x03 /* read lower 16-bit of status reg 2 */
247#define FM_IMSK1U 0x04 /* r/w upper 16-bit of IMSK 1 */
248#define FM_IMSK1L 0x05 /* r/w lower 16-bit of IMSK 1 */
249#define FM_IMSK2U 0x06 /* r/w upper 16-bit of IMSK 2 */
250#define FM_IMSK2L 0x07 /* r/w lower 16-bit of IMSK 2 */
251#define FM_SAID 0x08 /* r/w short addr.-individual */
252#define FM_LAIM 0x09 /* r/w long addr.-ind. (MSW of LAID) */
253#define FM_LAIC 0x0a /* r/w long addr.-ind. (middle)*/
254#define FM_LAIL 0x0b /* r/w long addr.-ind. (LSW) */
255#define FM_SAGP 0x0c /* r/w short address-group */
256#define FM_LAGM 0x0d /* r/w long addr.-gr. (MSW of LAGP) */
257#define FM_LAGC 0x0e /* r/w long addr.-gr. (middle) */
258#define FM_LAGL 0x0f /* r/w long addr.-gr. (LSW) */
259#define FM_MDREG1 0x10 /* r/w 16-bit mode reg 1 */
260#define FM_STMCHN 0x11 /* read state-machine reg */
261#define FM_MIR1 0x12 /* read upper 16-bit of MAC Info Reg */
262#define FM_MIR0 0x13 /* read lower 16-bit of MAC Info Reg */
263#define FM_TMAX 0x14 /* r/w 16-bit TMAX reg */
264#define FM_TVX 0x15 /* write 8-bit TVX reg with NP7-0
265 read TVX on NP7-0, timer on NP15-8*/
266#define FM_TRT 0x16 /* r/w upper 16-bit of TRT timer */
267#define FM_THT 0x17 /* r/w upper 16-bit of THT timer */
268#define FM_TNEG 0x18 /* read upper 16-bit of TNEG (TTRT) */
269#define FM_TMRS 0x19 /* read lower 5-bit of TNEG,TRT,THT */
270 /* F E D C B A 9 8 7 6 5 4 3 2 1 0
271 x |-TNEG4-0| |-TRT4-0-| |-THT4-0-| (x-late count) */
272#define FM_TREQ0 0x1a /* r/w 16-bit TREQ0 reg (LSW of TRT) */
273#define FM_TREQ1 0x1b /* r/w 16-bit TREQ1 reg (MSW of TRT) */
274#define FM_PRI0 0x1c /* r/w priority r. for asyn.-queue 0 */
275#define FM_PRI1 0x1d /* r/w priority r. for asyn.-queue 1 */
276#define FM_PRI2 0x1e /* r/w priority r. for asyn.-queue 2 */
277#define FM_TSYNC 0x1f /* r/w 16-bit of the TSYNC register */
278#define FM_MDREG2 0x20 /* r/w 16-bit mode reg 2 */
279#define FM_FRMTHR 0x21 /* r/w the frame threshold register */
280#define FM_EACB 0x22 /* r/w end addr of claim/beacon area */
281#define FM_EARV 0x23 /* r/w end addr of receive queue */
282/* Supernet 3 */
283#define FM_EARV1 FM_EARV
284
285#define FM_EAS 0x24 /* r/w end addr of synchr. queue */
286#define FM_EAA0 0x25 /* r/w end addr of asyn. queue 0 */
287#define FM_EAA1 0x26 /* r/w end addr of asyn. queue 1 */
288#define FM_EAA2 0x27 /* r/w end addr of asyn. queue 2 */
289#define FM_SACL 0x28 /* r/w start addr of claim frame */
290#define FM_SABC 0x29 /* r/w start addr of beacon frame */
291#define FM_WPXSF 0x2a /* r/w the write ptr. for special fr.*/
292#define FM_RPXSF 0x2b /* r/w the read ptr. for special fr. */
293#define FM_RPR 0x2d /* r/w the read ptr. for receive qu. */
294#define FM_WPR 0x2e /* r/w the write ptr. for receive qu.*/
295#define FM_SWPR 0x2f /* r/w the shadow wr.-ptr. for rec.q.*/
296/* Supernet 3 */
297#define FM_RPR1 FM_RPR
298#define FM_WPR1 FM_WPR
299#define FM_SWPR1 FM_SWPR
300
301#define FM_WPXS 0x30 /* r/w the write ptr. for synchr. qu.*/
302#define FM_WPXA0 0x31 /* r/w the write ptr. for asyn. qu.0 */
303#define FM_WPXA1 0x32 /* r/w the write ptr. for asyn. qu.1 */
304#define FM_WPXA2 0x33 /* r/w the write ptr. for asyn. qu.2 */
305#define FM_SWPXS 0x34 /* r/w the shadow wr.-ptr. for syn.q.*/
306#define FM_SWPXA0 0x35 /* r/w the shad. wr.-ptr. for asyn.q0*/
307#define FM_SWPXA1 0x36 /* r/w the shad. wr.-ptr. for asyn.q1*/
308#define FM_SWPXA2 0x37 /* r/w the shad. wr.-ptr. for asyn.q2*/
309#define FM_RPXS 0x38 /* r/w the read ptr. for synchr. qu. */
310#define FM_RPXA0 0x39 /* r/w the read ptr. for asyn. qu. 0 */
311#define FM_RPXA1 0x3a /* r/w the read ptr. for asyn. qu. 1 */
312#define FM_RPXA2 0x3b /* r/w the read ptr. for asyn. qu. 2 */
313#define FM_MARR 0x3c /* r/w the memory read addr register */
314#define FM_MARW 0x3d /* r/w the memory write addr register*/
315#define FM_MDRU 0x3e /* r/w upper 16-bit of mem. data reg */
316#define FM_MDRL 0x3f /* r/w lower 16-bit of mem. data reg */
317
318/* following instructions relate to MAC counters and timer */
319#define FM_TMSYNC 0x40 /* r/w upper 16 bits of TMSYNC timer */
320#define FM_FCNTR 0x41 /* r/w the 16-bit frame counter */
321#define FM_LCNTR 0x42 /* r/w the 16-bit lost counter */
322#define FM_ECNTR 0x43 /* r/w the 16-bit error counter */
323
324/* Supernet 3: extensions to old register block */
325#define FM_FSCNTR 0x44 /* r/? Frame Strip Counter */
326#define FM_FRSELREG 0x45 /* r/w Frame Selection Register */
327
328/* Supernet 3: extensions for 2. receive queue etc. */
329#define FM_MDREG3 0x60 /* r/w Mode Register 3 */
330#define FM_ST3U 0x61 /* read upper 16-bit of status reg 3 */
331#define FM_ST3L 0x62 /* read lower 16-bit of status reg 3 */
332#define FM_IMSK3U 0x63 /* r/w upper 16-bit of IMSK reg 3 */
333#define FM_IMSK3L 0x64 /* r/w lower 16-bit of IMSK reg 3 */
334#define FM_IVR 0x65 /* read Interrupt Vector register */
335#define FM_IMR 0x66 /* r/w Interrupt mask register */
336/* 0x67 Hidden */
337#define FM_RPR2 0x68 /* r/w the read ptr. for rec. qu. 2 */
338#define FM_WPR2 0x69 /* r/w the write ptr. for rec. qu. 2 */
339#define FM_SWPR2 0x6a /* r/w the shadow wptr. for rec. q. 2 */
340#define FM_EARV2 0x6b /* r/w end addr of rec. qu. 2 */
341#define FM_UNLCKDLY 0x6c /* r/w Auto Unlock Delay register */
342 /* Bit 15-8: RECV2 unlock threshold */
343 /* Bit 7-0: RECV1 unlock threshold */
344/* 0x6f-0x73 Hidden */
345#define FM_LTDPA1 0x79 /* r/w Last Trans desc ptr for A1 qu. */
346/* 0x80-0x9a PLCS registers of built-in PLCS (Supernet 3 only) */
347
348/* Supernet 3: Adderss Filter Registers */
349#define FM_AFCMD 0xb0 /* r/w Address Filter Command Reg */
350#define FM_AFSTAT 0xb2 /* r/w Address Filter Status Reg */
351#define FM_AFBIST 0xb4 /* r/w Address Filter BIST signature */
352#define FM_AFCOMP2 0xb6 /* r/w Address Filter Comparand 2 */
353#define FM_AFCOMP1 0xb8 /* r/w Address Filter Comparand 1 */
354#define FM_AFCOMP0 0xba /* r/w Address Filter Comparand 0 */
355#define FM_AFMASK2 0xbc /* r/w Address Filter Mask 2 */
356#define FM_AFMASK1 0xbe /* r/w Address Filter Mask 1 */
357#define FM_AFMASK0 0xc0 /* r/w Address Filter Mask 0 */
358#define FM_AFPERS 0xc2 /* r/w Address Filter Personality Reg */
359
360/* Supernet 3: Orion (PDX?) Registers */
361#define FM_ORBIST 0xd0 /* r/w Orion BIST signature */
362#define FM_ORSTAT 0xd2 /* r/w Orion Status Register */
363
364
365/*
366 * Mode Register 1 (MDREG1)
367 */
368#define FM_RES0 0x0001 /* reserved */
369 /* SN3: other definition */
370#define FM_XMTINH_HOLD 0x0002 /* transmit-inhibit/hold bit */
371 /* SN3: other definition */
372#define FM_HOFLXI 0x0003 /* SN3: Hold / Flush / Inhibit */
373#define FM_FULL_HALF 0x0004 /* full-duplex/half-duplex bit */
374#define FM_LOCKTX 0x0008 /* lock-transmit-asynchr.-queues bit */
375#define FM_EXGPA0 0x0010 /* extended-group-addressing bit 0 */
376#define FM_EXGPA1 0x0020 /* extended-group-addressing bit 1 */
377#define FM_DISCRY 0x0040 /* disable-carry bit */
378 /* SN3: reserved */
379#define FM_SELRA 0x0080 /* select input from PHY (1=RA,0=RB) */
380
381#define FM_ADDET 0x0700 /* address detection */
382#define FM_MDAMA (0<<8) /* address detection : DA = MA */
383#define FM_MDASAMA (1<<8) /* address detection : DA=MA||SA=MA */
384#define FM_MRNNSAFNMA (2<<8) /* rec. non-NSA frames DA=MA&&SA!=MA */
385#define FM_MRNNSAF (3<<8) /* rec. non-NSA frames DA = MA */
386#define FM_MDISRCV (4<<8) /* disable receive function */
387#define FM_MRES0 (5<<8) /* reserve */
388#define FM_MLIMPROM (6<<8) /* limited-promiscuous mode */
389#define FM_MPROMISCOUS (7<<8) /* address detection : promiscuous */
390
391#define FM_SELSA 0x0800 /* select-short-address bit */
392
393#define FM_MMODE 0x7000 /* mode select */
394#define FM_MINIT (0<<12) /* initialize */
395#define FM_MMEMACT (1<<12) /* memory activate */
396#define FM_MONLINESP (2<<12) /* on-line special */
397#define FM_MONLINE (3<<12) /* on-line (FDDI operational mode) */
398#define FM_MILOOP (4<<12) /* internal loopback */
399#define FM_MRES1 (5<<12) /* reserved */
400#define FM_MRES2 (6<<12) /* reserved */
401#define FM_MELOOP (7<<12) /* external loopback */
402
403#define FM_SNGLFRM 0x8000 /* single-frame-receive mode */
404 /* SN3: reserved */
405
406#define MDR1INIT (FM_MINIT | FM_MDAMA)
407
408/*
409 * Mode Register 2 (MDREG2)
410 */
411#define FM_AFULL 0x000f /* 4-bit value (empty loc.in txqueue)*/
412#define FM_RCVERR 0x0010 /* rec.-errored-frames bit */
413#define FM_SYMCTL 0x0020 /* sysmbol-control bit */
414 /* SN3: reserved */
415#define FM_SYNPRQ 0x0040 /* synchron.-NP-DMA-request bit */
416#define FM_ENNPRQ 0x0080 /* enable-NP-DMA-request bit */
417#define FM_ENHSRQ 0x0100 /* enable-host-request bit */
418#define FM_RXFBB01 0x0600 /* rec. frame byte boundary bit0 & 1 */
419#define FM_LSB 0x0800 /* determ. ordering of bytes in buffer*/
420#define FM_PARITY 0x1000 /* 1 = even, 0 = odd */
421#define FM_CHKPAR 0x2000 /* 1 = parity of 32-bit buffer BD-bus*/
422#define FM_STRPFCS 0x4000 /* 1 = strips FCS field of rec.frame */
423#define FM_BMMODE 0x8000 /* Buffer-Memory-Mode (1 = tag mode) */
424 /* SN3: 1 = tag, 0 = modified tag */
425
426/*
427 * Status Register 1, Upper 16 Bits (ST1U)
428 */
429#define FM_STEFRMS 0x0001 /* transmit end of frame: synchr. qu.*/
430#define FM_STEFRMA0 0x0002 /* transmit end of frame: asyn. qu.0 */
431#define FM_STEFRMA1 0x0004 /* transmit end of frame: asyn. qu.1 */
432#define FM_STEFRMA2 0x0008 /* transmit end of frame: asyn. qu.2 */
433 /* SN3: reserved */
434#define FM_STECFRMS 0x0010 /* transmit end of chain of syn. qu. */
435 /* SN3: reserved */
436#define FM_STECFRMA0 0x0020 /* transmit end of chain of asyn. q0 */
437 /* SN3: reserved */
438#define FM_STECFRMA1 0x0040 /* transmit end of chain of asyn. q1 */
439 /* SN3: STECMDA1 */
440#define FM_STECMDA1 0x0040 /* SN3: 'no description' */
441#define FM_STECFRMA2 0x0080 /* transmit end of chain of asyn. q2 */
442 /* SN3: reserved */
443#define FM_STEXDONS 0x0100 /* transmit until XDONE in syn. qu. */
444#define FM_STBFLA 0x0200 /* asynchr.-queue trans. buffer full */
445#define FM_STBFLS 0x0400 /* synchr.-queue transm. buffer full */
446#define FM_STXABRS 0x0800 /* synchr. queue transmit-abort */
447#define FM_STXABRA0 0x1000 /* asynchr. queue 0 transmit-abort */
448#define FM_STXABRA1 0x2000 /* asynchr. queue 1 transmit-abort */
449#define FM_STXABRA2 0x4000 /* asynchr. queue 2 transmit-abort */
450 /* SN3: reserved */
451#define FM_SXMTABT 0x8000 /* transmit abort */
452
453/*
454 * Status Register 1, Lower 16 Bits (ST1L)
455 */
456#define FM_SQLCKS 0x0001 /* queue lock for synchr. queue */
457#define FM_SQLCKA0 0x0002 /* queue lock for asynchr. queue 0 */
458#define FM_SQLCKA1 0x0004 /* queue lock for asynchr. queue 1 */
459#define FM_SQLCKA2 0x0008 /* queue lock for asynchr. queue 2 */
460 /* SN3: reserved */
461#define FM_STXINFLS 0x0010 /* transmit instruction full: syn. */
462 /* SN3: reserved */
463#define FM_STXINFLA0 0x0020 /* transmit instruction full: asyn.0 */
464 /* SN3: reserved */
465#define FM_STXINFLA1 0x0040 /* transmit instruction full: asyn.1 */
466 /* SN3: reserved */
467#define FM_STXINFLA2 0x0080 /* transmit instruction full: asyn.2 */
468 /* SN3: reserved */
469#define FM_SPCEPDS 0x0100 /* parity/coding error: syn. queue */
470#define FM_SPCEPDA0 0x0200 /* parity/coding error: asyn. queue0 */
471#define FM_SPCEPDA1 0x0400 /* parity/coding error: asyn. queue1 */
472#define FM_SPCEPDA2 0x0800 /* parity/coding error: asyn. queue2 */
473 /* SN3: reserved */
474#define FM_STBURS 0x1000 /* transmit buffer underrun: syn. q. */
475#define FM_STBURA0 0x2000 /* transmit buffer underrun: asyn.0 */
476#define FM_STBURA1 0x4000 /* transmit buffer underrun: asyn.1 */
477#define FM_STBURA2 0x8000 /* transmit buffer underrun: asyn.2 */
478 /* SN3: reserved */
479
480/*
481 * Status Register 2, Upper 16 Bits (ST2U)
482 */
483#define FM_SOTRBEC 0x0001 /* other beacon received */
484#define FM_SMYBEC 0x0002 /* my beacon received */
485#define FM_SBEC 0x0004 /* beacon state entered */
486#define FM_SLOCLM 0x0008 /* low claim received */
487#define FM_SHICLM 0x0010 /* high claim received */
488#define FM_SMYCLM 0x0020 /* my claim received */
489#define FM_SCLM 0x0040 /* claim state entered */
490#define FM_SERRSF 0x0080 /* error in special frame */
491#define FM_SNFSLD 0x0100 /* NP and FORMAC+ simultaneous load */
492#define FM_SRFRCTOV 0x0200 /* receive frame counter overflow */
493 /* SN3: reserved */
494#define FM_SRCVFRM 0x0400 /* receive frame */
495 /* SN3: reserved */
496#define FM_SRCVOVR 0x0800 /* receive FIFO overflow */
497#define FM_SRBFL 0x1000 /* receive buffer full */
498#define FM_SRABT 0x2000 /* receive abort */
499#define FM_SRBMT 0x4000 /* receive buffer empty */
500#define FM_SRCOMP 0x8000 /* receive complete. Nontag mode */
501
502/*
503 * Status Register 2, Lower 16 Bits (ST2L)
504 * Attention: SN3 docu shows these bits the other way around
505 */
506#define FM_SRES0 0x0001 /* reserved */
507#define FM_SESTRIPTK 0x0001 /* SN3: 'no description' */
508#define FM_STRTEXR 0x0002 /* TRT expired in claim | beacon st. */
509#define FM_SDUPCLM 0x0004 /* duplicate claim received */
510#define FM_SSIFG 0x0008 /* short interframe gap */
511#define FM_SFRMCTR 0x0010 /* frame counter overflow */
512#define FM_SERRCTR 0x0020 /* error counter overflow */
513#define FM_SLSTCTR 0x0040 /* lost counter overflow */
514#define FM_SPHINV 0x0080 /* PHY invalid */
515#define FM_SADET 0x0100 /* address detect */
516#define FM_SMISFRM 0x0200 /* missed frame */
517#define FM_STRTEXP 0x0400 /* TRT expired and late count > 0 */
518#define FM_STVXEXP 0x0800 /* TVX expired */
519#define FM_STKISS 0x1000 /* token issued */
520#define FM_STKERR 0x2000 /* token error */
521#define FM_SMULTDA 0x4000 /* multiple destination address */
522#define FM_SRNGOP 0x8000 /* ring operational */
523
524/*
525 * Supernet 3:
526 * Status Register 3, Upper 16 Bits (ST3U)
527 */
528#define FM_SRQUNLCK1 0x0001 /* receive queue unlocked queue 1 */
529#define FM_SRQUNLCK2 0x0002 /* receive queue unlocked queue 2 */
530#define FM_SRPERRQ1 0x0004 /* receive parity error rx queue 1 */
531#define FM_SRPERRQ2 0x0008 /* receive parity error rx queue 2 */
532 /* Bit 4-10: reserved */
533#define FM_SRCVOVR2 0x0800 /* receive FIFO overfull rx queue 2 */
534#define FM_SRBFL2 0x1000 /* receive buffer full rx queue 2 */
535#define FM_SRABT2 0x2000 /* receive abort rx queue 2 */
536#define FM_SRBMT2 0x4000 /* receive buf empty rx queue 2 */
537#define FM_SRCOMP2 0x8000 /* receive comp rx queue 2 */
538
539/*
540 * Supernet 3:
541 * Status Register 3, Lower 16 Bits (ST3L)
542 */
543#define FM_AF_BIST_DONE 0x0001 /* Address Filter BIST is done */
544#define FM_PLC_BIST_DONE 0x0002 /* internal PLC Bist is done */
545#define FM_PDX_BIST_DONE 0x0004 /* PDX BIST is done */
546 /* Bit 3: reserved */
547#define FM_SICAMDAMAT 0x0010 /* Status internal CAM DA match */
548#define FM_SICAMDAXACT 0x0020 /* Status internal CAM DA exact match */
549#define FM_SICAMSAMAT 0x0040 /* Status internal CAM SA match */
550#define FM_SICAMSAXACT 0x0080 /* Status internal CAM SA exact match */
551
552/*
553 * MAC State-Machine Register FM_STMCHN
554 */
555#define FM_MDRTAG 0x0004 /* tag bit of long word read */
556#define FM_SNPPND 0x0008 /* r/w from buffer mem. is pending */
557#define FM_TXSTAT 0x0070 /* transmitter state machine state */
558#define FM_RCSTAT 0x0380 /* receiver state machine state */
559#define FM_TM01 0x0c00 /* indicate token mode */
560#define FM_SIM 0x1000 /* indicate send immediate-mode */
561#define FM_REV 0xe000 /* FORMAC Plus revision number */
562
563/*
564 * Supernet 3
565 * Mode Register 3
566 */
567#define FM_MENRS 0x0001 /* Ena enhanced rec status encoding */
568#define FM_MENXS 0x0002 /* Ena enhanced xmit status encoding */
569#define FM_MENXCT 0x0004 /* Ena EXACT/INEXACT matching */
570#define FM_MENAFULL 0x0008 /* Ena enh QCTRL encoding for AFULL */
571#define FM_MEIND 0x0030 /* Ena enh A,C indicator settings */
572#define FM_MENQCTRL 0x0040 /* Ena enh QCTRL encoding */
573#define FM_MENRQAUNLCK 0x0080 /* Ena rec q auto unlock */
574#define FM_MENDAS 0x0100 /* Ena DAS connections by cntr MUX */
575#define FM_MENPLCCST 0x0200 /* Ena Counter Segm test in PLC blck */
576#define FM_MENSGLINT 0x0400 /* Ena Vectored Interrupt reading */
577#define FM_MENDRCV 0x0800 /* Ena dual receive queue operation */
578#define FM_MENFCLOC 0x3000 /* Ena FC location within frm data */
579#define FM_MENTRCMD 0x4000 /* Ena ASYNC1 xmit only after command */
580#define FM_MENTDLPBK 0x8000 /* Ena TDAT to RDAT lkoopback */
581
582/*
583 * Supernet 3
584 * Frame Selection Register
585 */
586#define FM_RECV1 0x000f /* options for receive queue 1 */
587#define FM_RCV1_ALL (0<<0) /* receive all frames */
588#define FM_RCV1_LLC (1<<0) /* rec all LLC frames */
589#define FM_RCV1_SMT (2<<0) /* rec all SMT frames */
590#define FM_RCV1_NSMT (3<<0) /* rec non-SMT frames */
591#define FM_RCV1_IMP (4<<0) /* rec Implementor frames */
592#define FM_RCV1_MAC (5<<0) /* rec all MAC frames */
593#define FM_RCV1_SLLC (6<<0) /* rec all sync LLC frames */
594#define FM_RCV1_ALLC (7<<0) /* rec all async LLC frames */
595#define FM_RCV1_VOID (8<<0) /* rec all void frames */
596#define FM_RCV1_ALSMT (9<<0) /* rec all async LLC & SMT frames */
597#define FM_RECV2 0x00f0 /* options for receive queue 2 */
598#define FM_RCV2_ALL (0<<4) /* receive all other frames */
599#define FM_RCV2_LLC (1<<4) /* rec all LLC frames */
600#define FM_RCV2_SMT (2<<4) /* rec all SMT frames */
601#define FM_RCV2_NSMT (3<<4) /* rec non-SMT frames */
602#define FM_RCV2_IMP (4<<4) /* rec Implementor frames */
603#define FM_RCV2_MAC (5<<4) /* rec all MAC frames */
604#define FM_RCV2_SLLC (6<<4) /* rec all sync LLC frames */
605#define FM_RCV2_ALLC (7<<4) /* rec all async LLC frames */
606#define FM_RCV2_VOID (8<<4) /* rec all void frames */
607#define FM_RCV2_ALSMT (9<<4) /* rec all async LLC & SMT frames */
608#define FM_ENXMTADSWAP 0x4000 /* enh rec addr swap (phys -> can) */
609#define FM_ENRCVADSWAP 0x8000 /* enh tx addr swap (can -> phys) */
610
611/*
612 * Supernet 3:
613 * Address Filter Command Register (AFCMD)
614 */
615#define FM_INST 0x0007 /* Address Filter Operation */
616#define FM_IINV_CAM (0<<0) /* Invalidate CAM */
617#define FM_IWRITE_CAM (1<<0) /* Write CAM */
618#define FM_IREAD_CAM (2<<0) /* Read CAM */
619#define FM_IRUN_BIST (3<<0) /* Run BIST */
620#define FM_IFIND (4<<0) /* Find */
621#define FM_IINV (5<<0) /* Invalidate */
622#define FM_ISKIP (6<<0) /* Skip */
623#define FM_ICL_SKIP (7<<0) /* Clear all SKIP bits */
624
625/*
626 * Supernet 3:
627 * Address Filter Status Register (AFSTAT)
628 */
629 /* Bit 0-4: reserved */
630#define FM_REV_NO 0x00e0 /* Revision Number of Address Filter */
631#define FM_BIST_DONE 0x0100 /* BIST complete */
632#define FM_EMPTY 0x0200 /* CAM empty */
633#define FM_ERROR 0x0400 /* Error (improper operation) */
634#define FM_MULT 0x0800 /* Multiple Match */
635#define FM_EXACT 0x1000 /* Exact Match */
636#define FM_FOUND 0x2000 /* Comparand found in CAM */
637#define FM_FULL 0x4000 /* CAM full */
638#define FM_DONE 0x8000 /* DONE indicator */
639
640/*
641 * Supernet 3:
642 * BIST Signature Register (AFBIST)
643 */
644#define AF_BIST_SIGNAT 0x0553 /* Address Filter BIST Signature */
645
646/*
647 * Supernet 3:
648 * Personality Register (AFPERS)
649 */
650#define FM_VALID 0x0001 /* CAM Entry Valid */
651#define FM_DA 0x0002 /* Destination Address */
652#define FM_DAX 0x0004 /* Destination Address Exact */
653#define FM_SA 0x0008 /* Source Address */
654#define FM_SAX 0x0010 /* Source Address Exact */
655#define FM_SKIP 0x0020 /* Skip this entry */
656
657/*
658 * instruction set for command register 1 (NPADDR6-0 = 0x00)
659 */
660#define FM_IRESET 0x01 /* software reset */
661#define FM_IRMEMWI 0x02 /* load Memory Data Reg., inc MARR */
662#define FM_IRMEMWO 0x03 /* load MDR from buffer memory, n.i. */
663#define FM_IIL 0x04 /* idle/listen */
664#define FM_ICL 0x05 /* claim/listen */
665#define FM_IBL 0x06 /* beacon/listen */
666#define FM_ILTVX 0x07 /* load TVX timer from TVX reg */
667#define FM_INRTM 0x08 /* nonrestricted token mode */
668#define FM_IENTM 0x09 /* enter nonrestricted token mode */
669#define FM_IERTM 0x0a /* enter restricted token mode */
670#define FM_IRTM 0x0b /* restricted token mode */
671#define FM_ISURT 0x0c /* send unrestricted token */
672#define FM_ISRT 0x0d /* send restricted token */
673#define FM_ISIM 0x0e /* enter send-immediate mode */
674#define FM_IESIM 0x0f /* exit send-immediate mode */
675#define FM_ICLLS 0x11 /* clear synchronous queue lock */
676#define FM_ICLLA0 0x12 /* clear asynchronous queue 0 lock */
677#define FM_ICLLA1 0x14 /* clear asynchronous queue 1 lock */
678#define FM_ICLLA2 0x18 /* clear asynchronous queue 2 lock */
679 /* SN3: reserved */
680#define FM_ICLLR 0x20 /* clear receive queue (SN3:1) lock */
681#define FM_ICLLR2 0x21 /* SN3: clear receive queue 2 lock */
682#define FM_ITRXBUS 0x22 /* SN3: Tristate X-Bus (SAS only) */
683#define FM_IDRXBUS 0x23 /* SN3: drive X-Bus */
684#define FM_ICLLAL 0x3f /* clear all queue locks */
685
686/*
687 * instruction set for command register 2 (NPADDR6-0 = 0x01)
688 */
689#define FM_ITRS 0x01 /* transmit synchronous queue */
690 /* SN3: reserved */
691#define FM_ITRA0 0x02 /* transmit asynchronous queue 0 */
692 /* SN3: reserved */
693#define FM_ITRA1 0x04 /* transmit asynchronous queue 1 */
694 /* SN3: reserved */
695#define FM_ITRA2 0x08 /* transmit asynchronous queue 2 */
696 /* SN3: reserved */
697#define FM_IACTR 0x10 /* abort current transmit activity */
698#define FM_IRSTQ 0x20 /* reset transmit queues */
699#define FM_ISTTB 0x30 /* set tag bit */
700#define FM_IERSF 0x40 /* enable receive single frame */
701 /* SN3: reserved */
702#define FM_ITR 0x50 /* SN3: Transmit Command */
703
704
705/*
706 * defines for PLC (Am79C864)
707 */
708
709/*
710 * PLC read/write (r/w) registers
711 */
712#define PL_CNTRL_A 0x00 /* control register A (r/w) */
713#define PL_CNTRL_B 0x01 /* control register B (r/w) */
714#define PL_INTR_MASK 0x02 /* interrupt mask (r/w) */
715#define PL_XMIT_VECTOR 0x03 /* transmit vector register (r/w) */
716#define PL_VECTOR_LEN 0x04 /* transmit vector length (r/w) */
717#define PL_LE_THRESHOLD 0x05 /* link error event threshold (r/w) */
718#define PL_C_MIN 0x06 /* minimum connect state time (r/w) */
719#define PL_TL_MIN 0x07 /* min. line state transmit t. (r/w) */
720#define PL_TB_MIN 0x08 /* minimum break time (r/w) */
721#define PL_T_OUT 0x09 /* signal timeout (r/w) */
722#define PL_CNTRL_C 0x0a /* control register C (r/w) */
723#define PL_LC_LENGTH 0x0b /* link confidence test time (r/w) */
724#define PL_T_SCRUB 0x0c /* scrub time = MAC TVX (r/w) */
725#define PL_NS_MAX 0x0d /* max. noise time before break (r/w)*/
726#define PL_TPC_LOAD_V 0x0e /* TPC timer load value (write only) */
727#define PL_TNE_LOAD_V 0x0f /* TNE timer load value (write only) */
728#define PL_STATUS_A 0x10 /* status register A (read only) */
729#define PL_STATUS_B 0x11 /* status register B (read only) */
730#define PL_TPC 0x12 /* timer for PCM (ro) [20.48 us] */
731#define PL_TNE 0x13 /* time of noise event [0.32 us] */
732#define PL_CLK_DIV 0x14 /* TNE clock divider (read only) */
733#define PL_BIST_SIGNAT 0x15 /* built in self test signature (ro)*/
734#define PL_RCV_VECTOR 0x16 /* receive vector reg. (read only) */
735#define PL_INTR_EVENT 0x17 /* interrupt event reg. (read only) */
736#define PL_VIOL_SYM_CTR 0x18 /* violation symbol count. (read o) */
737#define PL_MIN_IDLE_CTR 0x19 /* minimum idle counter (read only) */
738#define PL_LINK_ERR_CTR 0x1a /* link error event ctr.(read only) */
739#ifdef MOT_ELM
740#define PL_T_FOT_ASS 0x1e /* FOTOFF Assert Timer */
741#define PL_T_FOT_DEASS 0x1f /* FOTOFF Deassert Timer */
742#endif /* MOT_ELM */
743
744#ifdef MOT_ELM
745/*
746 * Special Quad-Elm Registers.
747 * A Quad-ELM consists of for ELMs and these additional registers.
748 */
749#define QELM_XBAR_W 0x80 /* Crossbar Control ELM W */
750#define QELM_XBAR_X 0x81 /* Crossbar Control ELM X */
751#define QELM_XBAR_Y 0x82 /* Crossbar Control ELM Y */
752#define QELM_XBAR_Z 0x83 /* Crossbar Control ELM Z */
753#define QELM_XBAR_P 0x84 /* Crossbar Control Bus P */
754#define QELM_XBAR_S 0x85 /* Crossbar Control Bus S */
755#define QELM_XBAR_R 0x86 /* Crossbar Control Bus R */
756#define QELM_WR_XBAR 0x87 /* Write the Crossbar now (write) */
757#define QELM_CTR_W 0x88 /* Counter W */
758#define QELM_CTR_X 0x89 /* Counter X */
759#define QELM_CTR_Y 0x8a /* Counter Y */
760#define QELM_CTR_Z 0x8b /* Counter Z */
761#define QELM_INT_MASK 0x8c /* Interrupt mask register */
762#define QELM_INT_DATA 0x8d /* Interrupt data (event) register */
763#define QELM_ELMB 0x00 /* Elm base */
764#define QELM_ELM_SIZE 0x20 /* ELM size */
765#endif /* MOT_ELM */
766/*
767 * PLC control register A (PL_CNTRL_A: log. addr. 0x00)
768 * It is used for timer configuration, specification of PCM MAINT state option,
769 * counter interrupt frequency, PLC data path config. and Built In Self Test.
770 */
771#define PL_RUN_BIST 0x0001 /* begin running its Built In Self T.*/
772#define PL_RF_DISABLE 0x0002 /* disable the Repeat Filter state m.*/
773#define PL_SC_REM_LOOP 0x0004 /* remote loopback path */
774#define PL_SC_BYPASS 0x0008 /* by providing a physical bypass */
775#define PL_LM_LOC_LOOP 0x0010 /* loop path just after elastic buff.*/
776#define PL_EB_LOC_LOOP 0x0020 /* loop path just prior to PDT/PDR IF*/
777#define PL_FOT_OFF 0x0040 /* assertion of /FOTOFF pin of PLC */
778#define PL_LOOPBACK 0x0080 /* it cause the /LPBCK pin ass. low */
779#define PL_MINI_CTR_INT 0x0100 /* partially contr. when bit is ass. */
780#define PL_VSYM_CTR_INT 0x0200 /* controls when int bit is asserted */
781#define PL_ENA_PAR_CHK 0x0400 /* enable parity check */
782#define PL_REQ_SCRUB 0x0800 /* limited access to scrub capability*/
783#define PL_TPC_16BIT 0x1000 /* causes the TPC as a 16 bit timer */
784#define PL_TNE_16BIT 0x2000 /* causes the TNE as a 16 bit timer */
785#define PL_NOISE_TIMER 0x4000 /* allows the noise timing function */
786
787/*
788 * PLC control register B (PL_CNTRL_B: log. addr. 0x01)
789 * It contains signals and requeste to direct the process of PCM and it is also
790 * used to control the Line State Match interrupt.
791 */
792#define PL_PCM_CNTRL 0x0003 /* control PCM state machine */
793#define PL_PCM_NAF (0) /* state is not affected */
794#define PL_PCM_START (1) /* goes to the BREAK state */
795#define PL_PCM_TRACE (2) /* goes to the TRACE state */
796#define PL_PCM_STOP (3) /* goes to the OFF state */
797
798#define PL_MAINT 0x0004 /* if OFF state --> MAINT state */
799#define PL_LONG 0x0008 /* perf. a long Link Confid.Test(LCT)*/
800#define PL_PC_JOIN 0x0010 /* if NEXT state --> JOIN state */
801
802#define PL_PC_LOOP 0x0060 /* loopback used in the LCT */
803#define PL_NOLCT (0<<5) /* no LCT is performed */
804#define PL_TPDR (1<<5) /* PCM asserts transmit PDR */
805#define PL_TIDLE (2<<5) /* PCM asserts transmit idle */
806#define PL_RLBP (3<<5) /* trans. PDR & remote loopb. path */
807
808#define PL_CLASS_S 0x0080 /* signif. that single att. station */
809
810#define PL_MAINT_LS 0x0700 /* line state while in the MAINT st. */
811#define PL_M_QUI0 (0<<8) /* transmit QUIET line state */
812#define PL_M_IDLE (1<<8) /* transmit IDLE line state */
813#define PL_M_HALT (2<<8) /* transmit HALT line state */
814#define PL_M_MASTR (3<<8) /* transmit MASTER line state */
815#define PL_M_QUI1 (4<<8) /* transmit QUIET line state */
816#define PL_M_QUI2 (5<<8) /* transmit QUIET line state */
817#define PL_M_TPDR (6<<8) /* tr. PHY_DATA requ.-symbol is tr.ed*/
818#define PL_M_QUI3 (7<<8) /* transmit QUIET line state */
819
820#define PL_MATCH_LS 0x7800 /* line state to be comp. with curr.*/
821#define PL_I_ANY (0<<11) /* Int. on any change in *_LINE_ST */
822#define PL_I_IDLE (1<<11) /* Interrupt on IDLE line state */
823#define PL_I_HALT (2<<11) /* Interrupt on HALT line state */
824#define PL_I_MASTR (4<<11) /* Interrupt on MASTER line state */
825#define PL_I_QUIET (8<<11) /* Interrupt on QUIET line state */
826
827#define PL_CONFIG_CNTRL 0x8000 /* control over scrub, byp. & loopb.*/
828
829/*
830 * PLC control register C (PL_CNTRL_C: log. addr. 0x0a)
831 * It contains the scrambling control registers (PLC-S only)
832 */
833#define PL_C_CIPHER_ENABLE (1<<0) /* enable scrambler */
834#define PL_C_CIPHER_LPBCK (1<<1) /* loopback scrambler */
835#define PL_C_SDOFF_ENABLE (1<<6) /* enable SDOFF timer */
836#define PL_C_SDON_ENABLE (1<<7) /* enable SDON timer */
837#ifdef MOT_ELM
838#define PL_C_FOTOFF_CTRL (3<<2) /* FOTOFF timer control */
839#define PL_C_FOTOFF_TIM (0<<2) /* FOTOFF use timer for (de)-assert */
840#define PL_C_FOTOFF_INA (2<<2) /* FOTOFF forced inactive */
841#define PL_C_FOTOFF_ACT (3<<2) /* FOTOFF forced active */
842#define PL_C_FOTOFF_SRCE (1<<4) /* FOTOFF source is PCM state != OFF */
843#define PL_C_RXDATA_EN (1<<5) /* Rec scr data forced to 0 */
844#define PL_C_SDNRZEN (1<<8) /* Monitor rec descr. data for act */
845#else /* nMOT_ELM */
846#define PL_C_FOTOFF_CTRL (3<<8) /* FOTOFF timer control */
847#define PL_C_FOTOFF_0 (0<<8) /* timer off */
848#define PL_C_FOTOFF_30 (1<<8) /* 30uS */
849#define PL_C_FOTOFF_50 (2<<8) /* 50uS */
850#define PL_C_FOTOFF_NEVER (3<<8) /* never */
851#define PL_C_SDON_TIMER (3<<10) /* SDON timer control */
852#define PL_C_SDON_084 (0<<10) /* 0.84 uS */
853#define PL_C_SDON_132 (1<<10) /* 1.32 uS */
854#define PL_C_SDON_252 (2<<10) /* 2.52 uS */
855#define PL_C_SDON_512 (3<<10) /* 5.12 uS */
856#define PL_C_SOFF_TIMER (3<<12) /* SDOFF timer control */
857#define PL_C_SOFF_076 (0<<12) /* 0.76 uS */
858#define PL_C_SOFF_132 (1<<12) /* 1.32 uS */
859#define PL_C_SOFF_252 (2<<12) /* 2.52 uS */
860#define PL_C_SOFF_512 (3<<12) /* 5.12 uS */
861#define PL_C_TSEL (3<<14) /* scrambler path select */
862#endif /* nMOT_ELM */
863
864/*
865 * PLC status register A (PL_STATUS_A: log. addr. 0x10)
866 * It is used to report status information to the Node Processor about the
867 * Line State Machine (LSM).
868 */
869#ifdef MOT_ELM
870#define PLC_INT_MASK 0xc000 /* ELM integration bits in status A */
871#define PLC_INT_C 0x0000 /* ELM Revision Band C */
872#define PLC_INT_CAMEL 0x4000 /* ELM integrated into CAMEL */
873#define PLC_INT_QE 0x8000 /* ELM integrated into Quad ELM */
874#define PLC_REV_MASK 0x3800 /* revision bits in status A */
875#define PLC_REVISION_B 0x0000 /* rev bits for ELM Rev B */
876#define PLC_REVISION_QA 0x0800 /* rev bits for ELM core in QELM-A */
877#else /* nMOT_ELM */
878#define PLC_REV_MASK 0xf800 /* revision bits in status A */
879#define PLC_REVISION_A 0x0000 /* revision bits for PLC */
880#define PLC_REVISION_S 0xf800 /* revision bits for PLC-S */
881#define PLC_REV_SN3 0x7800 /* revision bits for PLC-S in IFCP */
882#endif /* nMOT_ELM */
883#define PL_SYM_PR_CTR 0x0007 /* contains the LSM symbol pair Ctr. */
884#define PL_UNKN_LINE_ST 0x0008 /* unknown line state bit from LSM */
885#define PL_LSM_STATE 0x0010 /* state bit of LSM */
886
887#define PL_LINE_ST 0x00e0 /* contains recogn. line state of LSM*/
888#define PL_L_NLS (0<<5) /* noise line state */
889#define PL_L_ALS (1<<5) /* activ line state */
890#define PL_L_UND (2<<5) /* undefined */
891#define PL_L_ILS4 (3<<5) /* idle l. s. (after 4 idle symbols) */
892#define PL_L_QLS (4<<5) /* quiet line state */
893#define PL_L_MLS (5<<5) /* master line state */
894#define PL_L_HLS (6<<5) /* halt line state */
895#define PL_L_ILS16 (7<<5) /* idle line state (after 16 idle s.)*/
896
897#define PL_PREV_LINE_ST 0x0300 /* value of previous line state */
898#define PL_P_QLS (0<<8) /* quiet line state */
899#define PL_P_MLS (1<<8) /* master line state */
900#define PL_P_HLS (2<<8) /* halt line state */
901#define PL_P_ILS16 (3<<8) /* idle line state (after 16 idle s.)*/
902
903#define PL_SIGNAL_DET 0x0400 /* 1=that signal detect is deasserted*/
904
905
906/*
907 * PLC status register B (PL_STATUS_B: log. addr. 0x11)
908 * It contains signals and status from the repeat filter and PCM state machine.
909 */
910#define PL_BREAK_REASON 0x0007 /* reason for PCM state mach.s to br.*/
911#define PL_B_NOT (0) /* PCM SM has not gone to BREAK state*/
912#define PL_B_PCS (1) /* PC_Start issued */
913#define PL_B_TPC (2) /* TPC timer expired after T_OUT */
914#define PL_B_TNE (3) /* TNE timer expired after NS_MAX */
915#define PL_B_QLS (4) /* quit line state detected */
916#define PL_B_ILS (5) /* idle line state detected */
917#define PL_B_HLS (6) /* halt line state detected */
918
919#define PL_TCF 0x0008 /* transmit code flag (start exec.) */
920#define PL_RCF 0x0010 /* receive code flag (start exec.) */
921#define PL_LSF 0x0020 /* line state flag (l.s. has been r.)*/
922#define PL_PCM_SIGNAL 0x0040 /* indic. that XMIT_VECTOR hb.written*/
923
924#define PL_PCM_STATE 0x0780 /* state bits of PCM state machine */
925#define PL_PC0 (0<<7) /* OFF - when /RST or PCM_CNTRL */
926#define PL_PC1 (1<<7) /* BREAK - entry point in start PCM*/
927#define PL_PC2 (2<<7) /* TRACE - to localize stuck Beacon*/
928#define PL_PC3 (3<<7) /* CONNECT - synchronize ends of conn*/
929#define PL_PC4 (4<<7) /* NEXT - to separate the signalng*/
930#define PL_PC5 (5<<7) /* SIGNAL - PCM trans/rec. bit infos*/
931#define PL_PC6 (6<<7) /* JOIN - 1. state to activ conn. */
932#define PL_PC7 (7<<7) /* VERIFY - 2. - " - (3. ACTIVE) */
933#define PL_PC8 (8<<7) /* ACTIVE - PHY has been incorporated*/
934#define PL_PC9 (9<<7) /* MAINT - for test purposes or so
935 that PCM op. completely in softw. */
936
937#define PL_PCI_SCRUB 0x0800 /* scrubbing function is being exec. */
938
939#define PL_PCI_STATE 0x3000 /* Physical Connect. Insertion SM */
940#define PL_CI_REMV (0<<12) /* REMOVED */
941#define PL_CI_ISCR (1<<12) /* INSERT_SCRUB */
942#define PL_CI_RSCR (2<<12) /* REMOVE_SCRUB */
943#define PL_CI_INS (3<<12) /* INSERTED */
944
945#define PL_RF_STATE 0xc000 /* state bit of repeate filter SM */
946#define PL_RF_REPT (0<<14) /* REPEAT */
947#define PL_RF_IDLE (1<<14) /* IDLE */
948#define PL_RF_HALT1 (2<<14) /* HALT1 */
949#define PL_RF_HALT2 (3<<14) /* HALT2 */
950
951
952/*
953 * PLC interrupt event register (PL_INTR_EVENT: log. addr. 0x17)
954 * It is read only and is clearde whenever it is read!
955 * It is used by the PLC to report events to the node processor.
956 */
957#define PL_PARITY_ERR 0x0001 /* p. error h.b.detected on TX9-0 inp*/
958#define PL_LS_MATCH 0x0002 /* l.s.== l.s. PLC_CNTRL_B's MATCH_LS*/
959#define PL_PCM_CODE 0x0004 /* transmit&receive | LCT complete */
960#define PL_TRACE_PROP 0x0008 /* master l.s. while PCM ACTIV|TRACE */
961#define PL_SELF_TEST 0x0010 /* QUIET|HALT while PCM in TRACE st. */
962#define PL_PCM_BREAK 0x0020 /* PCM has entered the BREAK state */
963#define PL_PCM_ENABLED 0x0040 /* asserted SC_JOIN, scrub. & ACTIV */
964#define PL_TPC_EXPIRED 0x0080 /* TPC timer reached zero */
965#define PL_TNE_EXPIRED 0x0100 /* TNE timer reached zero */
966#define PL_EBUF_ERR 0x0200 /* elastic buff. det. over-|underflow*/
967#define PL_PHYINV 0x0400 /* physical layer invalid signal */
968#define PL_VSYM_CTR 0x0800 /* violation symbol counter has incr.*/
969#define PL_MINI_CTR 0x1000 /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/
970#define PL_LE_CTR 0x2000 /* link error event counter */
971#define PL_LSDO 0x4000 /* SDO input pin changed to a 1 */
972#define PL_NP_ERR 0x8000 /* NP has requested to r/w an inv. r.*/
973
974/*
975 * The PLC interrupt mask register (PL_INTR_MASK: log. addr. 0x02) constr. is
976 * equal PL_INTR_EVENT register.
977 * For each set bit, the setting of corresponding bit generate an int to NP.
978 */
979
980#ifdef MOT_ELM
981/*
982 * Quad ELM Crosbar Control register values (QELM_XBAR_?)
983 */
984#define QELM_XOUT_IDLE 0x0000 /* Idles/Passthrough */
985#define QELM_XOUT_P 0x0001 /* Output to: Bus P */
986#define QELM_XOUT_S 0x0002 /* Output to: Bus S */
987#define QELM_XOUT_R 0x0003 /* Output to: Bus R */
988#define QELM_XOUT_W 0x0004 /* Output to: ELM W */
989#define QELM_XOUT_X 0x0005 /* Output to: ELM X */
990#define QELM_XOUT_Y 0x0006 /* Output to: ELM Y */
991#define QELM_XOUT_Z 0x0007 /* Output to: ELM Z */
992
993/*
994 * Quad ELM Interrupt data and event registers.
995 */
996#define QELM_NP_ERR (1<<15) /* Node Processor Error */
997#define QELM_COUNT_Z (1<<7) /* Counter Z Interrupt */
998#define QELM_COUNT_Y (1<<6) /* Counter Y Interrupt */
999#define QELM_COUNT_X (1<<5) /* Counter X Interrupt */
1000#define QELM_COUNT_W (1<<4) /* Counter W Interrupt */
1001#define QELM_ELM_Z (1<<3) /* ELM Z Interrupt */
1002#define QELM_ELM_Y (1<<2) /* ELM Y Interrupt */
1003#define QELM_ELM_X (1<<1) /* ELM X Interrupt */
1004#define QELM_ELM_W (1<<0) /* ELM W Interrupt */
1005#endif /* MOT_ELM */
1006/*
1007 * PLC Timing Parameters
1008 */
1009#define TP_C_MIN 0xff9c /* 2 ms */
1010#define TP_TL_MIN 0xfff0 /* 0.3 ms */
1011#define TP_TB_MIN 0xff10 /* 5 ms */
1012#define TP_T_OUT 0xd9db /* 200 ms */
1013#define TP_LC_LENGTH 0xf676 /* 50 ms */
1014#define TP_LC_LONGLN 0xa0a2 /* 500 ms */
1015#define TP_T_SCRUB 0xff6d /* 3.5 ms */
1016#define TP_NS_MAX 0xf021 /* 1.3 ms */
1017
1018/*
1019 * BIST values
1020 */
1021#define PLC_BIST 0x6ecd /* BIST signature for PLC */
1022#define PLCS_BIST 0x5b6b /* BIST signature for PLC-S */
1023#define PLC_ELM_B_BIST 0x6ecd /* BIST signature of ELM Rev. B */
1024#define PLC_ELM_D_BIST 0x5b6b /* BIST signature of ELM Rev. D */
1025#define PLC_CAM_A_BIST 0x9e75 /* BIST signature of CAMEL Rev. A */
1026#define PLC_CAM_B_BIST 0x5b6b /* BIST signature of CAMEL Rev. B */
1027#define PLC_IFD_A_BIST 0x9e75 /* BIST signature of IFDDI Rev. A */
1028#define PLC_IFD_B_BIST 0x5b6b /* BIST signature of IFDDI Rev. B */
1029#define PLC_QELM_A_BIST 0x5b6b /* BIST signature of QELM Rev. A */
1030
1031/*
1032 FDDI board recources
1033 */
1034
1035/*
1036 * request register array (log. addr: RQA_A + a<<1 {a=0..7}) write only.
1037 * It specifies to FORMAC+ the type of buffer memory access the host requires.
1038 */
1039#define RQ_NOT 0 /* not request */
1040#define RQ_RES 1 /* reserved */
1041#define RQ_SFW 2 /* special frame write */
1042#define RQ_RRQ 3 /* read request: receive queue */
1043#define RQ_WSQ 4 /* write request: synchronous queue */
1044#define RQ_WA0 5 /* write requ.: asynchronous queue 0 */
1045#define RQ_WA1 6 /* write requ.: asynchronous queue 1 */
1046#define RQ_WA2 7 /* write requ.: asynchronous queue 2 */
1047
1048#define SZ_LONG (sizeof(long))
1049
1050/*
1051 * FDDI defaults
1052 * NOTE : In the ANSI docs, times are specified in units of "symbol time".
1053 * AMD chips use BCLK as unit. 1 BCKL == 2 symbols
1054 */
1055#define COMPLREF ((u_long)32*256*256) /* two's complement 21 bit */
1056#define MSTOBCLK(x) ((u_long)(x)*12500L)
1057#define MSTOTVX(x) (((u_long)(x)*1000L)/80/255)
1058
1059#endif /* _SUPERNET_ */
diff --git a/drivers/net/skfp/h/targethw.h b/drivers/net/skfp/h/targethw.h
deleted file mode 100644
index 626dc7263591..000000000000
--- a/drivers/net/skfp/h/targethw.h
+++ /dev/null
@@ -1,138 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#ifndef _TARGETHW_
16#define _TARGETHW_
17
18 /*
19 * PCI Watermark definition
20 */
21#ifdef PCI
22#define RX_WATERMARK 24
23#define TX_WATERMARK 24
24#define SK_ML_ID_1 0x20
25#define SK_ML_ID_2 0x30
26#endif
27
28#include "h/skfbi.h"
29#ifndef TAG_MODE
30#include "h/fplus.h"
31#else
32#include "h/fplustm.h"
33#endif
34
35#ifndef HW_PTR
36#define HW_PTR void __iomem *
37#endif
38
39#ifdef MULT_OEM
40#define OI_STAT_LAST 0 /* end of OEM data base */
41#define OI_STAT_PRESENT 1 /* entry present but not empty */
42#define OI_STAT_VALID 2 /* holds valid ID, but is not active */
43#define OI_STAT_ACTIVE 3 /* holds valid ID, entry is active */
44 /* active = adapter is supported */
45
46/* Memory representation of IDs must match representation in adapter. */
47struct s_oem_ids {
48 u_char oi_status ; /* Stat: last, present, valid, active */
49 u_char oi_mark[5] ; /* "PID00" .. "PID07" .. */
50 u_char oi_id[4] ; /* id bytes, representation as */
51 /* defined by hardware, */
52#ifdef PCI
53 u_char oi_sub_id[4] ; /* sub id bytes, representation as */
54 /* defined by hardware, */
55#endif
56} ;
57#endif /* MULT_OEM */
58
59
60struct s_smt_hw {
61 /*
62 * global
63 */
64 HW_PTR iop ; /* IO base address */
65 short dma ; /* DMA channel */
66 short irq ; /* IRQ level */
67 short eprom ; /* FLASH prom */
68
69#ifndef SYNC
70 u_short n_a_send ; /* pending send requests */
71#endif
72
73#if defined(PCI)
74 short slot ; /* slot number */
75 short max_slots ; /* maximum number of slots */
76 short wdog_used ; /* TRUE if the watch dog is used */
77#endif
78
79#ifdef PCI
80 u_short pci_handle ; /* handle to access the BIOS func */
81 u_long is_imask ; /* int maske for the int source reg */
82 u_long phys_mem_addr ; /* physical memory address */
83 u_short mc_dummy ; /* work around for MC compiler bug */
84 /*
85 * state of the hardware
86 */
87 u_short hw_state ; /* started or stopped */
88
89#define STARTED 1
90#define STOPPED 0
91
92 int hw_is_64bit ; /* does we have a 64 bit adapter */
93#endif
94
95#ifdef TAG_MODE
96 u_long pci_fix_value ; /* value parsed by PCIFIX */
97#endif
98
99 /*
100 * hwt.c
101 */
102 u_long t_start ; /* HWT start */
103 u_long t_stop ; /* HWT stop */
104 u_short timer_activ ; /* HWT timer active */
105
106 /*
107 * PIC
108 */
109 u_char pic_a1 ;
110 u_char pic_21 ;
111
112 /*
113 * GENERIC ; do not modify beyond this line
114 */
115
116 /*
117 * physical and canonical address
118 */
119 struct fddi_addr fddi_home_addr ;
120 struct fddi_addr fddi_canon_addr ;
121 struct fddi_addr fddi_phys_addr ;
122
123 /*
124 * mac variables
125 */
126 struct mac_parameter mac_pa ; /* tmin, tmax, tvx, treq .. */
127 struct mac_counter mac_ct ; /* recv., lost, error */
128 u_short mac_ring_is_up ; /* ring is up flag */
129
130 struct s_smt_fp fp ; /* formac+ */
131
132#ifdef MULT_OEM
133 struct s_oem_ids *oem_id ; /* pointer to selected id */
134 int oem_min_status ; /* IDs to take care of */
135#endif /* MULT_OEM */
136
137} ;
138#endif
diff --git a/drivers/net/skfp/h/targetos.h b/drivers/net/skfp/h/targetos.h
deleted file mode 100644
index 5d940e7b8ea0..000000000000
--- a/drivers/net/skfp/h/targetos.h
+++ /dev/null
@@ -1,165 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15/*
16 * Operating system specific definitions for driver and
17 * hardware module.
18 */
19
20#ifndef TARGETOS_H
21#define TARGETOS_H
22
23
24//-------- those should go into include/linux/pci.h
25#define PCI_VENDOR_ID_SK 0x1148
26#define PCI_DEVICE_ID_SK_FP 0x4000
27//--------
28
29
30
31//-------- those should go into include/linux/if_fddi.h
32#define FDDI_MAC_HDR_LEN 13
33
34#define FDDI_RII 0x01 /* routing information bit */
35#define FDDI_RCF_DIR_BIT 0x80
36#define FDDI_RCF_LEN_MASK 0x1f
37#define FDDI_RCF_BROADCAST 0x8000
38#define FDDI_RCF_LIMITED_BROADCAST 0xA000
39#define FDDI_RCF_FRAME2K 0x20
40#define FDDI_RCF_FRAME4K 0x30
41//--------
42
43
44#undef ADDR
45
46#include <asm/io.h>
47#include <linux/netdevice.h>
48#include <linux/fddidevice.h>
49#include <linux/skbuff.h>
50#include <linux/pci.h>
51#include <linux/init.h>
52
53// is redefined by linux, but we need our definition
54#undef ADDR
55#ifdef MEM_MAPPED_IO
56#define ADDR(a) (smc->hw.iop+(a))
57#else
58#define ADDR(a) (((a)>>7) ? (outp(smc->hw.iop+B0_RAP,(a)>>7), (smc->hw.iop+( ((a)&0x7F) | ((a)>>7 ? 0x80:0)) )) : (smc->hw.iop+(((a)&0x7F)|((a)>>7 ? 0x80:0))))
59#endif
60
61#include "h/hwmtm.h"
62
63#define TRUE 1
64#define FALSE 0
65
66// HWM Definitions
67// -----------------------
68#define FDDI_TRACE(string, arg1, arg2, arg3) // Performance analysis.
69#ifdef PCI
70#define NDD_TRACE(string, arg1, arg2, arg3) // Performance analysis.
71#endif // PCI
72#define SMT_PAGESIZE PAGE_SIZE // Size of a memory page (power of 2).
73// -----------------------
74
75
76// SMT Definitions
77// -----------------------
78#define TICKS_PER_SECOND HZ
79#define SMC_VERSION 1
80// -----------------------
81
82
83// OS-Driver Definitions
84// -----------------------
85#define NO_ADDRESS 0xffe0 /* No Device (I/O) Address */
86#define SKFP_MAX_NUM_BOARDS 8 /* maximum number of PCI boards */
87
88#define SK_BUS_TYPE_PCI 0
89#define SK_BUS_TYPE_EISA 1
90
91#define FP_IO_LEN 256 /* length of IO area used */
92
93#define u8 unsigned char
94#define u16 unsigned short
95#define u32 unsigned int
96
97#define MAX_TX_QUEUE_LEN 20 // number of packets queued by driver
98#define MAX_FRAME_SIZE 4550
99
100#define RX_LOW_WATERMARK NUM_RECEIVE_BUFFERS / 2
101#define TX_LOW_WATERMARK NUM_TRANSMIT_BUFFERS - 2
102
103/*
104** Include the IOCTL stuff
105*/
106#include <linux/sockios.h>
107
108#define SKFPIOCTL SIOCDEVPRIVATE
109
110struct s_skfp_ioctl {
111 unsigned short cmd; /* Command to run */
112 unsigned short len; /* Length of the data buffer */
113 unsigned char __user *data; /* Pointer to the data buffer */
114};
115
116/*
117** Recognised ioctl commands for the driver
118*/
119#define SKFP_GET_STATS 0x05 /* Get the driver statistics */
120#define SKFP_CLR_STATS 0x06 /* Zero out the driver statistics */
121
122// The per-adapter driver structure
123struct s_smt_os {
124 struct net_device *dev;
125 struct net_device *next_module;
126 u32 bus_type; /* bus type (0 == PCI, 1 == EISA) */
127 struct pci_dev pdev; /* PCI device structure */
128
129 unsigned long base_addr;
130 unsigned char factory_mac_addr[8];
131 ulong SharedMemSize;
132 ulong SharedMemHeap;
133 void* SharedMemAddr;
134 dma_addr_t SharedMemDMA;
135
136 ulong QueueSkb;
137 struct sk_buff_head SendSkbQueue;
138
139 ulong MaxFrameSize;
140 u8 ResetRequested;
141
142 // MAC statistics structure
143 struct fddi_statistics MacStat;
144
145 // receive into this local buffer if no skb available
146 // data will be not valid, because multiple RxDs can
147 // point here at the same time, it must be at least
148 // MAX_FRAME_SIZE bytes in size
149 unsigned char *LocalRxBuffer;
150 dma_addr_t LocalRxBufferDMA;
151
152 // Version (required by SMT module).
153 u_long smc_version ;
154
155 // Required by Hardware Module (HWM).
156 struct hw_modul hwm ;
157
158 // For SMP-savety
159 spinlock_t DriverLock;
160
161};
162
163typedef struct s_smt_os skfddi_priv;
164
165#endif // _TARGETOS_
diff --git a/drivers/net/skfp/h/types.h b/drivers/net/skfp/h/types.h
deleted file mode 100644
index 5a3bf8378f9e..000000000000
--- a/drivers/net/skfp/h/types.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * The information in this file is provided "AS IS" without warranty.
12 *
13 ******************************************************************************/
14
15#include <linux/types.h>
16/*
17 ----------------------
18 Basic SMT system types
19 ----------------------
20*/
21#ifndef _TYPES_
22#define _TYPES_
23
24#define _packed
25#ifndef far
26#define far
27#endif
28#ifndef _far
29#define _far
30#endif
31
32#define inp(p) ioread8(p)
33#define inpw(p) ioread16(p)
34#define inpd(p) ioread32(p)
35#define outp(p,c) iowrite8(c,p)
36#define outpw(p,s) iowrite16(s,p)
37#define outpd(p,l) iowrite32(l,p)
38
39#endif /* _TYPES_ */
diff --git a/drivers/net/skfp/hwmtm.c b/drivers/net/skfp/hwmtm.c
deleted file mode 100644
index e26398b5a7dc..000000000000
--- a/drivers/net/skfp/hwmtm.c
+++ /dev/null
@@ -1,2178 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17#ifndef lint
18static char const ID_sccs[] = "@(#)hwmtm.c 1.40 99/05/31 (C) SK" ;
19#endif
20
21#define HWMTM
22
23#ifndef FDDI
24#define FDDI
25#endif
26
27#include "h/types.h"
28#include "h/fddi.h"
29#include "h/smc.h"
30#include "h/supern_2.h"
31#include "h/skfbiinc.h"
32
33/*
34 -------------------------------------------------------------
35 DOCUMENTATION
36 -------------------------------------------------------------
37 BEGIN_MANUAL_ENTRY(DOCUMENTATION)
38
39 T B D
40
41 END_MANUAL_ENTRY
42*/
43/*
44 -------------------------------------------------------------
45 LOCAL VARIABLES:
46 -------------------------------------------------------------
47*/
48#ifdef COMMON_MB_POOL
49static SMbuf *mb_start = 0 ;
50static SMbuf *mb_free = 0 ;
51static int mb_init = FALSE ;
52static int call_count = 0 ;
53#endif
54
55/*
56 -------------------------------------------------------------
57 EXTERNE VARIABLES:
58 -------------------------------------------------------------
59*/
60
61#ifdef DEBUG
62#ifndef DEBUG_BRD
63extern struct smt_debug debug ;
64#endif
65#endif
66
67#ifdef NDIS_OS2
68extern u_char offDepth ;
69extern u_char force_irq_pending ;
70#endif
71
72/*
73 -------------------------------------------------------------
74 LOCAL FUNCTIONS:
75 -------------------------------------------------------------
76*/
77
78static void queue_llc_rx(struct s_smc *smc, SMbuf *mb);
79static void smt_to_llc(struct s_smc *smc, SMbuf *mb);
80static void init_txd_ring(struct s_smc *smc);
81static void init_rxd_ring(struct s_smc *smc);
82static void queue_txd_mb(struct s_smc *smc, SMbuf *mb);
83static u_long init_descr_ring(struct s_smc *smc, union s_fp_descr volatile *start,
84 int count);
85static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue);
86static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue);
87static SMbuf* get_llc_rx(struct s_smc *smc);
88static SMbuf* get_txd_mb(struct s_smc *smc);
89static void mac_drv_clear_txd(struct s_smc *smc);
90
91/*
92 -------------------------------------------------------------
93 EXTERNAL FUNCTIONS:
94 -------------------------------------------------------------
95*/
96/* The external SMT functions are listed in cmtdef.h */
97
98extern void* mac_drv_get_space(struct s_smc *smc, unsigned int size);
99extern void* mac_drv_get_desc_mem(struct s_smc *smc, unsigned int size);
100extern void mac_drv_fill_rxd(struct s_smc *smc);
101extern void mac_drv_tx_complete(struct s_smc *smc,
102 volatile struct s_smt_fp_txd *txd);
103extern void mac_drv_rx_complete(struct s_smc *smc,
104 volatile struct s_smt_fp_rxd *rxd,
105 int frag_count, int len);
106extern void mac_drv_requeue_rxd(struct s_smc *smc,
107 volatile struct s_smt_fp_rxd *rxd,
108 int frag_count);
109extern void mac_drv_clear_rxd(struct s_smc *smc,
110 volatile struct s_smt_fp_rxd *rxd, int frag_count);
111
112#ifdef USE_OS_CPY
113extern void hwm_cpy_rxd2mb(void);
114extern void hwm_cpy_txd2mb(void);
115#endif
116
117#ifdef ALL_RX_COMPLETE
118extern void mac_drv_all_receives_complete(void);
119#endif
120
121extern u_long mac_drv_virt2phys(struct s_smc *smc, void *virt);
122extern u_long dma_master(struct s_smc *smc, void *virt, int len, int flag);
123
124#ifdef NDIS_OS2
125extern void post_proc(void);
126#else
127extern void dma_complete(struct s_smc *smc, volatile union s_fp_descr *descr,
128 int flag);
129#endif
130
131extern int mac_drv_rx_init(struct s_smc *smc, int len, int fc, char *look_ahead,
132 int la_len);
133
134/*
135 -------------------------------------------------------------
136 PUBLIC FUNCTIONS:
137 -------------------------------------------------------------
138*/
139void process_receive(struct s_smc *smc);
140void fddi_isr(struct s_smc *smc);
141void smt_free_mbuf(struct s_smc *smc, SMbuf *mb);
142void init_driver_fplus(struct s_smc *smc);
143void mac_drv_rx_mode(struct s_smc *smc, int mode);
144void init_fddi_driver(struct s_smc *smc, u_char *mac_addr);
145void mac_drv_clear_tx_queue(struct s_smc *smc);
146void mac_drv_clear_rx_queue(struct s_smc *smc);
147void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
148 int frame_status);
149void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
150 int frame_status);
151
152int mac_drv_init(struct s_smc *smc);
153int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
154 int frame_status);
155
156u_int mac_drv_check_space(void);
157
158SMbuf* smt_get_mbuf(struct s_smc *smc);
159
160#ifdef DEBUG
161 void mac_drv_debug_lev(void);
162#endif
163
164/*
165 -------------------------------------------------------------
166 MACROS:
167 -------------------------------------------------------------
168*/
169#ifndef UNUSED
170#ifdef lint
171#define UNUSED(x) (x) = (x)
172#else
173#define UNUSED(x)
174#endif
175#endif
176
177#ifdef USE_CAN_ADDR
178#define MA smc->hw.fddi_canon_addr.a
179#define GROUP_ADDR_BIT 0x01
180#else
181#define MA smc->hw.fddi_home_addr.a
182#define GROUP_ADDR_BIT 0x80
183#endif
184
185#define RXD_TXD_COUNT (HWM_ASYNC_TXD_COUNT+HWM_SYNC_TXD_COUNT+\
186 SMT_R1_RXD_COUNT+SMT_R2_RXD_COUNT)
187
188#ifdef MB_OUTSIDE_SMC
189#define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd) +\
190 MAX_MBUF*sizeof(SMbuf))
191#define EXT_VIRT_MEM_2 ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
192#else
193#define EXT_VIRT_MEM ((RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd))
194#endif
195
196 /*
197 * define critical read for 16 Bit drivers
198 */
199#if defined(NDIS_OS2) || defined(ODI2)
200#define CR_READ(var) ((var) & 0xffff0000 | ((var) & 0xffff))
201#else
202#define CR_READ(var) (__le32)(var)
203#endif
204
205#define IMASK_SLOW (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
206 IS_MINTR1 | IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
207 IS_R1_C | IS_XA_C | IS_XS_C)
208
209/*
210 -------------------------------------------------------------
211 INIT- AND SMT FUNCTIONS:
212 -------------------------------------------------------------
213*/
214
215
216/*
217 * BEGIN_MANUAL_ENTRY(mac_drv_check_space)
218 * u_int mac_drv_check_space()
219 *
220 * function DOWNCALL (drvsr.c)
221 * This function calculates the needed non virtual
222 * memory for MBufs, RxD and TxD descriptors etc.
223 * needed by the driver.
224 *
225 * return u_int memory in bytes
226 *
227 * END_MANUAL_ENTRY
228 */
229u_int mac_drv_check_space(void)
230{
231#ifdef MB_OUTSIDE_SMC
232#ifdef COMMON_MB_POOL
233 call_count++ ;
234 if (call_count == 1) {
235 return EXT_VIRT_MEM;
236 }
237 else {
238 return EXT_VIRT_MEM_2;
239 }
240#else
241 return EXT_VIRT_MEM;
242#endif
243#else
244 return 0;
245#endif
246}
247
248/*
249 * BEGIN_MANUAL_ENTRY(mac_drv_init)
250 * void mac_drv_init(smc)
251 *
252 * function DOWNCALL (drvsr.c)
253 * In this function the hardware module allocates it's
254 * memory.
255 * The operating system dependent module should call
256 * mac_drv_init once, after the adatper is detected.
257 * END_MANUAL_ENTRY
258 */
259int mac_drv_init(struct s_smc *smc)
260{
261 if (sizeof(struct s_smt_fp_rxd) % 16) {
262 SMT_PANIC(smc,HWM_E0001,HWM_E0001_MSG) ;
263 }
264 if (sizeof(struct s_smt_fp_txd) % 16) {
265 SMT_PANIC(smc,HWM_E0002,HWM_E0002_MSG) ;
266 }
267
268 /*
269 * get the required memory for the RxDs and TxDs
270 */
271 if (!(smc->os.hwm.descr_p = (union s_fp_descr volatile *)
272 mac_drv_get_desc_mem(smc,(u_int)
273 (RXD_TXD_COUNT+1)*sizeof(struct s_smt_fp_txd)))) {
274 return 1; /* no space the hwm modul can't work */
275 }
276
277 /*
278 * get the memory for the SMT MBufs
279 */
280#ifndef MB_OUTSIDE_SMC
281 smc->os.hwm.mbuf_pool.mb_start=(SMbuf *)(&smc->os.hwm.mbuf_pool.mb[0]) ;
282#else
283#ifndef COMMON_MB_POOL
284 if (!(smc->os.hwm.mbuf_pool.mb_start = (SMbuf *) mac_drv_get_space(smc,
285 MAX_MBUF*sizeof(SMbuf)))) {
286 return 1; /* no space the hwm modul can't work */
287 }
288#else
289 if (!mb_start) {
290 if (!(mb_start = (SMbuf *) mac_drv_get_space(smc,
291 MAX_MBUF*sizeof(SMbuf)))) {
292 return 1; /* no space the hwm modul can't work */
293 }
294 }
295#endif
296#endif
297 return 0;
298}
299
300/*
301 * BEGIN_MANUAL_ENTRY(init_driver_fplus)
302 * init_driver_fplus(smc)
303 *
304 * Sets hardware modul specific values for the mode register 2
305 * (e.g. the byte alignment for the received frames, the position of the
306 * least significant byte etc.)
307 * END_MANUAL_ENTRY
308 */
309void init_driver_fplus(struct s_smc *smc)
310{
311 smc->hw.fp.mdr2init = FM_LSB | FM_BMMODE | FM_ENNPRQ | FM_ENHSRQ | 3 ;
312
313#ifdef PCI
314 smc->hw.fp.mdr2init |= FM_CHKPAR | FM_PARITY ;
315#endif
316 smc->hw.fp.mdr3init = FM_MENRQAUNLCK | FM_MENRS ;
317
318#ifdef USE_CAN_ADDR
319 /* enable address bit swapping */
320 smc->hw.fp.frselreg_init = FM_ENXMTADSWAP | FM_ENRCVADSWAP ;
321#endif
322}
323
324static u_long init_descr_ring(struct s_smc *smc,
325 union s_fp_descr volatile *start,
326 int count)
327{
328 int i ;
329 union s_fp_descr volatile *d1 ;
330 union s_fp_descr volatile *d2 ;
331 u_long phys ;
332
333 DB_GEN("descr ring starts at = %x ",(void *)start,0,3) ;
334 for (i=count-1, d1=start; i ; i--) {
335 d2 = d1 ;
336 d1++ ; /* descr is owned by the host */
337 d2->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
338 d2->r.rxd_next = &d1->r ;
339 phys = mac_drv_virt2phys(smc,(void *)d1) ;
340 d2->r.rxd_nrdadr = cpu_to_le32(phys) ;
341 }
342 DB_GEN("descr ring ends at = %x ",(void *)d1,0,3) ;
343 d1->r.rxd_rbctrl = cpu_to_le32(BMU_CHECK) ;
344 d1->r.rxd_next = &start->r ;
345 phys = mac_drv_virt2phys(smc,(void *)start) ;
346 d1->r.rxd_nrdadr = cpu_to_le32(phys) ;
347
348 for (i=count, d1=start; i ; i--) {
349 DRV_BUF_FLUSH(&d1->r,DDI_DMA_SYNC_FORDEV) ;
350 d1++;
351 }
352 return phys;
353}
354
355static void init_txd_ring(struct s_smc *smc)
356{
357 struct s_smt_fp_txd volatile *ds ;
358 struct s_smt_tx_queue *queue ;
359 u_long phys ;
360
361 /*
362 * initialize the transmit descriptors
363 */
364 ds = (struct s_smt_fp_txd volatile *) ((char *)smc->os.hwm.descr_p +
365 SMT_R1_RXD_COUNT*sizeof(struct s_smt_fp_rxd)) ;
366 queue = smc->hw.fp.tx[QUEUE_A0] ;
367 DB_GEN("Init async TxD ring, %d TxDs ",HWM_ASYNC_TXD_COUNT,0,3) ;
368 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
369 HWM_ASYNC_TXD_COUNT) ;
370 phys = le32_to_cpu(ds->txd_ntdadr) ;
371 ds++ ;
372 queue->tx_curr_put = queue->tx_curr_get = ds ;
373 ds-- ;
374 queue->tx_free = HWM_ASYNC_TXD_COUNT ;
375 queue->tx_used = 0 ;
376 outpd(ADDR(B5_XA_DA),phys) ;
377
378 ds = (struct s_smt_fp_txd volatile *) ((char *)ds +
379 HWM_ASYNC_TXD_COUNT*sizeof(struct s_smt_fp_txd)) ;
380 queue = smc->hw.fp.tx[QUEUE_S] ;
381 DB_GEN("Init sync TxD ring, %d TxDs ",HWM_SYNC_TXD_COUNT,0,3) ;
382 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
383 HWM_SYNC_TXD_COUNT) ;
384 phys = le32_to_cpu(ds->txd_ntdadr) ;
385 ds++ ;
386 queue->tx_curr_put = queue->tx_curr_get = ds ;
387 queue->tx_free = HWM_SYNC_TXD_COUNT ;
388 queue->tx_used = 0 ;
389 outpd(ADDR(B5_XS_DA),phys) ;
390}
391
392static void init_rxd_ring(struct s_smc *smc)
393{
394 struct s_smt_fp_rxd volatile *ds ;
395 struct s_smt_rx_queue *queue ;
396 u_long phys ;
397
398 /*
399 * initialize the receive descriptors
400 */
401 ds = (struct s_smt_fp_rxd volatile *) smc->os.hwm.descr_p ;
402 queue = smc->hw.fp.rx[QUEUE_R1] ;
403 DB_GEN("Init RxD ring, %d RxDs ",SMT_R1_RXD_COUNT,0,3) ;
404 (void)init_descr_ring(smc,(union s_fp_descr volatile *)ds,
405 SMT_R1_RXD_COUNT) ;
406 phys = le32_to_cpu(ds->rxd_nrdadr) ;
407 ds++ ;
408 queue->rx_curr_put = queue->rx_curr_get = ds ;
409 queue->rx_free = SMT_R1_RXD_COUNT ;
410 queue->rx_used = 0 ;
411 outpd(ADDR(B4_R1_DA),phys) ;
412}
413
414/*
415 * BEGIN_MANUAL_ENTRY(init_fddi_driver)
416 * void init_fddi_driver(smc,mac_addr)
417 *
418 * initializes the driver and it's variables
419 *
420 * END_MANUAL_ENTRY
421 */
422void init_fddi_driver(struct s_smc *smc, u_char *mac_addr)
423{
424 SMbuf *mb ;
425 int i ;
426
427 init_board(smc,mac_addr) ;
428 (void)init_fplus(smc) ;
429
430 /*
431 * initialize the SMbufs for the SMT
432 */
433#ifndef COMMON_MB_POOL
434 mb = smc->os.hwm.mbuf_pool.mb_start ;
435 smc->os.hwm.mbuf_pool.mb_free = (SMbuf *)NULL ;
436 for (i = 0; i < MAX_MBUF; i++) {
437 mb->sm_use_count = 1 ;
438 smt_free_mbuf(smc,mb) ;
439 mb++ ;
440 }
441#else
442 mb = mb_start ;
443 if (!mb_init) {
444 mb_free = 0 ;
445 for (i = 0; i < MAX_MBUF; i++) {
446 mb->sm_use_count = 1 ;
447 smt_free_mbuf(smc,mb) ;
448 mb++ ;
449 }
450 mb_init = TRUE ;
451 }
452#endif
453
454 /*
455 * initialize the other variables
456 */
457 smc->os.hwm.llc_rx_pipe = smc->os.hwm.llc_rx_tail = (SMbuf *)NULL ;
458 smc->os.hwm.txd_tx_pipe = smc->os.hwm.txd_tx_tail = NULL ;
459 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = smc->os.hwm.pass_DB = 0 ;
460 smc->os.hwm.pass_llc_promisc = TRUE ;
461 smc->os.hwm.queued_rx_frames = smc->os.hwm.queued_txd_mb = 0 ;
462 smc->os.hwm.detec_count = 0 ;
463 smc->os.hwm.rx_break = 0 ;
464 smc->os.hwm.rx_len_error = 0 ;
465 smc->os.hwm.isr_flag = FALSE ;
466
467 /*
468 * make sure that the start pointer is 16 byte aligned
469 */
470 i = 16 - ((long)smc->os.hwm.descr_p & 0xf) ;
471 if (i != 16) {
472 DB_GEN("i = %d",i,0,3) ;
473 smc->os.hwm.descr_p = (union s_fp_descr volatile *)
474 ((char *)smc->os.hwm.descr_p+i) ;
475 }
476 DB_GEN("pt to descr area = %x",(void *)smc->os.hwm.descr_p,0,3) ;
477
478 init_txd_ring(smc) ;
479 init_rxd_ring(smc) ;
480 mac_drv_fill_rxd(smc) ;
481
482 init_plc(smc) ;
483}
484
485
486SMbuf *smt_get_mbuf(struct s_smc *smc)
487{
488 register SMbuf *mb ;
489
490#ifndef COMMON_MB_POOL
491 mb = smc->os.hwm.mbuf_pool.mb_free ;
492#else
493 mb = mb_free ;
494#endif
495 if (mb) {
496#ifndef COMMON_MB_POOL
497 smc->os.hwm.mbuf_pool.mb_free = mb->sm_next ;
498#else
499 mb_free = mb->sm_next ;
500#endif
501 mb->sm_off = 8 ;
502 mb->sm_use_count = 1 ;
503 }
504 DB_GEN("get SMbuf: mb = %x",(void *)mb,0,3) ;
505 return mb; /* May be NULL */
506}
507
508void smt_free_mbuf(struct s_smc *smc, SMbuf *mb)
509{
510
511 if (mb) {
512 mb->sm_use_count-- ;
513 DB_GEN("free_mbuf: sm_use_count = %d",mb->sm_use_count,0,3) ;
514 /*
515 * If the use_count is != zero the MBuf is queued
516 * more than once and must not queued into the
517 * free MBuf queue
518 */
519 if (!mb->sm_use_count) {
520 DB_GEN("free SMbuf: mb = %x",(void *)mb,0,3) ;
521#ifndef COMMON_MB_POOL
522 mb->sm_next = smc->os.hwm.mbuf_pool.mb_free ;
523 smc->os.hwm.mbuf_pool.mb_free = mb ;
524#else
525 mb->sm_next = mb_free ;
526 mb_free = mb ;
527#endif
528 }
529 }
530 else
531 SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ;
532}
533
534
535/*
536 * BEGIN_MANUAL_ENTRY(mac_drv_repair_descr)
537 * void mac_drv_repair_descr(smc)
538 *
539 * function called from SMT (HWM / hwmtm.c)
540 * The BMU is idle when this function is called.
541 * Mac_drv_repair_descr sets up the physical address
542 * for all receive and transmit queues where the BMU
543 * should continue.
544 * It may be that the BMU was reseted during a fragmented
545 * transfer. In this case there are some fragments which will
546 * never completed by the BMU. The OWN bit of this fragments
547 * must be switched to be owned by the host.
548 *
549 * Give a start command to the receive BMU.
550 * Start the transmit BMUs if transmit frames pending.
551 *
552 * END_MANUAL_ENTRY
553 */
554void mac_drv_repair_descr(struct s_smc *smc)
555{
556 u_long phys ;
557
558 if (smc->hw.hw_state != STOPPED) {
559 SK_BREAK() ;
560 SMT_PANIC(smc,HWM_E0013,HWM_E0013_MSG) ;
561 return ;
562 }
563
564 /*
565 * repair tx queues: don't start
566 */
567 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_A0]) ;
568 outpd(ADDR(B5_XA_DA),phys) ;
569 if (smc->hw.fp.tx_q[QUEUE_A0].tx_used) {
570 outpd(ADDR(B0_XA_CSR),CSR_START) ;
571 }
572 phys = repair_txd_ring(smc,smc->hw.fp.tx[QUEUE_S]) ;
573 outpd(ADDR(B5_XS_DA),phys) ;
574 if (smc->hw.fp.tx_q[QUEUE_S].tx_used) {
575 outpd(ADDR(B0_XS_CSR),CSR_START) ;
576 }
577
578 /*
579 * repair rx queues
580 */
581 phys = repair_rxd_ring(smc,smc->hw.fp.rx[QUEUE_R1]) ;
582 outpd(ADDR(B4_R1_DA),phys) ;
583 outpd(ADDR(B0_R1_CSR),CSR_START) ;
584}
585
586static u_long repair_txd_ring(struct s_smc *smc, struct s_smt_tx_queue *queue)
587{
588 int i ;
589 int tx_used ;
590 u_long phys ;
591 u_long tbctrl ;
592 struct s_smt_fp_txd volatile *t ;
593
594 SK_UNUSED(smc) ;
595
596 t = queue->tx_curr_get ;
597 tx_used = queue->tx_used ;
598 for (i = tx_used+queue->tx_free-1 ; i ; i-- ) {
599 t = t->txd_next ;
600 }
601 phys = le32_to_cpu(t->txd_ntdadr) ;
602
603 t = queue->tx_curr_get ;
604 while (tx_used) {
605 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
606 tbctrl = le32_to_cpu(t->txd_tbctrl) ;
607
608 if (tbctrl & BMU_OWN) {
609 if (tbctrl & BMU_STF) {
610 break ; /* exit the loop */
611 }
612 else {
613 /*
614 * repair the descriptor
615 */
616 t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
617 }
618 }
619 phys = le32_to_cpu(t->txd_ntdadr) ;
620 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
621 t = t->txd_next ;
622 tx_used-- ;
623 }
624 return phys;
625}
626
627/*
628 * Repairs the receive descriptor ring and returns the physical address
629 * where the BMU should continue working.
630 *
631 * o The physical address where the BMU was stopped has to be
632 * determined. This is the next RxD after rx_curr_get with an OWN
633 * bit set.
634 * o The BMU should start working at beginning of the next frame.
635 * RxDs with an OWN bit set but with a reset STF bit should be
636 * skipped and owned by the driver (OWN = 0).
637 */
638static u_long repair_rxd_ring(struct s_smc *smc, struct s_smt_rx_queue *queue)
639{
640 int i ;
641 int rx_used ;
642 u_long phys ;
643 u_long rbctrl ;
644 struct s_smt_fp_rxd volatile *r ;
645
646 SK_UNUSED(smc) ;
647
648 r = queue->rx_curr_get ;
649 rx_used = queue->rx_used ;
650 for (i = SMT_R1_RXD_COUNT-1 ; i ; i-- ) {
651 r = r->rxd_next ;
652 }
653 phys = le32_to_cpu(r->rxd_nrdadr) ;
654
655 r = queue->rx_curr_get ;
656 while (rx_used) {
657 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
658 rbctrl = le32_to_cpu(r->rxd_rbctrl) ;
659
660 if (rbctrl & BMU_OWN) {
661 if (rbctrl & BMU_STF) {
662 break ; /* exit the loop */
663 }
664 else {
665 /*
666 * repair the descriptor
667 */
668 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
669 }
670 }
671 phys = le32_to_cpu(r->rxd_nrdadr) ;
672 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
673 r = r->rxd_next ;
674 rx_used-- ;
675 }
676 return phys;
677}
678
679
680/*
681 -------------------------------------------------------------
682 INTERRUPT SERVICE ROUTINE:
683 -------------------------------------------------------------
684*/
685
686/*
687 * BEGIN_MANUAL_ENTRY(fddi_isr)
688 * void fddi_isr(smc)
689 *
690 * function DOWNCALL (drvsr.c)
691 * interrupt service routine, handles the interrupt requests
692 * generated by the FDDI adapter.
693 *
694 * NOTE: The operating system dependent module must guarantee that the
695 * interrupts of the adapter are disabled when it calls fddi_isr.
696 *
697 * About the USE_BREAK_ISR mechanismn:
698 *
699 * The main requirement of this mechanismn is to force an timer IRQ when
700 * leaving process_receive() with leave_isr set. process_receive() may
701 * be called at any time from anywhere!
702 * To be sure we don't miss such event we set 'force_irq' per default.
703 * We have to force and Timer IRQ if 'smc->os.hwm.leave_isr' AND
704 * 'force_irq' are set. 'force_irq' may be reset if a receive complete
705 * IRQ is pending.
706 *
707 * END_MANUAL_ENTRY
708 */
709void fddi_isr(struct s_smc *smc)
710{
711 u_long is ; /* ISR source */
712 u_short stu, stl ;
713 SMbuf *mb ;
714
715#ifdef USE_BREAK_ISR
716 int force_irq ;
717#endif
718
719#ifdef ODI2
720 if (smc->os.hwm.rx_break) {
721 mac_drv_fill_rxd(smc) ;
722 if (smc->hw.fp.rx_q[QUEUE_R1].rx_used > 0) {
723 smc->os.hwm.rx_break = 0 ;
724 process_receive(smc) ;
725 }
726 else {
727 smc->os.hwm.detec_count = 0 ;
728 smt_force_irq(smc) ;
729 }
730 }
731#endif
732 smc->os.hwm.isr_flag = TRUE ;
733
734#ifdef USE_BREAK_ISR
735 force_irq = TRUE ;
736 if (smc->os.hwm.leave_isr) {
737 smc->os.hwm.leave_isr = FALSE ;
738 process_receive(smc) ;
739 }
740#endif
741
742 while ((is = GET_ISR() & ISR_MASK)) {
743 NDD_TRACE("CH0B",is,0,0) ;
744 DB_GEN("ISA = 0x%x",is,0,7) ;
745
746 if (is & IMASK_SLOW) {
747 NDD_TRACE("CH1b",is,0,0) ;
748 if (is & IS_PLINT1) { /* PLC1 */
749 plc1_irq(smc) ;
750 }
751 if (is & IS_PLINT2) { /* PLC2 */
752 plc2_irq(smc) ;
753 }
754 if (is & IS_MINTR1) { /* FORMAC+ STU1(U/L) */
755 stu = inpw(FM_A(FM_ST1U)) ;
756 stl = inpw(FM_A(FM_ST1L)) ;
757 DB_GEN("Slow transmit complete",0,0,6) ;
758 mac1_irq(smc,stu,stl) ;
759 }
760 if (is & IS_MINTR2) { /* FORMAC+ STU2(U/L) */
761 stu= inpw(FM_A(FM_ST2U)) ;
762 stl= inpw(FM_A(FM_ST2L)) ;
763 DB_GEN("Slow receive complete",0,0,6) ;
764 DB_GEN("stl = %x : stu = %x",stl,stu,7) ;
765 mac2_irq(smc,stu,stl) ;
766 }
767 if (is & IS_MINTR3) { /* FORMAC+ STU3(U/L) */
768 stu= inpw(FM_A(FM_ST3U)) ;
769 stl= inpw(FM_A(FM_ST3L)) ;
770 DB_GEN("FORMAC Mode Register 3",0,0,6) ;
771 mac3_irq(smc,stu,stl) ;
772 }
773 if (is & IS_TIMINT) { /* Timer 82C54-2 */
774 timer_irq(smc) ;
775#ifdef NDIS_OS2
776 force_irq_pending = 0 ;
777#endif
778 /*
779 * out of RxD detection
780 */
781 if (++smc->os.hwm.detec_count > 4) {
782 /*
783 * check out of RxD condition
784 */
785 process_receive(smc) ;
786 }
787 }
788 if (is & IS_TOKEN) { /* Restricted Token Monitor */
789 rtm_irq(smc) ;
790 }
791 if (is & IS_R1_P) { /* Parity error rx queue 1 */
792 /* clear IRQ */
793 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_P) ;
794 SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ;
795 }
796 if (is & IS_R1_C) { /* Encoding error rx queue 1 */
797 /* clear IRQ */
798 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_C) ;
799 SMT_PANIC(smc,HWM_E0005,HWM_E0005_MSG) ;
800 }
801 if (is & IS_XA_C) { /* Encoding error async tx q */
802 /* clear IRQ */
803 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_C) ;
804 SMT_PANIC(smc,HWM_E0006,HWM_E0006_MSG) ;
805 }
806 if (is & IS_XS_C) { /* Encoding error sync tx q */
807 /* clear IRQ */
808 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_C) ;
809 SMT_PANIC(smc,HWM_E0007,HWM_E0007_MSG) ;
810 }
811 }
812
813 /*
814 * Fast Tx complete Async/Sync Queue (BMU service)
815 */
816 if (is & (IS_XS_F|IS_XA_F)) {
817 DB_GEN("Fast tx complete queue",0,0,6) ;
818 /*
819 * clear IRQ, Note: no IRQ is lost, because
820 * we always service both queues
821 */
822 outpd(ADDR(B5_XS_CSR),CSR_IRQ_CL_F) ;
823 outpd(ADDR(B5_XA_CSR),CSR_IRQ_CL_F) ;
824 mac_drv_clear_txd(smc) ;
825 llc_restart_tx(smc) ;
826 }
827
828 /*
829 * Fast Rx Complete (BMU service)
830 */
831 if (is & IS_R1_F) {
832 DB_GEN("Fast receive complete",0,0,6) ;
833 /* clear IRQ */
834#ifndef USE_BREAK_ISR
835 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
836 process_receive(smc) ;
837#else
838 process_receive(smc) ;
839 if (smc->os.hwm.leave_isr) {
840 force_irq = FALSE ;
841 } else {
842 outpd(ADDR(B4_R1_CSR),CSR_IRQ_CL_F) ;
843 process_receive(smc) ;
844 }
845#endif
846 }
847
848#ifndef NDIS_OS2
849 while ((mb = get_llc_rx(smc))) {
850 smt_to_llc(smc,mb) ;
851 }
852#else
853 if (offDepth)
854 post_proc() ;
855
856 while (!offDepth && (mb = get_llc_rx(smc))) {
857 smt_to_llc(smc,mb) ;
858 }
859
860 if (!offDepth && smc->os.hwm.rx_break) {
861 process_receive(smc) ;
862 }
863#endif
864 if (smc->q.ev_get != smc->q.ev_put) {
865 NDD_TRACE("CH2a",0,0,0) ;
866 ev_dispatcher(smc) ;
867 }
868#ifdef NDIS_OS2
869 post_proc() ;
870 if (offDepth) { /* leave fddi_isr because */
871 break ; /* indications not allowed */
872 }
873#endif
874#ifdef USE_BREAK_ISR
875 if (smc->os.hwm.leave_isr) {
876 break ; /* leave fddi_isr */
877 }
878#endif
879
880 /* NOTE: when the isr is left, no rx is pending */
881 } /* end of interrupt source polling loop */
882
883#ifdef USE_BREAK_ISR
884 if (smc->os.hwm.leave_isr && force_irq) {
885 smt_force_irq(smc) ;
886 }
887#endif
888 smc->os.hwm.isr_flag = FALSE ;
889 NDD_TRACE("CH0E",0,0,0) ;
890}
891
892
893/*
894 -------------------------------------------------------------
895 RECEIVE FUNCTIONS:
896 -------------------------------------------------------------
897*/
898
899#ifndef NDIS_OS2
900/*
901 * BEGIN_MANUAL_ENTRY(mac_drv_rx_mode)
902 * void mac_drv_rx_mode(smc,mode)
903 *
904 * function DOWNCALL (fplus.c)
905 * Corresponding to the parameter mode, the operating system
906 * dependent module can activate several receive modes.
907 *
908 * para mode = 1: RX_ENABLE_ALLMULTI enable all multicasts
909 * = 2: RX_DISABLE_ALLMULTI disable "enable all multicasts"
910 * = 3: RX_ENABLE_PROMISC enable promiscuous
911 * = 4: RX_DISABLE_PROMISC disable promiscuous
912 * = 5: RX_ENABLE_NSA enable rec. of all NSA frames
913 * (disabled after 'driver reset' & 'set station address')
914 * = 6: RX_DISABLE_NSA disable rec. of all NSA frames
915 *
916 * = 21: RX_ENABLE_PASS_SMT ( see description )
917 * = 22: RX_DISABLE_PASS_SMT ( " " )
918 * = 23: RX_ENABLE_PASS_NSA ( " " )
919 * = 24: RX_DISABLE_PASS_NSA ( " " )
920 * = 25: RX_ENABLE_PASS_DB ( " " )
921 * = 26: RX_DISABLE_PASS_DB ( " " )
922 * = 27: RX_DISABLE_PASS_ALL ( " " )
923 * = 28: RX_DISABLE_LLC_PROMISC ( " " )
924 * = 29: RX_ENABLE_LLC_PROMISC ( " " )
925 *
926 *
927 * RX_ENABLE_PASS_SMT / RX_DISABLE_PASS_SMT
928 *
929 * If the operating system dependent module activates the
930 * mode RX_ENABLE_PASS_SMT, the hardware module
931 * duplicates all SMT frames with the frame control
932 * FC_SMT_INFO and passes them to the LLC receive channel
933 * by calling mac_drv_rx_init.
934 * The SMT Frames which are sent by the local SMT and the NSA
935 * frames whose A- and C-Indicator is not set are also duplicated
936 * and passed.
937 * The receive mode RX_DISABLE_PASS_SMT disables the passing
938 * of SMT frames.
939 *
940 * RX_ENABLE_PASS_NSA / RX_DISABLE_PASS_NSA
941 *
942 * If the operating system dependent module activates the
943 * mode RX_ENABLE_PASS_NSA, the hardware module
944 * duplicates all NSA frames with frame control FC_SMT_NSA
945 * and a set A-Indicator and passed them to the LLC
946 * receive channel by calling mac_drv_rx_init.
947 * All NSA Frames which are sent by the local SMT
948 * are also duplicated and passed.
949 * The receive mode RX_DISABLE_PASS_NSA disables the passing
950 * of NSA frames with the A- or C-Indicator set.
951 *
952 * NOTE: For fear that the hardware module receives NSA frames with
953 * a reset A-Indicator, the operating system dependent module
954 * has to call mac_drv_rx_mode with the mode RX_ENABLE_NSA
955 * before activate the RX_ENABLE_PASS_NSA mode and after every
956 * 'driver reset' and 'set station address'.
957 *
958 * RX_ENABLE_PASS_DB / RX_DISABLE_PASS_DB
959 *
960 * If the operating system dependent module activates the
961 * mode RX_ENABLE_PASS_DB, direct BEACON frames
962 * (FC_BEACON frame control) are passed to the LLC receive
963 * channel by mac_drv_rx_init.
964 * The receive mode RX_DISABLE_PASS_DB disables the passing
965 * of direct BEACON frames.
966 *
967 * RX_DISABLE_PASS_ALL
968 *
969 * Disables all special receives modes. It is equal to
970 * call mac_drv_set_rx_mode successively with the
971 * parameters RX_DISABLE_NSA, RX_DISABLE_PASS_SMT,
972 * RX_DISABLE_PASS_NSA and RX_DISABLE_PASS_DB.
973 *
974 * RX_ENABLE_LLC_PROMISC
975 *
976 * (default) all received LLC frames and all SMT/NSA/DBEACON
977 * frames depending on the attitude of the flags
978 * PASS_SMT/PASS_NSA/PASS_DBEACON will be delivered to the
979 * LLC layer
980 *
981 * RX_DISABLE_LLC_PROMISC
982 *
983 * all received SMT/NSA/DBEACON frames depending on the
984 * attitude of the flags PASS_SMT/PASS_NSA/PASS_DBEACON
985 * will be delivered to the LLC layer.
986 * all received LLC frames with a directed address, Multicast
987 * or Broadcast address will be delivered to the LLC
988 * layer too.
989 *
990 * END_MANUAL_ENTRY
991 */
992void mac_drv_rx_mode(struct s_smc *smc, int mode)
993{
994 switch(mode) {
995 case RX_ENABLE_PASS_SMT:
996 smc->os.hwm.pass_SMT = TRUE ;
997 break ;
998 case RX_DISABLE_PASS_SMT:
999 smc->os.hwm.pass_SMT = FALSE ;
1000 break ;
1001 case RX_ENABLE_PASS_NSA:
1002 smc->os.hwm.pass_NSA = TRUE ;
1003 break ;
1004 case RX_DISABLE_PASS_NSA:
1005 smc->os.hwm.pass_NSA = FALSE ;
1006 break ;
1007 case RX_ENABLE_PASS_DB:
1008 smc->os.hwm.pass_DB = TRUE ;
1009 break ;
1010 case RX_DISABLE_PASS_DB:
1011 smc->os.hwm.pass_DB = FALSE ;
1012 break ;
1013 case RX_DISABLE_PASS_ALL:
1014 smc->os.hwm.pass_SMT = smc->os.hwm.pass_NSA = FALSE ;
1015 smc->os.hwm.pass_DB = FALSE ;
1016 smc->os.hwm.pass_llc_promisc = TRUE ;
1017 mac_set_rx_mode(smc,RX_DISABLE_NSA) ;
1018 break ;
1019 case RX_DISABLE_LLC_PROMISC:
1020 smc->os.hwm.pass_llc_promisc = FALSE ;
1021 break ;
1022 case RX_ENABLE_LLC_PROMISC:
1023 smc->os.hwm.pass_llc_promisc = TRUE ;
1024 break ;
1025 case RX_ENABLE_ALLMULTI:
1026 case RX_DISABLE_ALLMULTI:
1027 case RX_ENABLE_PROMISC:
1028 case RX_DISABLE_PROMISC:
1029 case RX_ENABLE_NSA:
1030 case RX_DISABLE_NSA:
1031 default:
1032 mac_set_rx_mode(smc,mode) ;
1033 break ;
1034 }
1035}
1036#endif /* ifndef NDIS_OS2 */
1037
1038/*
1039 * process receive queue
1040 */
1041void process_receive(struct s_smc *smc)
1042{
1043 int i ;
1044 int n ;
1045 int frag_count ; /* number of RxDs of the curr rx buf */
1046 int used_frags ; /* number of RxDs of the curr frame */
1047 struct s_smt_rx_queue *queue ; /* points to the queue ctl struct */
1048 struct s_smt_fp_rxd volatile *r ; /* rxd pointer */
1049 struct s_smt_fp_rxd volatile *rxd ; /* first rxd of rx frame */
1050 u_long rbctrl ; /* receive buffer control word */
1051 u_long rfsw ; /* receive frame status word */
1052 u_short rx_used ;
1053 u_char far *virt ;
1054 char far *data ;
1055 SMbuf *mb ;
1056 u_char fc ; /* Frame control */
1057 int len ; /* Frame length */
1058
1059 smc->os.hwm.detec_count = 0 ;
1060 queue = smc->hw.fp.rx[QUEUE_R1] ;
1061 NDD_TRACE("RHxB",0,0,0) ;
1062 for ( ; ; ) {
1063 r = queue->rx_curr_get ;
1064 rx_used = queue->rx_used ;
1065 frag_count = 0 ;
1066
1067#ifdef USE_BREAK_ISR
1068 if (smc->os.hwm.leave_isr) {
1069 goto rx_end ;
1070 }
1071#endif
1072#ifdef NDIS_OS2
1073 if (offDepth) {
1074 smc->os.hwm.rx_break = 1 ;
1075 goto rx_end ;
1076 }
1077 smc->os.hwm.rx_break = 0 ;
1078#endif
1079#ifdef ODI2
1080 if (smc->os.hwm.rx_break) {
1081 goto rx_end ;
1082 }
1083#endif
1084 n = 0 ;
1085 do {
1086 DB_RX("Check RxD %x for OWN and EOF",(void *)r,0,5) ;
1087 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1088 rbctrl = le32_to_cpu(CR_READ(r->rxd_rbctrl));
1089
1090 if (rbctrl & BMU_OWN) {
1091 NDD_TRACE("RHxE",r,rfsw,rbctrl) ;
1092 DB_RX("End of RxDs",0,0,4) ;
1093 goto rx_end ;
1094 }
1095 /*
1096 * out of RxD detection
1097 */
1098 if (!rx_used) {
1099 SK_BREAK() ;
1100 SMT_PANIC(smc,HWM_E0009,HWM_E0009_MSG) ;
1101 /* Either we don't have an RxD or all
1102 * RxDs are filled. Therefore it's allowed
1103 * for to set the STOPPED flag */
1104 smc->hw.hw_state = STOPPED ;
1105 mac_drv_clear_rx_queue(smc) ;
1106 smc->hw.hw_state = STARTED ;
1107 mac_drv_fill_rxd(smc) ;
1108 smc->os.hwm.detec_count = 0 ;
1109 goto rx_end ;
1110 }
1111 rfsw = le32_to_cpu(r->rxd_rfsw) ;
1112 if ((rbctrl & BMU_STF) != ((rbctrl & BMU_ST_BUF) <<5)) {
1113 /*
1114 * The BMU_STF bit is deleted, 1 frame is
1115 * placed into more than 1 rx buffer
1116 *
1117 * skip frame by setting the rx len to 0
1118 *
1119 * if fragment count == 0
1120 * The missing STF bit belongs to the
1121 * current frame, search for the
1122 * EOF bit to complete the frame
1123 * else
1124 * the fragment belongs to the next frame,
1125 * exit the loop and process the frame
1126 */
1127 SK_BREAK() ;
1128 rfsw = 0 ;
1129 if (frag_count) {
1130 break ;
1131 }
1132 }
1133 n += rbctrl & 0xffff ;
1134 r = r->rxd_next ;
1135 frag_count++ ;
1136 rx_used-- ;
1137 } while (!(rbctrl & BMU_EOF)) ;
1138 used_frags = frag_count ;
1139 DB_RX("EOF set in RxD, used_frags = %d ",used_frags,0,5) ;
1140
1141 /* may be next 2 DRV_BUF_FLUSH() can be skipped, because */
1142 /* BMU_ST_BUF will not be changed by the ASIC */
1143 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1144 while (rx_used && !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
1145 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1146 r = r->rxd_next ;
1147 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1148 frag_count++ ;
1149 rx_used-- ;
1150 }
1151 DB_RX("STF bit found",0,0,5) ;
1152
1153 /*
1154 * The received frame is finished for the process receive
1155 */
1156 rxd = queue->rx_curr_get ;
1157 queue->rx_curr_get = r ;
1158 queue->rx_free += frag_count ;
1159 queue->rx_used = rx_used ;
1160
1161 /*
1162 * ASIC Errata no. 7 (STF - Bit Bug)
1163 */
1164 rxd->rxd_rbctrl &= cpu_to_le32(~BMU_STF) ;
1165
1166 for (r=rxd, i=frag_count ; i ; r=r->rxd_next, i--){
1167 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1168 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1169 }
1170 smc->hw.fp.err_stats.err_valid++ ;
1171 smc->mib.m[MAC0].fddiMACCopied_Ct++ ;
1172
1173 /* the length of the data including the FC */
1174 len = (rfsw & RD_LENGTH) - 4 ;
1175
1176 DB_RX("frame length = %d",len,0,4) ;
1177 /*
1178 * check the frame_length and all error flags
1179 */
1180 if (rfsw & (RX_MSRABT|RX_FS_E|RX_FS_CRC|RX_FS_IMPL)){
1181 if (rfsw & RD_S_MSRABT) {
1182 DB_RX("Frame aborted by the FORMAC",0,0,2) ;
1183 smc->hw.fp.err_stats.err_abort++ ;
1184 }
1185 /*
1186 * check frame status
1187 */
1188 if (rfsw & RD_S_SEAC2) {
1189 DB_RX("E-Indicator set",0,0,2) ;
1190 smc->hw.fp.err_stats.err_e_indicator++ ;
1191 }
1192 if (rfsw & RD_S_SFRMERR) {
1193 DB_RX("CRC error",0,0,2) ;
1194 smc->hw.fp.err_stats.err_crc++ ;
1195 }
1196 if (rfsw & RX_FS_IMPL) {
1197 DB_RX("Implementer frame",0,0,2) ;
1198 smc->hw.fp.err_stats.err_imp_frame++ ;
1199 }
1200 goto abort_frame ;
1201 }
1202 if (len > FDDI_RAW_MTU-4) {
1203 DB_RX("Frame too long error",0,0,2) ;
1204 smc->hw.fp.err_stats.err_too_long++ ;
1205 goto abort_frame ;
1206 }
1207 /*
1208 * SUPERNET 3 Bug: FORMAC delivers status words
1209 * of aborded frames to the BMU
1210 */
1211 if (len <= 4) {
1212 DB_RX("Frame length = 0",0,0,2) ;
1213 goto abort_frame ;
1214 }
1215
1216 if (len != (n-4)) {
1217 DB_RX("BMU: rx len differs: [%d:%d]",len,n,4);
1218 smc->os.hwm.rx_len_error++ ;
1219 goto abort_frame ;
1220 }
1221
1222 /*
1223 * Check SA == MA
1224 */
1225 virt = (u_char far *) rxd->rxd_virt ;
1226 DB_RX("FC = %x",*virt,0,2) ;
1227 if (virt[12] == MA[5] &&
1228 virt[11] == MA[4] &&
1229 virt[10] == MA[3] &&
1230 virt[9] == MA[2] &&
1231 virt[8] == MA[1] &&
1232 (virt[7] & ~GROUP_ADDR_BIT) == MA[0]) {
1233 goto abort_frame ;
1234 }
1235
1236 /*
1237 * test if LLC frame
1238 */
1239 if (rfsw & RX_FS_LLC) {
1240 /*
1241 * if pass_llc_promisc is disable
1242 * if DA != Multicast or Broadcast or DA!=MA
1243 * abort the frame
1244 */
1245 if (!smc->os.hwm.pass_llc_promisc) {
1246 if(!(virt[1] & GROUP_ADDR_BIT)) {
1247 if (virt[6] != MA[5] ||
1248 virt[5] != MA[4] ||
1249 virt[4] != MA[3] ||
1250 virt[3] != MA[2] ||
1251 virt[2] != MA[1] ||
1252 virt[1] != MA[0]) {
1253 DB_RX("DA != MA and not multi- or broadcast",0,0,2) ;
1254 goto abort_frame ;
1255 }
1256 }
1257 }
1258
1259 /*
1260 * LLC frame received
1261 */
1262 DB_RX("LLC - receive",0,0,4) ;
1263 mac_drv_rx_complete(smc,rxd,frag_count,len) ;
1264 }
1265 else {
1266 if (!(mb = smt_get_mbuf(smc))) {
1267 smc->hw.fp.err_stats.err_no_buf++ ;
1268 DB_RX("No SMbuf; receive terminated",0,0,4) ;
1269 goto abort_frame ;
1270 }
1271 data = smtod(mb,char *) - 1 ;
1272
1273 /*
1274 * copy the frame into a SMT_MBuf
1275 */
1276#ifdef USE_OS_CPY
1277 hwm_cpy_rxd2mb(rxd,data,len) ;
1278#else
1279 for (r=rxd, i=used_frags ; i ; r=r->rxd_next, i--){
1280 n = le32_to_cpu(r->rxd_rbctrl) & RD_LENGTH ;
1281 DB_RX("cp SMT frame to mb: len = %d",n,0,6) ;
1282 memcpy(data,r->rxd_virt,n) ;
1283 data += n ;
1284 }
1285 data = smtod(mb,char *) - 1 ;
1286#endif
1287 fc = *(char *)mb->sm_data = *data ;
1288 mb->sm_len = len - 1 ; /* len - fc */
1289 data++ ;
1290
1291 /*
1292 * SMT frame received
1293 */
1294 switch(fc) {
1295 case FC_SMT_INFO :
1296 smc->hw.fp.err_stats.err_smt_frame++ ;
1297 DB_RX("SMT frame received ",0,0,5) ;
1298
1299 if (smc->os.hwm.pass_SMT) {
1300 DB_RX("pass SMT frame ",0,0,5) ;
1301 mac_drv_rx_complete(smc, rxd,
1302 frag_count,len) ;
1303 }
1304 else {
1305 DB_RX("requeue RxD",0,0,5) ;
1306 mac_drv_requeue_rxd(smc,rxd,frag_count);
1307 }
1308
1309 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1310 break ;
1311 case FC_SMT_NSA :
1312 smc->hw.fp.err_stats.err_smt_frame++ ;
1313 DB_RX("SMT frame received ",0,0,5) ;
1314
1315 /* if pass_NSA set pass the NSA frame or */
1316 /* pass_SMT set and the A-Indicator */
1317 /* is not set, pass the NSA frame */
1318 if (smc->os.hwm.pass_NSA ||
1319 (smc->os.hwm.pass_SMT &&
1320 !(rfsw & A_INDIC))) {
1321 DB_RX("pass SMT frame ",0,0,5) ;
1322 mac_drv_rx_complete(smc, rxd,
1323 frag_count,len) ;
1324 }
1325 else {
1326 DB_RX("requeue RxD",0,0,5) ;
1327 mac_drv_requeue_rxd(smc,rxd,frag_count);
1328 }
1329
1330 smt_received_pack(smc,mb,(int)(rfsw>>25)) ;
1331 break ;
1332 case FC_BEACON :
1333 if (smc->os.hwm.pass_DB) {
1334 DB_RX("pass DB frame ",0,0,5) ;
1335 mac_drv_rx_complete(smc, rxd,
1336 frag_count,len) ;
1337 }
1338 else {
1339 DB_RX("requeue RxD",0,0,5) ;
1340 mac_drv_requeue_rxd(smc,rxd,frag_count);
1341 }
1342 smt_free_mbuf(smc,mb) ;
1343 break ;
1344 default :
1345 /*
1346 * unknown FC abord the frame
1347 */
1348 DB_RX("unknown FC error",0,0,2) ;
1349 smt_free_mbuf(smc,mb) ;
1350 DB_RX("requeue RxD",0,0,5) ;
1351 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1352 if ((fc & 0xf0) == FC_MAC)
1353 smc->hw.fp.err_stats.err_mac_frame++ ;
1354 else
1355 smc->hw.fp.err_stats.err_imp_frame++ ;
1356
1357 break ;
1358 }
1359 }
1360
1361 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1362 NDD_TRACE("RHx1",queue->rx_curr_get,0,0) ;
1363
1364 continue ;
1365 /*--------------------------------------------------------------------*/
1366abort_frame:
1367 DB_RX("requeue RxD",0,0,5) ;
1368 mac_drv_requeue_rxd(smc,rxd,frag_count) ;
1369
1370 DB_RX("next RxD is %x ",queue->rx_curr_get,0,3) ;
1371 NDD_TRACE("RHx2",queue->rx_curr_get,0,0) ;
1372 }
1373rx_end:
1374#ifdef ALL_RX_COMPLETE
1375 mac_drv_all_receives_complete(smc) ;
1376#endif
1377 return ; /* lint bug: needs return detect end of function */
1378}
1379
1380static void smt_to_llc(struct s_smc *smc, SMbuf *mb)
1381{
1382 u_char fc ;
1383
1384 DB_RX("send a queued frame to the llc layer",0,0,4) ;
1385 smc->os.hwm.r.len = mb->sm_len ;
1386 smc->os.hwm.r.mb_pos = smtod(mb,char *) ;
1387 fc = *smc->os.hwm.r.mb_pos ;
1388 (void)mac_drv_rx_init(smc,(int)mb->sm_len,(int)fc,
1389 smc->os.hwm.r.mb_pos,(int)mb->sm_len) ;
1390 smt_free_mbuf(smc,mb) ;
1391}
1392
1393/*
1394 * BEGIN_MANUAL_ENTRY(hwm_rx_frag)
1395 * void hwm_rx_frag(smc,virt,phys,len,frame_status)
1396 *
1397 * function MACRO (hardware module, hwmtm.h)
1398 * This function calls dma_master for preparing the
1399 * system hardware for the DMA transfer and initializes
1400 * the current RxD with the length and the physical and
1401 * virtual address of the fragment. Furthermore, it sets the
1402 * STF and EOF bits depending on the frame status byte,
1403 * switches the OWN flag of the RxD, so that it is owned by the
1404 * adapter and issues an rx_start.
1405 *
1406 * para virt virtual pointer to the fragment
1407 * len the length of the fragment
1408 * frame_status status of the frame, see design description
1409 *
1410 * NOTE: It is possible to call this function with a fragment length
1411 * of zero.
1412 *
1413 * END_MANUAL_ENTRY
1414 */
1415void hwm_rx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1416 int frame_status)
1417{
1418 struct s_smt_fp_rxd volatile *r ;
1419 __le32 rbctrl;
1420
1421 NDD_TRACE("RHfB",virt,len,frame_status) ;
1422 DB_RX("hwm_rx_frag: len = %d, frame_status = %x\n",len,frame_status,2) ;
1423 r = smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put ;
1424 r->rxd_virt = virt ;
1425 r->rxd_rbadr = cpu_to_le32(phys) ;
1426 rbctrl = cpu_to_le32( (((__u32)frame_status &
1427 (FIRST_FRAG|LAST_FRAG))<<26) |
1428 (((u_long) frame_status & FIRST_FRAG) << 21) |
1429 BMU_OWN | BMU_CHECK | BMU_EN_IRQ_EOF | len) ;
1430 r->rxd_rbctrl = rbctrl ;
1431
1432 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1433 outpd(ADDR(B0_R1_CSR),CSR_START) ;
1434 smc->hw.fp.rx_q[QUEUE_R1].rx_free-- ;
1435 smc->hw.fp.rx_q[QUEUE_R1].rx_used++ ;
1436 smc->hw.fp.rx_q[QUEUE_R1].rx_curr_put = r->rxd_next ;
1437 NDD_TRACE("RHfE",r,le32_to_cpu(r->rxd_rbadr),0) ;
1438}
1439
1440/*
1441 * BEGINN_MANUAL_ENTRY(mac_drv_clear_rx_queue)
1442 *
1443 * void mac_drv_clear_rx_queue(smc)
1444 * struct s_smc *smc ;
1445 *
1446 * function DOWNCALL (hardware module, hwmtm.c)
1447 * mac_drv_clear_rx_queue is called by the OS-specific module
1448 * after it has issued a card_stop.
1449 * In this case, the frames in the receive queue are obsolete and
1450 * should be removed. For removing mac_drv_clear_rx_queue
1451 * calls dma_master for each RxD and mac_drv_clear_rxd for each
1452 * receive buffer.
1453 *
1454 * NOTE: calling sequence card_stop:
1455 * CLI_FBI(), card_stop(),
1456 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
1457 *
1458 * NOTE: The caller is responsible that the BMUs are idle
1459 * when this function is called.
1460 *
1461 * END_MANUAL_ENTRY
1462 */
1463void mac_drv_clear_rx_queue(struct s_smc *smc)
1464{
1465 struct s_smt_fp_rxd volatile *r ;
1466 struct s_smt_fp_rxd volatile *next_rxd ;
1467 struct s_smt_rx_queue *queue ;
1468 int frag_count ;
1469 int i ;
1470
1471 if (smc->hw.hw_state != STOPPED) {
1472 SK_BREAK() ;
1473 SMT_PANIC(smc,HWM_E0012,HWM_E0012_MSG) ;
1474 return ;
1475 }
1476
1477 queue = smc->hw.fp.rx[QUEUE_R1] ;
1478 DB_RX("clear_rx_queue",0,0,5) ;
1479
1480 /*
1481 * dma_complete and mac_drv_clear_rxd for all RxDs / receive buffers
1482 */
1483 r = queue->rx_curr_get ;
1484 while (queue->rx_used) {
1485 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1486 DB_RX("switch OWN bit of RxD 0x%x ",r,0,5) ;
1487 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
1488 frag_count = 1 ;
1489 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1490 r = r->rxd_next ;
1491 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1492 while (r != queue->rx_curr_put &&
1493 !(r->rxd_rbctrl & cpu_to_le32(BMU_ST_BUF))) {
1494 DB_RX("Check STF bit in %x",(void *)r,0,5) ;
1495 r->rxd_rbctrl &= ~cpu_to_le32(BMU_OWN) ;
1496 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORDEV) ;
1497 r = r->rxd_next ;
1498 DRV_BUF_FLUSH(r,DDI_DMA_SYNC_FORCPU) ;
1499 frag_count++ ;
1500 }
1501 DB_RX("STF bit found",0,0,5) ;
1502 next_rxd = r ;
1503
1504 for (r=queue->rx_curr_get,i=frag_count; i ; r=r->rxd_next,i--){
1505 DB_RX("dma_complete for RxD %x",(void *)r,0,5) ;
1506 dma_complete(smc,(union s_fp_descr volatile *)r,DMA_WR);
1507 }
1508
1509 DB_RX("mac_drv_clear_rxd: RxD %x frag_count %d ",
1510 (void *)queue->rx_curr_get,frag_count,5) ;
1511 mac_drv_clear_rxd(smc,queue->rx_curr_get,frag_count) ;
1512
1513 queue->rx_curr_get = next_rxd ;
1514 queue->rx_used -= frag_count ;
1515 queue->rx_free += frag_count ;
1516 }
1517}
1518
1519
1520/*
1521 -------------------------------------------------------------
1522 SEND FUNCTIONS:
1523 -------------------------------------------------------------
1524*/
1525
1526/*
1527 * BEGIN_MANUAL_ENTRY(hwm_tx_init)
1528 * int hwm_tx_init(smc,fc,frag_count,frame_len,frame_status)
1529 *
1530 * function DOWN_CALL (hardware module, hwmtm.c)
1531 * hwm_tx_init checks if the frame can be sent through the
1532 * corresponding send queue.
1533 *
1534 * para fc the frame control. To determine through which
1535 * send queue the frame should be transmitted.
1536 * 0x50 - 0x57: asynchronous LLC frame
1537 * 0xD0 - 0xD7: synchronous LLC frame
1538 * 0x41, 0x4F: SMT frame to the network
1539 * 0x42: SMT frame to the network and to the local SMT
1540 * 0x43: SMT frame to the local SMT
1541 * frag_count count of the fragments for this frame
1542 * frame_len length of the frame
1543 * frame_status status of the frame, the send queue bit is already
1544 * specified
1545 *
1546 * return frame_status
1547 *
1548 * END_MANUAL_ENTRY
1549 */
1550int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count, int frame_len,
1551 int frame_status)
1552{
1553 NDD_TRACE("THiB",fc,frag_count,frame_len) ;
1554 smc->os.hwm.tx_p = smc->hw.fp.tx[frame_status & QUEUE_A0] ;
1555 smc->os.hwm.tx_descr = TX_DESCRIPTOR | (((u_long)(frame_len-1)&3)<<27) ;
1556 smc->os.hwm.tx_len = frame_len ;
1557 DB_TX("hwm_tx_init: fc = %x, len = %d",fc,frame_len,3) ;
1558 if ((fc & ~(FC_SYNC_BIT|FC_LLC_PRIOR)) == FC_ASYNC_LLC) {
1559 frame_status |= LAN_TX ;
1560 }
1561 else {
1562 switch (fc) {
1563 case FC_SMT_INFO :
1564 case FC_SMT_NSA :
1565 frame_status |= LAN_TX ;
1566 break ;
1567 case FC_SMT_LOC :
1568 frame_status |= LOC_TX ;
1569 break ;
1570 case FC_SMT_LAN_LOC :
1571 frame_status |= LAN_TX | LOC_TX ;
1572 break ;
1573 default :
1574 SMT_PANIC(smc,HWM_E0010,HWM_E0010_MSG) ;
1575 }
1576 }
1577 if (!smc->hw.mac_ring_is_up) {
1578 frame_status &= ~LAN_TX ;
1579 frame_status |= RING_DOWN ;
1580 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1581 }
1582 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1583#ifndef NDIS_OS2
1584 mac_drv_clear_txd(smc) ;
1585 if (frag_count > smc->os.hwm.tx_p->tx_free) {
1586 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1587 frame_status &= ~LAN_TX ;
1588 frame_status |= OUT_OF_TXD ;
1589 }
1590#else
1591 DB_TX("Out of TxDs, terminate LAN_TX",0,0,2) ;
1592 frame_status &= ~LAN_TX ;
1593 frame_status |= OUT_OF_TXD ;
1594#endif
1595 }
1596 DB_TX("frame_status = %x",frame_status,0,3) ;
1597 NDD_TRACE("THiE",frame_status,smc->os.hwm.tx_p->tx_free,0) ;
1598 return frame_status;
1599}
1600
1601/*
1602 * BEGIN_MANUAL_ENTRY(hwm_tx_frag)
1603 * void hwm_tx_frag(smc,virt,phys,len,frame_status)
1604 *
1605 * function DOWNCALL (hardware module, hwmtm.c)
1606 * If the frame should be sent to the LAN, this function calls
1607 * dma_master, fills the current TxD with the virtual and the
1608 * physical address, sets the STF and EOF bits dependent on
1609 * the frame status, and requests the BMU to start the
1610 * transmit.
1611 * If the frame should be sent to the local SMT, an SMT_MBuf
1612 * is allocated if the FIRST_FRAG bit is set in the frame_status.
1613 * The fragment of the frame is copied into the SMT MBuf.
1614 * The function smt_received_pack is called if the LAST_FRAG
1615 * bit is set in the frame_status word.
1616 *
1617 * para virt virtual pointer to the fragment
1618 * len the length of the fragment
1619 * frame_status status of the frame, see design description
1620 *
1621 * return nothing returned, no parameter is modified
1622 *
1623 * NOTE: It is possible to invoke this macro with a fragment length
1624 * of zero.
1625 *
1626 * END_MANUAL_ENTRY
1627 */
1628void hwm_tx_frag(struct s_smc *smc, char far *virt, u_long phys, int len,
1629 int frame_status)
1630{
1631 struct s_smt_fp_txd volatile *t ;
1632 struct s_smt_tx_queue *queue ;
1633 __le32 tbctrl ;
1634
1635 queue = smc->os.hwm.tx_p ;
1636
1637 NDD_TRACE("THfB",virt,len,frame_status) ;
1638 /* Bug fix: AF / May 31 1999 (#missing)
1639 * snmpinfo problem reported by IBM is caused by invalid
1640 * t-pointer (txd) if LAN_TX is not set but LOC_TX only.
1641 * Set: t = queue->tx_curr_put here !
1642 */
1643 t = queue->tx_curr_put ;
1644
1645 DB_TX("hwm_tx_frag: len = %d, frame_status = %x ",len,frame_status,2) ;
1646 if (frame_status & LAN_TX) {
1647 /* '*t' is already defined */
1648 DB_TX("LAN_TX: TxD = %x, virt = %x ",t,virt,3) ;
1649 t->txd_virt = virt ;
1650 t->txd_txdscr = cpu_to_le32(smc->os.hwm.tx_descr) ;
1651 t->txd_tbadr = cpu_to_le32(phys) ;
1652 tbctrl = cpu_to_le32((((__u32)frame_status &
1653 (FIRST_FRAG|LAST_FRAG|EN_IRQ_EOF))<< 26) |
1654 BMU_OWN|BMU_CHECK |len) ;
1655 t->txd_tbctrl = tbctrl ;
1656
1657#ifndef AIX
1658 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1659 outpd(queue->tx_bmu_ctl,CSR_START) ;
1660#else /* ifndef AIX */
1661 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1662 if (frame_status & QUEUE_A0) {
1663 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1664 }
1665 else {
1666 outpd(ADDR(B0_XS_CSR),CSR_START) ;
1667 }
1668#endif
1669 queue->tx_free-- ;
1670 queue->tx_used++ ;
1671 queue->tx_curr_put = t->txd_next ;
1672 if (frame_status & LAST_FRAG) {
1673 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1674 }
1675 }
1676 if (frame_status & LOC_TX) {
1677 DB_TX("LOC_TX: ",0,0,3) ;
1678 if (frame_status & FIRST_FRAG) {
1679 if(!(smc->os.hwm.tx_mb = smt_get_mbuf(smc))) {
1680 smc->hw.fp.err_stats.err_no_buf++ ;
1681 DB_TX("No SMbuf; transmit terminated",0,0,4) ;
1682 }
1683 else {
1684 smc->os.hwm.tx_data =
1685 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1686#ifdef USE_OS_CPY
1687#ifdef PASS_1ST_TXD_2_TX_COMP
1688 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1689 smc->os.hwm.tx_len) ;
1690#endif
1691#endif
1692 }
1693 }
1694 if (smc->os.hwm.tx_mb) {
1695#ifndef USE_OS_CPY
1696 DB_TX("copy fragment into MBuf ",0,0,3) ;
1697 memcpy(smc->os.hwm.tx_data,virt,len) ;
1698 smc->os.hwm.tx_data += len ;
1699#endif
1700 if (frame_status & LAST_FRAG) {
1701#ifdef USE_OS_CPY
1702#ifndef PASS_1ST_TXD_2_TX_COMP
1703 /*
1704 * hwm_cpy_txd2mb(txd,data,len) copies 'len'
1705 * bytes from the virtual pointer in 'rxd'
1706 * to 'data'. The virtual pointer of the
1707 * os-specific tx-buffer should be written
1708 * in the LAST txd.
1709 */
1710 hwm_cpy_txd2mb(t,smc->os.hwm.tx_data,
1711 smc->os.hwm.tx_len) ;
1712#endif /* nPASS_1ST_TXD_2_TX_COMP */
1713#endif /* USE_OS_CPY */
1714 smc->os.hwm.tx_data =
1715 smtod(smc->os.hwm.tx_mb,char *) - 1 ;
1716 *(char *)smc->os.hwm.tx_mb->sm_data =
1717 *smc->os.hwm.tx_data ;
1718 smc->os.hwm.tx_data++ ;
1719 smc->os.hwm.tx_mb->sm_len =
1720 smc->os.hwm.tx_len - 1 ;
1721 DB_TX("pass LLC frame to SMT ",0,0,3) ;
1722 smt_received_pack(smc,smc->os.hwm.tx_mb,
1723 RD_FS_LOCAL) ;
1724 }
1725 }
1726 }
1727 NDD_TRACE("THfE",t,queue->tx_free,0) ;
1728}
1729
1730
1731/*
1732 * queues a receive for later send
1733 */
1734static void queue_llc_rx(struct s_smc *smc, SMbuf *mb)
1735{
1736 DB_GEN("queue_llc_rx: mb = %x",(void *)mb,0,4) ;
1737 smc->os.hwm.queued_rx_frames++ ;
1738 mb->sm_next = (SMbuf *)NULL ;
1739 if (smc->os.hwm.llc_rx_pipe == NULL) {
1740 smc->os.hwm.llc_rx_pipe = mb ;
1741 }
1742 else {
1743 smc->os.hwm.llc_rx_tail->sm_next = mb ;
1744 }
1745 smc->os.hwm.llc_rx_tail = mb ;
1746
1747 /*
1748 * force an timer IRQ to receive the data
1749 */
1750 if (!smc->os.hwm.isr_flag) {
1751 smt_force_irq(smc) ;
1752 }
1753}
1754
1755/*
1756 * get a SMbuf from the llc_rx_queue
1757 */
1758static SMbuf *get_llc_rx(struct s_smc *smc)
1759{
1760 SMbuf *mb ;
1761
1762 if ((mb = smc->os.hwm.llc_rx_pipe)) {
1763 smc->os.hwm.queued_rx_frames-- ;
1764 smc->os.hwm.llc_rx_pipe = mb->sm_next ;
1765 }
1766 DB_GEN("get_llc_rx: mb = 0x%x",(void *)mb,0,4) ;
1767 return mb;
1768}
1769
1770/*
1771 * queues a transmit SMT MBuf during the time were the MBuf is
1772 * queued the TxD ring
1773 */
1774static void queue_txd_mb(struct s_smc *smc, SMbuf *mb)
1775{
1776 DB_GEN("_rx: queue_txd_mb = %x",(void *)mb,0,4) ;
1777 smc->os.hwm.queued_txd_mb++ ;
1778 mb->sm_next = (SMbuf *)NULL ;
1779 if (smc->os.hwm.txd_tx_pipe == NULL) {
1780 smc->os.hwm.txd_tx_pipe = mb ;
1781 }
1782 else {
1783 smc->os.hwm.txd_tx_tail->sm_next = mb ;
1784 }
1785 smc->os.hwm.txd_tx_tail = mb ;
1786}
1787
1788/*
1789 * get a SMbuf from the txd_tx_queue
1790 */
1791static SMbuf *get_txd_mb(struct s_smc *smc)
1792{
1793 SMbuf *mb ;
1794
1795 if ((mb = smc->os.hwm.txd_tx_pipe)) {
1796 smc->os.hwm.queued_txd_mb-- ;
1797 smc->os.hwm.txd_tx_pipe = mb->sm_next ;
1798 }
1799 DB_GEN("get_txd_mb: mb = 0x%x",(void *)mb,0,4) ;
1800 return mb;
1801}
1802
1803/*
1804 * SMT Send function
1805 */
1806void smt_send_mbuf(struct s_smc *smc, SMbuf *mb, int fc)
1807{
1808 char far *data ;
1809 int len ;
1810 int n ;
1811 int i ;
1812 int frag_count ;
1813 int frame_status ;
1814 SK_LOC_DECL(char far,*virt[3]) ;
1815 int frag_len[3] ;
1816 struct s_smt_tx_queue *queue ;
1817 struct s_smt_fp_txd volatile *t ;
1818 u_long phys ;
1819 __le32 tbctrl;
1820
1821 NDD_TRACE("THSB",mb,fc,0) ;
1822 DB_TX("smt_send_mbuf: mb = 0x%x, fc = 0x%x",mb,fc,4) ;
1823
1824 mb->sm_off-- ; /* set to fc */
1825 mb->sm_len++ ; /* + fc */
1826 data = smtod(mb,char *) ;
1827 *data = fc ;
1828 if (fc == FC_SMT_LOC)
1829 *data = FC_SMT_INFO ;
1830
1831 /*
1832 * determine the frag count and the virt addresses of the frags
1833 */
1834 frag_count = 0 ;
1835 len = mb->sm_len ;
1836 while (len) {
1837 n = SMT_PAGESIZE - ((long)data & (SMT_PAGESIZE-1)) ;
1838 if (n >= len) {
1839 n = len ;
1840 }
1841 DB_TX("frag: virt/len = 0x%x/%d ",(void *)data,n,5) ;
1842 virt[frag_count] = data ;
1843 frag_len[frag_count] = n ;
1844 frag_count++ ;
1845 len -= n ;
1846 data += n ;
1847 }
1848
1849 /*
1850 * determine the frame status
1851 */
1852 queue = smc->hw.fp.tx[QUEUE_A0] ;
1853 if (fc == FC_BEACON || fc == FC_SMT_LOC) {
1854 frame_status = LOC_TX ;
1855 }
1856 else {
1857 frame_status = LAN_TX ;
1858 if ((smc->os.hwm.pass_NSA &&(fc == FC_SMT_NSA)) ||
1859 (smc->os.hwm.pass_SMT &&(fc == FC_SMT_INFO)))
1860 frame_status |= LOC_TX ;
1861 }
1862
1863 if (!smc->hw.mac_ring_is_up || frag_count > queue->tx_free) {
1864 frame_status &= ~LAN_TX;
1865 if (frame_status) {
1866 DB_TX("Ring is down: terminate LAN_TX",0,0,2) ;
1867 }
1868 else {
1869 DB_TX("Ring is down: terminate transmission",0,0,2) ;
1870 smt_free_mbuf(smc,mb) ;
1871 return ;
1872 }
1873 }
1874 DB_TX("frame_status = 0x%x ",frame_status,0,5) ;
1875
1876 if ((frame_status & LAN_TX) && (frame_status & LOC_TX)) {
1877 mb->sm_use_count = 2 ;
1878 }
1879
1880 if (frame_status & LAN_TX) {
1881 t = queue->tx_curr_put ;
1882 frame_status |= FIRST_FRAG ;
1883 for (i = 0; i < frag_count; i++) {
1884 DB_TX("init TxD = 0x%x",(void *)t,0,5) ;
1885 if (i == frag_count-1) {
1886 frame_status |= LAST_FRAG ;
1887 t->txd_txdscr = cpu_to_le32(TX_DESCRIPTOR |
1888 (((__u32)(mb->sm_len-1)&3) << 27)) ;
1889 }
1890 t->txd_virt = virt[i] ;
1891 phys = dma_master(smc, (void far *)virt[i],
1892 frag_len[i], DMA_RD|SMT_BUF) ;
1893 t->txd_tbadr = cpu_to_le32(phys) ;
1894 tbctrl = cpu_to_le32((((__u32)frame_status &
1895 (FIRST_FRAG|LAST_FRAG)) << 26) |
1896 BMU_OWN | BMU_CHECK | BMU_SMT_TX |frag_len[i]) ;
1897 t->txd_tbctrl = tbctrl ;
1898#ifndef AIX
1899 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1900 outpd(queue->tx_bmu_ctl,CSR_START) ;
1901#else
1902 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
1903 outpd(ADDR(B0_XA_CSR),CSR_START) ;
1904#endif
1905 frame_status &= ~FIRST_FRAG ;
1906 queue->tx_curr_put = t = t->txd_next ;
1907 queue->tx_free-- ;
1908 queue->tx_used++ ;
1909 }
1910 smc->mib.m[MAC0].fddiMACTransmit_Ct++ ;
1911 queue_txd_mb(smc,mb) ;
1912 }
1913
1914 if (frame_status & LOC_TX) {
1915 DB_TX("pass Mbuf to LLC queue",0,0,5) ;
1916 queue_llc_rx(smc,mb) ;
1917 }
1918
1919 /*
1920 * We need to unqueue the free SMT_MBUFs here, because it may
1921 * be that the SMT want's to send more than 1 frame for one down call
1922 */
1923 mac_drv_clear_txd(smc) ;
1924 NDD_TRACE("THSE",t,queue->tx_free,frag_count) ;
1925}
1926
1927/* BEGIN_MANUAL_ENTRY(mac_drv_clear_txd)
1928 * void mac_drv_clear_txd(smc)
1929 *
1930 * function DOWNCALL (hardware module, hwmtm.c)
1931 * mac_drv_clear_txd searches in both send queues for TxD's
1932 * which were finished by the adapter. It calls dma_complete
1933 * for each TxD. If the last fragment of an LLC frame is
1934 * reached, it calls mac_drv_tx_complete to release the
1935 * send buffer.
1936 *
1937 * return nothing
1938 *
1939 * END_MANUAL_ENTRY
1940 */
1941static void mac_drv_clear_txd(struct s_smc *smc)
1942{
1943 struct s_smt_tx_queue *queue ;
1944 struct s_smt_fp_txd volatile *t1 ;
1945 struct s_smt_fp_txd volatile *t2 = NULL ;
1946 SMbuf *mb ;
1947 u_long tbctrl ;
1948 int i ;
1949 int frag_count ;
1950 int n ;
1951
1952 NDD_TRACE("THcB",0,0,0) ;
1953 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
1954 queue = smc->hw.fp.tx[i] ;
1955 t1 = queue->tx_curr_get ;
1956 DB_TX("clear_txd: QUEUE = %d (0=sync/1=async)",i,0,5) ;
1957
1958 for ( ; ; ) {
1959 frag_count = 0 ;
1960
1961 do {
1962 DRV_BUF_FLUSH(t1,DDI_DMA_SYNC_FORCPU) ;
1963 DB_TX("check OWN/EOF bit of TxD 0x%x",t1,0,5) ;
1964 tbctrl = le32_to_cpu(CR_READ(t1->txd_tbctrl));
1965
1966 if (tbctrl & BMU_OWN || !queue->tx_used){
1967 DB_TX("End of TxDs queue %d",i,0,4) ;
1968 goto free_next_queue ; /* next queue */
1969 }
1970 t1 = t1->txd_next ;
1971 frag_count++ ;
1972 } while (!(tbctrl & BMU_EOF)) ;
1973
1974 t1 = queue->tx_curr_get ;
1975 for (n = frag_count; n; n--) {
1976 tbctrl = le32_to_cpu(t1->txd_tbctrl) ;
1977 dma_complete(smc,
1978 (union s_fp_descr volatile *) t1,
1979 (int) (DMA_RD |
1980 ((tbctrl & BMU_SMT_TX) >> 18))) ;
1981 t2 = t1 ;
1982 t1 = t1->txd_next ;
1983 }
1984
1985 if (tbctrl & BMU_SMT_TX) {
1986 mb = get_txd_mb(smc) ;
1987 smt_free_mbuf(smc,mb) ;
1988 }
1989 else {
1990#ifndef PASS_1ST_TXD_2_TX_COMP
1991 DB_TX("mac_drv_tx_comp for TxD 0x%x",t2,0,4) ;
1992 mac_drv_tx_complete(smc,t2) ;
1993#else
1994 DB_TX("mac_drv_tx_comp for TxD 0x%x",
1995 queue->tx_curr_get,0,4) ;
1996 mac_drv_tx_complete(smc,queue->tx_curr_get) ;
1997#endif
1998 }
1999 queue->tx_curr_get = t1 ;
2000 queue->tx_free += frag_count ;
2001 queue->tx_used -= frag_count ;
2002 }
2003free_next_queue: ;
2004 }
2005 NDD_TRACE("THcE",0,0,0) ;
2006}
2007
2008/*
2009 * BEGINN_MANUAL_ENTRY(mac_drv_clear_tx_queue)
2010 *
2011 * void mac_drv_clear_tx_queue(smc)
2012 * struct s_smc *smc ;
2013 *
2014 * function DOWNCALL (hardware module, hwmtm.c)
2015 * mac_drv_clear_tx_queue is called from the SMT when
2016 * the RMT state machine has entered the ISOLATE state.
2017 * This function is also called by the os-specific module
2018 * after it has called the function card_stop().
2019 * In this case, the frames in the send queues are obsolete and
2020 * should be removed.
2021 *
2022 * note calling sequence:
2023 * CLI_FBI(), card_stop(),
2024 * mac_drv_clear_tx_queue(), mac_drv_clear_rx_queue(),
2025 *
2026 * NOTE: The caller is responsible that the BMUs are idle
2027 * when this function is called.
2028 *
2029 * END_MANUAL_ENTRY
2030 */
2031void mac_drv_clear_tx_queue(struct s_smc *smc)
2032{
2033 struct s_smt_fp_txd volatile *t ;
2034 struct s_smt_tx_queue *queue ;
2035 int tx_used ;
2036 int i ;
2037
2038 if (smc->hw.hw_state != STOPPED) {
2039 SK_BREAK() ;
2040 SMT_PANIC(smc,HWM_E0011,HWM_E0011_MSG) ;
2041 return ;
2042 }
2043
2044 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2045 queue = smc->hw.fp.tx[i] ;
2046 DB_TX("clear_tx_queue: QUEUE = %d (0=sync/1=async)",i,0,5) ;
2047
2048 /*
2049 * switch the OWN bit of all pending frames to the host
2050 */
2051 t = queue->tx_curr_get ;
2052 tx_used = queue->tx_used ;
2053 while (tx_used) {
2054 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORCPU) ;
2055 DB_TX("switch OWN bit of TxD 0x%x ",t,0,5) ;
2056 t->txd_tbctrl &= ~cpu_to_le32(BMU_OWN) ;
2057 DRV_BUF_FLUSH(t,DDI_DMA_SYNC_FORDEV) ;
2058 t = t->txd_next ;
2059 tx_used-- ;
2060 }
2061 }
2062
2063 /*
2064 * release all TxD's for both send queues
2065 */
2066 mac_drv_clear_txd(smc) ;
2067
2068 for (i = QUEUE_S; i <= QUEUE_A0; i++) {
2069 queue = smc->hw.fp.tx[i] ;
2070 t = queue->tx_curr_get ;
2071
2072 /*
2073 * write the phys pointer of the NEXT descriptor into the
2074 * BMU's current address descriptor pointer and set
2075 * tx_curr_get and tx_curr_put to this position
2076 */
2077 if (i == QUEUE_S) {
2078 outpd(ADDR(B5_XS_DA),le32_to_cpu(t->txd_ntdadr)) ;
2079 }
2080 else {
2081 outpd(ADDR(B5_XA_DA),le32_to_cpu(t->txd_ntdadr)) ;
2082 }
2083
2084 queue->tx_curr_put = queue->tx_curr_get->txd_next ;
2085 queue->tx_curr_get = queue->tx_curr_put ;
2086 }
2087}
2088
2089
2090/*
2091 -------------------------------------------------------------
2092 TEST FUNCTIONS:
2093 -------------------------------------------------------------
2094*/
2095
2096#ifdef DEBUG
2097/*
2098 * BEGIN_MANUAL_ENTRY(mac_drv_debug_lev)
2099 * void mac_drv_debug_lev(smc,flag,lev)
2100 *
2101 * function DOWNCALL (drvsr.c)
2102 * To get a special debug info the user can assign a debug level
2103 * to any debug flag.
2104 *
2105 * para flag debug flag, possible values are:
2106 * = 0: reset all debug flags (the defined level is
2107 * ignored)
2108 * = 1: debug.d_smtf
2109 * = 2: debug.d_smt
2110 * = 3: debug.d_ecm
2111 * = 4: debug.d_rmt
2112 * = 5: debug.d_cfm
2113 * = 6: debug.d_pcm
2114 *
2115 * = 10: debug.d_os.hwm_rx (hardware module receive path)
2116 * = 11: debug.d_os.hwm_tx(hardware module transmit path)
2117 * = 12: debug.d_os.hwm_gen(hardware module general flag)
2118 *
2119 * lev debug level
2120 *
2121 * END_MANUAL_ENTRY
2122 */
2123void mac_drv_debug_lev(struct s_smc *smc, int flag, int lev)
2124{
2125 switch(flag) {
2126 case (int)NULL:
2127 DB_P.d_smtf = DB_P.d_smt = DB_P.d_ecm = DB_P.d_rmt = 0 ;
2128 DB_P.d_cfm = 0 ;
2129 DB_P.d_os.hwm_rx = DB_P.d_os.hwm_tx = DB_P.d_os.hwm_gen = 0 ;
2130#ifdef SBA
2131 DB_P.d_sba = 0 ;
2132#endif
2133#ifdef ESS
2134 DB_P.d_ess = 0 ;
2135#endif
2136 break ;
2137 case DEBUG_SMTF:
2138 DB_P.d_smtf = lev ;
2139 break ;
2140 case DEBUG_SMT:
2141 DB_P.d_smt = lev ;
2142 break ;
2143 case DEBUG_ECM:
2144 DB_P.d_ecm = lev ;
2145 break ;
2146 case DEBUG_RMT:
2147 DB_P.d_rmt = lev ;
2148 break ;
2149 case DEBUG_CFM:
2150 DB_P.d_cfm = lev ;
2151 break ;
2152 case DEBUG_PCM:
2153 DB_P.d_pcm = lev ;
2154 break ;
2155 case DEBUG_SBA:
2156#ifdef SBA
2157 DB_P.d_sba = lev ;
2158#endif
2159 break ;
2160 case DEBUG_ESS:
2161#ifdef ESS
2162 DB_P.d_ess = lev ;
2163#endif
2164 break ;
2165 case DB_HWM_RX:
2166 DB_P.d_os.hwm_rx = lev ;
2167 break ;
2168 case DB_HWM_TX:
2169 DB_P.d_os.hwm_tx = lev ;
2170 break ;
2171 case DB_HWM_GEN:
2172 DB_P.d_os.hwm_gen = lev ;
2173 break ;
2174 default:
2175 break ;
2176 }
2177}
2178#endif
diff --git a/drivers/net/skfp/hwt.c b/drivers/net/skfp/hwt.c
deleted file mode 100644
index c0798fd2ca69..000000000000
--- a/drivers/net/skfp/hwt.c
+++ /dev/null
@@ -1,269 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 * Timer Driver for FBI board (timer chip 82C54)
19 */
20
21/*
22 * Modifications:
23 *
24 * 28-Jun-1994 sw Edit v1.6.
25 * MCA: Added support for the SK-NET FDDI-FM2 adapter. The
26 * following functions have been added(+) or modified(*):
27 * hwt_start(*), hwt_stop(*), hwt_restart(*), hwt_read(*)
28 */
29
30#include "h/types.h"
31#include "h/fddi.h"
32#include "h/smc.h"
33
34#ifndef lint
35static const char ID_sccs[] = "@(#)hwt.c 1.13 97/04/23 (C) SK " ;
36#endif
37
38/*
39 * Prototypes of local functions.
40 */
41/* 28-Jun-1994 sw - Note: hwt_restart() is also used in module 'drvfbi.c'. */
42/*static void hwt_restart() ; */
43
44/************************
45 *
46 * hwt_start
47 *
48 * Start hardware timer (clock ticks are 16us).
49 *
50 * void hwt_start(
51 * struct s_smc *smc,
52 * u_long time) ;
53 * In
54 * smc - A pointer to the SMT Context structure.
55 *
56 * time - The time in units of 16us to load the timer with.
57 * Out
58 * Nothing.
59 *
60 ************************/
61#define HWT_MAX (65000)
62
63void hwt_start(struct s_smc *smc, u_long time)
64{
65 u_short cnt ;
66
67 if (time > HWT_MAX)
68 time = HWT_MAX ;
69
70 smc->hw.t_start = time ;
71 smc->hw.t_stop = 0L ;
72
73 cnt = (u_short)time ;
74 /*
75 * if time < 16 us
76 * time = 16 us
77 */
78 if (!cnt)
79 cnt++ ;
80
81 outpd(ADDR(B2_TI_INI), (u_long) cnt * 200) ; /* Load timer value. */
82 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */
83
84 smc->hw.timer_activ = TRUE ;
85}
86
87/************************
88 *
89 * hwt_stop
90 *
91 * Stop hardware timer.
92 *
93 * void hwt_stop(
94 * struct s_smc *smc) ;
95 * In
96 * smc - A pointer to the SMT Context structure.
97 * Out
98 * Nothing.
99 *
100 ************************/
101void hwt_stop(struct s_smc *smc)
102{
103 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
104 outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ;
105
106 smc->hw.timer_activ = FALSE ;
107}
108
109/************************
110 *
111 * hwt_init
112 *
113 * Initialize hardware timer.
114 *
115 * void hwt_init(
116 * struct s_smc *smc) ;
117 * In
118 * smc - A pointer to the SMT Context structure.
119 * Out
120 * Nothing.
121 *
122 ************************/
123void hwt_init(struct s_smc *smc)
124{
125 smc->hw.t_start = 0 ;
126 smc->hw.t_stop = 0 ;
127 smc->hw.timer_activ = FALSE ;
128
129 hwt_restart(smc) ;
130}
131
132/************************
133 *
134 * hwt_restart
135 *
136 * Clear timer interrupt.
137 *
138 * void hwt_restart(
139 * struct s_smc *smc) ;
140 * In
141 * smc - A pointer to the SMT Context structure.
142 * Out
143 * Nothing.
144 *
145 ************************/
146void hwt_restart(struct s_smc *smc)
147{
148 hwt_stop(smc) ;
149}
150
151/************************
152 *
153 * hwt_read
154 *
155 * Stop hardware timer and read time elapsed since last start.
156 *
157 * u_long hwt_read(smc) ;
158 * In
159 * smc - A pointer to the SMT Context structure.
160 * Out
161 * The elapsed time since last start in units of 16us.
162 *
163 ************************/
164u_long hwt_read(struct s_smc *smc)
165{
166 u_short tr ;
167 u_long is ;
168
169 if (smc->hw.timer_activ) {
170 hwt_stop(smc) ;
171 tr = (u_short)((inpd(ADDR(B2_TI_VAL))/200) & 0xffff) ;
172
173 is = GET_ISR() ;
174 /* Check if timer expired (or wraparound). */
175 if ((tr > smc->hw.t_start) || (is & IS_TIMINT)) {
176 hwt_restart(smc) ;
177 smc->hw.t_stop = smc->hw.t_start ;
178 }
179 else
180 smc->hw.t_stop = smc->hw.t_start - tr ;
181 }
182 return smc->hw.t_stop;
183}
184
185#ifdef PCI
186/************************
187 *
188 * hwt_quick_read
189 *
190 * Stop hardware timer and read timer value and start the timer again.
191 *
192 * u_long hwt_read(smc) ;
193 * In
194 * smc - A pointer to the SMT Context structure.
195 * Out
196 * current timer value in units of 80ns.
197 *
198 ************************/
199u_long hwt_quick_read(struct s_smc *smc)
200{
201 u_long interval ;
202 u_long time ;
203
204 interval = inpd(ADDR(B2_TI_INI)) ;
205 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
206 time = inpd(ADDR(B2_TI_VAL)) ;
207 outpd(ADDR(B2_TI_INI),time) ;
208 outpw(ADDR(B2_TI_CRTL), TIM_START) ;
209 outpd(ADDR(B2_TI_INI),interval) ;
210
211 return time;
212}
213
214/************************
215 *
216 * hwt_wait_time(smc,start,duration)
217 *
218 * This function returnes after the amount of time is elapsed
219 * since the start time.
220 *
221 * para start start time
222 * duration time to wait
223 *
224 * NOTE: The function will return immediately, if the timer is not
225 * started
226 ************************/
227void hwt_wait_time(struct s_smc *smc, u_long start, long int duration)
228{
229 long diff ;
230 long interval ;
231 int wrapped ;
232
233 /*
234 * check if timer is running
235 */
236 if (smc->hw.timer_activ == FALSE ||
237 hwt_quick_read(smc) == hwt_quick_read(smc)) {
238 return ;
239 }
240
241 interval = inpd(ADDR(B2_TI_INI)) ;
242 if (interval > duration) {
243 do {
244 diff = (long)(start - hwt_quick_read(smc)) ;
245 if (diff < 0) {
246 diff += interval ;
247 }
248 } while (diff <= duration) ;
249 }
250 else {
251 diff = interval ;
252 wrapped = 0 ;
253 do {
254 if (!wrapped) {
255 if (hwt_quick_read(smc) >= start) {
256 diff += interval ;
257 wrapped = 1 ;
258 }
259 }
260 else {
261 if (hwt_quick_read(smc) < start) {
262 wrapped = 0 ;
263 }
264 }
265 } while (diff <= duration) ;
266 }
267}
268#endif
269
diff --git a/drivers/net/skfp/pcmplc.c b/drivers/net/skfp/pcmplc.c
deleted file mode 100644
index 88d02d0a42c4..000000000000
--- a/drivers/net/skfp/pcmplc.c
+++ /dev/null
@@ -1,2014 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 PCM
19 Physical Connection Management
20*/
21
22/*
23 * Hardware independent state machine implemantation
24 * The following external SMT functions are referenced :
25 *
26 * queue_event()
27 * smt_timer_start()
28 * smt_timer_stop()
29 *
30 * The following external HW dependent functions are referenced :
31 * sm_pm_control()
32 * sm_ph_linestate()
33 * sm_pm_ls_latch()
34 *
35 * The following HW dependent events are required :
36 * PC_QLS
37 * PC_ILS
38 * PC_HLS
39 * PC_MLS
40 * PC_NSE
41 * PC_LEM
42 *
43 */
44
45
46#include "h/types.h"
47#include "h/fddi.h"
48#include "h/smc.h"
49#include "h/supern_2.h"
50#define KERNEL
51#include "h/smtstate.h"
52
53#ifndef lint
54static const char ID_sccs[] = "@(#)pcmplc.c 2.55 99/08/05 (C) SK " ;
55#endif
56
57#ifdef FDDI_MIB
58extern int snmp_fddi_trap(
59#ifdef ANSIC
60struct s_smc * smc, int type, int index
61#endif
62);
63#endif
64#ifdef CONCENTRATOR
65extern int plc_is_installed(
66#ifdef ANSIC
67struct s_smc *smc ,
68int p
69#endif
70) ;
71#endif
72/*
73 * FSM Macros
74 */
75#define AFLAG (0x20)
76#define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
77#define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
78#define ACTIONS(x) (x|AFLAG)
79
80/*
81 * PCM states
82 */
83#define PC0_OFF 0
84#define PC1_BREAK 1
85#define PC2_TRACE 2
86#define PC3_CONNECT 3
87#define PC4_NEXT 4
88#define PC5_SIGNAL 5
89#define PC6_JOIN 6
90#define PC7_VERIFY 7
91#define PC8_ACTIVE 8
92#define PC9_MAINT 9
93
94#ifdef DEBUG
95/*
96 * symbolic state names
97 */
98static const char * const pcm_states[] = {
99 "PC0_OFF","PC1_BREAK","PC2_TRACE","PC3_CONNECT","PC4_NEXT",
100 "PC5_SIGNAL","PC6_JOIN","PC7_VERIFY","PC8_ACTIVE","PC9_MAINT"
101} ;
102
103/*
104 * symbolic event names
105 */
106static const char * const pcm_events[] = {
107 "NONE","PC_START","PC_STOP","PC_LOOP","PC_JOIN","PC_SIGNAL",
108 "PC_REJECT","PC_MAINT","PC_TRACE","PC_PDR",
109 "PC_ENABLE","PC_DISABLE",
110 "PC_QLS","PC_ILS","PC_MLS","PC_HLS","PC_LS_PDR","PC_LS_NONE",
111 "PC_TIMEOUT_TB_MAX","PC_TIMEOUT_TB_MIN",
112 "PC_TIMEOUT_C_MIN","PC_TIMEOUT_T_OUT",
113 "PC_TIMEOUT_TL_MIN","PC_TIMEOUT_T_NEXT","PC_TIMEOUT_LCT",
114 "PC_NSE","PC_LEM"
115} ;
116#endif
117
118#ifdef MOT_ELM
119/*
120 * PCL-S control register
121 * this register in the PLC-S controls the scrambling parameters
122 */
123#define PLCS_CONTROL_C_U 0
124#define PLCS_CONTROL_C_S (PL_C_SDOFF_ENABLE | PL_C_SDON_ENABLE | \
125 PL_C_CIPHER_ENABLE)
126#define PLCS_FASSERT_U 0
127#define PLCS_FASSERT_S 0xFd76 /* 52.0 us */
128#define PLCS_FDEASSERT_U 0
129#define PLCS_FDEASSERT_S 0
130#else /* nMOT_ELM */
131/*
132 * PCL-S control register
133 * this register in the PLC-S controls the scrambling parameters
134 * can be patched for ANSI compliance if standard changes
135 */
136static const u_char plcs_control_c_u[17] = "PLC_CNTRL_C_U=\0\0" ;
137static const u_char plcs_control_c_s[17] = "PLC_CNTRL_C_S=\01\02" ;
138
139#define PLCS_CONTROL_C_U (plcs_control_c_u[14] | (plcs_control_c_u[15]<<8))
140#define PLCS_CONTROL_C_S (plcs_control_c_s[14] | (plcs_control_c_s[15]<<8))
141#endif /* nMOT_ELM */
142
143/*
144 * external vars
145 */
146/* struct definition see 'cmtdef.h' (also used by CFM) */
147
148#define PS_OFF 0
149#define PS_BIT3 1
150#define PS_BIT4 2
151#define PS_BIT7 3
152#define PS_LCT 4
153#define PS_BIT8 5
154#define PS_JOIN 6
155#define PS_ACTIVE 7
156
157#define LCT_LEM_MAX 255
158
159/*
160 * PLC timing parameter
161 */
162
163#define PLC_MS(m) ((int)((0x10000L-(m*100000L/2048))))
164#define SLOW_TL_MIN PLC_MS(6)
165#define SLOW_C_MIN PLC_MS(10)
166
167static const struct plt {
168 int timer ; /* relative plc timer address */
169 int para ; /* default timing parameters */
170} pltm[] = {
171 { PL_C_MIN, SLOW_C_MIN }, /* min t. to remain Connect State */
172 { PL_TL_MIN, SLOW_TL_MIN }, /* min t. to transmit a Line State */
173 { PL_TB_MIN, TP_TB_MIN }, /* min break time */
174 { PL_T_OUT, TP_T_OUT }, /* Signaling timeout */
175 { PL_LC_LENGTH, TP_LC_LENGTH }, /* Link Confidence Test Time */
176 { PL_T_SCRUB, TP_T_SCRUB }, /* Scrub Time == MAC TVX time ! */
177 { PL_NS_MAX, TP_NS_MAX }, /* max t. that noise is tolerated */
178 { 0,0 }
179} ;
180
181/*
182 * interrupt mask
183 */
184#ifdef SUPERNET_3
185/*
186 * Do we need the EBUF error during signaling, too, to detect SUPERNET_3
187 * PLL bug?
188 */
189static const int plc_imsk_na = PL_PCM_CODE | PL_TRACE_PROP | PL_PCM_BREAK |
190 PL_PCM_ENABLED | PL_SELF_TEST | PL_EBUF_ERR;
191#else /* SUPERNET_3 */
192/*
193 * We do NOT need the elasticity buffer error during signaling.
194 */
195static int plc_imsk_na = PL_PCM_CODE | PL_TRACE_PROP | PL_PCM_BREAK |
196 PL_PCM_ENABLED | PL_SELF_TEST ;
197#endif /* SUPERNET_3 */
198static const int plc_imsk_act = PL_PCM_CODE | PL_TRACE_PROP | PL_PCM_BREAK |
199 PL_PCM_ENABLED | PL_SELF_TEST | PL_EBUF_ERR;
200
201/* internal functions */
202static void pcm_fsm(struct s_smc *smc, struct s_phy *phy, int cmd);
203static void pc_rcode_actions(struct s_smc *smc, int bit, struct s_phy *phy);
204static void pc_tcode_actions(struct s_smc *smc, const int bit, struct s_phy *phy);
205static void reset_lem_struct(struct s_phy *phy);
206static void plc_init(struct s_smc *smc, int p);
207static void sm_ph_lem_start(struct s_smc *smc, int np, int threshold);
208static void sm_ph_lem_stop(struct s_smc *smc, int np);
209static void sm_ph_linestate(struct s_smc *smc, int phy, int ls);
210static void real_init_plc(struct s_smc *smc);
211
212/*
213 * SMT timer interface
214 * start PCM timer 0
215 */
216static void start_pcm_timer0(struct s_smc *smc, u_long value, int event,
217 struct s_phy *phy)
218{
219 phy->timer0_exp = FALSE ; /* clear timer event flag */
220 smt_timer_start(smc,&phy->pcm_timer0,value,
221 EV_TOKEN(EVENT_PCM+phy->np,event)) ;
222}
223/*
224 * SMT timer interface
225 * stop PCM timer 0
226 */
227static void stop_pcm_timer0(struct s_smc *smc, struct s_phy *phy)
228{
229 if (phy->pcm_timer0.tm_active)
230 smt_timer_stop(smc,&phy->pcm_timer0) ;
231}
232
233/*
234 init PCM state machine (called by driver)
235 clear all PCM vars and flags
236*/
237void pcm_init(struct s_smc *smc)
238{
239 int i ;
240 int np ;
241 struct s_phy *phy ;
242 struct fddi_mib_p *mib ;
243
244 for (np = 0,phy = smc->y ; np < NUMPHYS ; np++,phy++) {
245 /* Indicates the type of PHY being used */
246 mib = phy->mib ;
247 mib->fddiPORTPCMState = ACTIONS(PC0_OFF) ;
248 phy->np = np ;
249 switch (smc->s.sas) {
250#ifdef CONCENTRATOR
251 case SMT_SAS :
252 mib->fddiPORTMy_Type = (np == PS) ? TS : TM ;
253 break ;
254 case SMT_DAS :
255 mib->fddiPORTMy_Type = (np == PA) ? TA :
256 (np == PB) ? TB : TM ;
257 break ;
258 case SMT_NAC :
259 mib->fddiPORTMy_Type = TM ;
260 break;
261#else
262 case SMT_SAS :
263 mib->fddiPORTMy_Type = (np == PS) ? TS : TNONE ;
264 mib->fddiPORTHardwarePresent = (np == PS) ? TRUE :
265 FALSE ;
266#ifndef SUPERNET_3
267 smc->y[PA].mib->fddiPORTPCMState = PC0_OFF ;
268#else
269 smc->y[PB].mib->fddiPORTPCMState = PC0_OFF ;
270#endif
271 break ;
272 case SMT_DAS :
273 mib->fddiPORTMy_Type = (np == PB) ? TB : TA ;
274 break ;
275#endif
276 }
277 /*
278 * set PMD-type
279 */
280 phy->pmd_scramble = 0 ;
281 switch (phy->pmd_type[PMD_SK_PMD]) {
282 case 'P' :
283 mib->fddiPORTPMDClass = MIB_PMDCLASS_MULTI ;
284 break ;
285 case 'L' :
286 mib->fddiPORTPMDClass = MIB_PMDCLASS_LCF ;
287 break ;
288 case 'D' :
289 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
290 break ;
291 case 'S' :
292 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
293 phy->pmd_scramble = TRUE ;
294 break ;
295 case 'U' :
296 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
297 phy->pmd_scramble = TRUE ;
298 break ;
299 case '1' :
300 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE1 ;
301 break ;
302 case '2' :
303 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE2 ;
304 break ;
305 case '3' :
306 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE2 ;
307 break ;
308 case '4' :
309 mib->fddiPORTPMDClass = MIB_PMDCLASS_SINGLE1 ;
310 break ;
311 case 'H' :
312 mib->fddiPORTPMDClass = MIB_PMDCLASS_UNKNOWN ;
313 break ;
314 case 'I' :
315 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
316 break ;
317 case 'G' :
318 mib->fddiPORTPMDClass = MIB_PMDCLASS_TP ;
319 break ;
320 default:
321 mib->fddiPORTPMDClass = MIB_PMDCLASS_UNKNOWN ;
322 break ;
323 }
324 /*
325 * A and B port can be on primary and secondary path
326 */
327 switch (mib->fddiPORTMy_Type) {
328 case TA :
329 mib->fddiPORTAvailablePaths |= MIB_PATH_S ;
330 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
331 mib->fddiPORTRequestedPaths[2] =
332 MIB_P_PATH_LOCAL |
333 MIB_P_PATH_CON_ALTER |
334 MIB_P_PATH_SEC_PREFER ;
335 mib->fddiPORTRequestedPaths[3] =
336 MIB_P_PATH_LOCAL |
337 MIB_P_PATH_CON_ALTER |
338 MIB_P_PATH_SEC_PREFER |
339 MIB_P_PATH_THRU ;
340 break ;
341 case TB :
342 mib->fddiPORTAvailablePaths |= MIB_PATH_S ;
343 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
344 mib->fddiPORTRequestedPaths[2] =
345 MIB_P_PATH_LOCAL |
346 MIB_P_PATH_PRIM_PREFER ;
347 mib->fddiPORTRequestedPaths[3] =
348 MIB_P_PATH_LOCAL |
349 MIB_P_PATH_PRIM_PREFER |
350 MIB_P_PATH_CON_PREFER |
351 MIB_P_PATH_THRU ;
352 break ;
353 case TS :
354 mib->fddiPORTAvailablePaths |= MIB_PATH_S ;
355 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
356 mib->fddiPORTRequestedPaths[2] =
357 MIB_P_PATH_LOCAL |
358 MIB_P_PATH_CON_ALTER |
359 MIB_P_PATH_PRIM_PREFER ;
360 mib->fddiPORTRequestedPaths[3] =
361 MIB_P_PATH_LOCAL |
362 MIB_P_PATH_CON_ALTER |
363 MIB_P_PATH_PRIM_PREFER ;
364 break ;
365 case TM :
366 mib->fddiPORTRequestedPaths[1] = MIB_P_PATH_LOCAL ;
367 mib->fddiPORTRequestedPaths[2] =
368 MIB_P_PATH_LOCAL |
369 MIB_P_PATH_SEC_ALTER |
370 MIB_P_PATH_PRIM_ALTER ;
371 mib->fddiPORTRequestedPaths[3] = 0 ;
372 break ;
373 }
374
375 phy->pc_lem_fail = FALSE ;
376 mib->fddiPORTPCMStateX = mib->fddiPORTPCMState ;
377 mib->fddiPORTLCTFail_Ct = 0 ;
378 mib->fddiPORTBS_Flag = 0 ;
379 mib->fddiPORTCurrentPath = MIB_PATH_ISOLATED ;
380 mib->fddiPORTNeighborType = TNONE ;
381 phy->ls_flag = 0 ;
382 phy->rc_flag = 0 ;
383 phy->tc_flag = 0 ;
384 phy->td_flag = 0 ;
385 if (np >= PM)
386 phy->phy_name = '0' + np - PM ;
387 else
388 phy->phy_name = 'A' + np ;
389 phy->wc_flag = FALSE ; /* set by SMT */
390 memset((char *)&phy->lem,0,sizeof(struct lem_counter)) ;
391 reset_lem_struct(phy) ;
392 memset((char *)&phy->plc,0,sizeof(struct s_plc)) ;
393 phy->plc.p_state = PS_OFF ;
394 for (i = 0 ; i < NUMBITS ; i++) {
395 phy->t_next[i] = 0 ;
396 }
397 }
398 real_init_plc(smc) ;
399}
400
401void init_plc(struct s_smc *smc)
402{
403 SK_UNUSED(smc) ;
404
405 /*
406 * dummy
407 * this is an obsolete public entry point that has to remain
408 * for compat. It is used by various drivers.
409 * the work is now done in real_init_plc()
410 * which is called from pcm_init() ;
411 */
412}
413
414static void real_init_plc(struct s_smc *smc)
415{
416 int p ;
417
418 for (p = 0 ; p < NUMPHYS ; p++)
419 plc_init(smc,p) ;
420}
421
422static void plc_init(struct s_smc *smc, int p)
423{
424 int i ;
425#ifndef MOT_ELM
426 int rev ; /* Revision of PLC-x */
427#endif /* MOT_ELM */
428
429 /* transit PCM state machine to MAINT state */
430 outpw(PLC(p,PL_CNTRL_B),0) ;
431 outpw(PLC(p,PL_CNTRL_B),PL_PCM_STOP) ;
432 outpw(PLC(p,PL_CNTRL_A),0) ;
433
434 /*
435 * if PLC-S then set control register C
436 */
437#ifndef MOT_ELM
438 rev = inpw(PLC(p,PL_STATUS_A)) & PLC_REV_MASK ;
439 if (rev != PLC_REVISION_A)
440#endif /* MOT_ELM */
441 {
442 if (smc->y[p].pmd_scramble) {
443 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_S) ;
444#ifdef MOT_ELM
445 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_S) ;
446 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_S) ;
447#endif /* MOT_ELM */
448 }
449 else {
450 outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_U) ;
451#ifdef MOT_ELM
452 outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_U) ;
453 outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_U) ;
454#endif /* MOT_ELM */
455 }
456 }
457
458 /*
459 * set timer register
460 */
461 for ( i = 0 ; pltm[i].timer; i++) /* set timer parameter reg */
462 outpw(PLC(p,pltm[i].timer),pltm[i].para) ;
463
464 (void)inpw(PLC(p,PL_INTR_EVENT)) ; /* clear interrupt event reg */
465 plc_clear_irq(smc,p) ;
466 outpw(PLC(p,PL_INTR_MASK),plc_imsk_na); /* enable non active irq's */
467
468 /*
469 * if PCM is configured for class s, it will NOT go to the
470 * REMOVE state if offline (page 3-36;)
471 * in the concentrator, all inactive PHYS always must be in
472 * the remove state
473 * there's no real need to use this feature at all ..
474 */
475#ifndef CONCENTRATOR
476 if ((smc->s.sas == SMT_SAS) && (p == PS)) {
477 outpw(PLC(p,PL_CNTRL_B),PL_CLASS_S) ;
478 }
479#endif
480}
481
482/*
483 * control PCM state machine
484 */
485static void plc_go_state(struct s_smc *smc, int p, int state)
486{
487 HW_PTR port ;
488 int val ;
489
490 SK_UNUSED(smc) ;
491
492 port = (HW_PTR) (PLC(p,PL_CNTRL_B)) ;
493 val = inpw(port) & ~(PL_PCM_CNTRL | PL_MAINT) ;
494 outpw(port,val) ;
495 outpw(port,val | state) ;
496}
497
498/*
499 * read current line state (called by ECM & PCM)
500 */
501int sm_pm_get_ls(struct s_smc *smc, int phy)
502{
503 int state ;
504
505#ifdef CONCENTRATOR
506 if (!plc_is_installed(smc,phy))
507 return PC_QLS;
508#endif
509
510 state = inpw(PLC(phy,PL_STATUS_A)) & PL_LINE_ST ;
511 switch(state) {
512 case PL_L_QLS:
513 state = PC_QLS ;
514 break ;
515 case PL_L_MLS:
516 state = PC_MLS ;
517 break ;
518 case PL_L_HLS:
519 state = PC_HLS ;
520 break ;
521 case PL_L_ILS4:
522 case PL_L_ILS16:
523 state = PC_ILS ;
524 break ;
525 case PL_L_ALS:
526 state = PC_LS_PDR ;
527 break ;
528 default :
529 state = PC_LS_NONE ;
530 }
531 return state;
532}
533
534static int plc_send_bits(struct s_smc *smc, struct s_phy *phy, int len)
535{
536 int np = phy->np ; /* PHY index */
537 int n ;
538 int i ;
539
540 SK_UNUSED(smc) ;
541
542 /* create bit vector */
543 for (i = len-1,n = 0 ; i >= 0 ; i--) {
544 n = (n<<1) | phy->t_val[phy->bitn+i] ;
545 }
546 if (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL) {
547#if 0
548 printf("PL_PCM_SIGNAL is set\n") ;
549#endif
550 return 1;
551 }
552 /* write bit[n] & length = 1 to regs */
553 outpw(PLC(np,PL_VECTOR_LEN),len-1) ; /* len=nr-1 */
554 outpw(PLC(np,PL_XMIT_VECTOR),n) ;
555#ifdef DEBUG
556#if 1
557#ifdef DEBUG_BRD
558 if (smc->debug.d_plc & 0x80)
559#else
560 if (debug.d_plc & 0x80)
561#endif
562 printf("SIGNALING bit %d .. %d\n",phy->bitn,phy->bitn+len-1) ;
563#endif
564#endif
565 return 0;
566}
567
568/*
569 * config plc muxes
570 */
571void plc_config_mux(struct s_smc *smc, int mux)
572{
573 if (smc->s.sas != SMT_DAS)
574 return ;
575 if (mux == MUX_WRAPB) {
576 SETMASK(PLC(PA,PL_CNTRL_B),PL_CONFIG_CNTRL,PL_CONFIG_CNTRL) ;
577 SETMASK(PLC(PA,PL_CNTRL_A),PL_SC_REM_LOOP,PL_SC_REM_LOOP) ;
578 }
579 else {
580 CLEAR(PLC(PA,PL_CNTRL_B),PL_CONFIG_CNTRL) ;
581 CLEAR(PLC(PA,PL_CNTRL_A),PL_SC_REM_LOOP) ;
582 }
583 CLEAR(PLC(PB,PL_CNTRL_B),PL_CONFIG_CNTRL) ;
584 CLEAR(PLC(PB,PL_CNTRL_A),PL_SC_REM_LOOP) ;
585}
586
587/*
588 PCM state machine
589 called by dispatcher & fddi_init() (driver)
590 do
591 display state change
592 process event
593 until SM is stable
594*/
595void pcm(struct s_smc *smc, const int np, int event)
596{
597 int state ;
598 int oldstate ;
599 struct s_phy *phy ;
600 struct fddi_mib_p *mib ;
601
602#ifndef CONCENTRATOR
603 /*
604 * ignore 2nd PHY if SAS
605 */
606 if ((np != PS) && (smc->s.sas == SMT_SAS))
607 return ;
608#endif
609 phy = &smc->y[np] ;
610 mib = phy->mib ;
611 oldstate = mib->fddiPORTPCMState ;
612 do {
613 DB_PCM("PCM %c: state %s",
614 phy->phy_name,
615 (mib->fddiPORTPCMState & AFLAG) ? "ACTIONS " : "") ;
616 DB_PCM("%s, event %s\n",
617 pcm_states[mib->fddiPORTPCMState & ~AFLAG],
618 pcm_events[event]) ;
619 state = mib->fddiPORTPCMState ;
620 pcm_fsm(smc,phy,event) ;
621 event = 0 ;
622 } while (state != mib->fddiPORTPCMState) ;
623 /*
624 * because the PLC does the bit signaling for us,
625 * we're always in SIGNAL state
626 * the MIB want's to see CONNECT
627 * we therefore fake an entry in the MIB
628 */
629 if (state == PC5_SIGNAL)
630 mib->fddiPORTPCMStateX = PC3_CONNECT ;
631 else
632 mib->fddiPORTPCMStateX = state ;
633
634#ifndef SLIM_SMT
635 /*
636 * path change
637 */
638 if ( mib->fddiPORTPCMState != oldstate &&
639 ((oldstate == PC8_ACTIVE) || (mib->fddiPORTPCMState == PC8_ACTIVE))) {
640 smt_srf_event(smc,SMT_EVENT_PORT_PATH_CHANGE,
641 (int) (INDEX_PORT+ phy->np),0) ;
642 }
643#endif
644
645#ifdef FDDI_MIB
646 /* check whether a snmp-trap has to be sent */
647
648 if ( mib->fddiPORTPCMState != oldstate ) {
649 /* a real state change took place */
650 DB_SNMP ("PCM from %d to %d\n", oldstate, mib->fddiPORTPCMState);
651 if ( mib->fddiPORTPCMState == PC0_OFF ) {
652 /* send first trap */
653 snmp_fddi_trap (smc, 1, (int) mib->fddiPORTIndex );
654 } else if ( oldstate == PC0_OFF ) {
655 /* send second trap */
656 snmp_fddi_trap (smc, 2, (int) mib->fddiPORTIndex );
657 } else if ( mib->fddiPORTPCMState != PC2_TRACE &&
658 oldstate == PC8_ACTIVE ) {
659 /* send third trap */
660 snmp_fddi_trap (smc, 3, (int) mib->fddiPORTIndex );
661 } else if ( mib->fddiPORTPCMState == PC8_ACTIVE ) {
662 /* send fourth trap */
663 snmp_fddi_trap (smc, 4, (int) mib->fddiPORTIndex );
664 }
665 }
666#endif
667
668 pcm_state_change(smc,np,state) ;
669}
670
671/*
672 * PCM state machine
673 */
674static void pcm_fsm(struct s_smc *smc, struct s_phy *phy, int cmd)
675{
676 int i ;
677 int np = phy->np ; /* PHY index */
678 struct s_plc *plc ;
679 struct fddi_mib_p *mib ;
680#ifndef MOT_ELM
681 u_short plc_rev ; /* Revision of the plc */
682#endif /* nMOT_ELM */
683
684 plc = &phy->plc ;
685 mib = phy->mib ;
686
687 /*
688 * general transitions independent of state
689 */
690 switch (cmd) {
691 case PC_STOP :
692 /*PC00-PC80*/
693 if (mib->fddiPORTPCMState != PC9_MAINT) {
694 GO_STATE(PC0_OFF) ;
695 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
696 FDDI_PORT_EVENT, (u_long) FDDI_PORT_STOP,
697 smt_get_port_event_word(smc));
698 }
699 return ;
700 case PC_START :
701 /*PC01-PC81*/
702 if (mib->fddiPORTPCMState != PC9_MAINT)
703 GO_STATE(PC1_BREAK) ;
704 return ;
705 case PC_DISABLE :
706 /* PC09-PC99 */
707 GO_STATE(PC9_MAINT) ;
708 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
709 FDDI_PORT_EVENT, (u_long) FDDI_PORT_DISABLED,
710 smt_get_port_event_word(smc));
711 return ;
712 case PC_TIMEOUT_LCT :
713 /* if long or extended LCT */
714 stop_pcm_timer0(smc,phy) ;
715 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
716 /* end of LCT is indicate by PCM_CODE (initiate PCM event) */
717 return ;
718 }
719
720 switch(mib->fddiPORTPCMState) {
721 case ACTIONS(PC0_OFF) :
722 stop_pcm_timer0(smc,phy) ;
723 outpw(PLC(np,PL_CNTRL_A),0) ;
724 CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
725 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
726 sm_ph_lem_stop(smc,np) ; /* disable LEM */
727 phy->cf_loop = FALSE ;
728 phy->cf_join = FALSE ;
729 queue_event(smc,EVENT_CFM,CF_JOIN+np) ;
730 plc_go_state(smc,np,PL_PCM_STOP) ;
731 mib->fddiPORTConnectState = PCM_DISABLED ;
732 ACTIONS_DONE() ;
733 break ;
734 case PC0_OFF:
735 /*PC09*/
736 if (cmd == PC_MAINT) {
737 GO_STATE(PC9_MAINT) ;
738 break ;
739 }
740 break ;
741 case ACTIONS(PC1_BREAK) :
742 /* Stop the LCT timer if we came from Signal state */
743 stop_pcm_timer0(smc,phy) ;
744 ACTIONS_DONE() ;
745 plc_go_state(smc,np,0) ;
746 CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
747 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
748 sm_ph_lem_stop(smc,np) ; /* disable LEM */
749 /*
750 * if vector is already loaded, go to OFF to clear PCM_SIGNAL
751 */
752#if 0
753 if (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL) {
754 plc_go_state(smc,np,PL_PCM_STOP) ;
755 /* TB_MIN ? */
756 }
757#endif
758 /*
759 * Go to OFF state in any case.
760 */
761 plc_go_state(smc,np,PL_PCM_STOP) ;
762
763 if (mib->fddiPORTPC_Withhold == PC_WH_NONE)
764 mib->fddiPORTConnectState = PCM_CONNECTING ;
765 phy->cf_loop = FALSE ;
766 phy->cf_join = FALSE ;
767 queue_event(smc,EVENT_CFM,CF_JOIN+np) ;
768 phy->ls_flag = FALSE ;
769 phy->pc_mode = PM_NONE ; /* needed by CFM */
770 phy->bitn = 0 ; /* bit signaling start bit */
771 for (i = 0 ; i < 3 ; i++)
772 pc_tcode_actions(smc,i,phy) ;
773
774 /* Set the non-active interrupt mask register */
775 outpw(PLC(np,PL_INTR_MASK),plc_imsk_na) ;
776
777 /*
778 * If the LCT was stopped. There might be a
779 * PCM_CODE interrupt event present.
780 * This must be cleared.
781 */
782 (void)inpw(PLC(np,PL_INTR_EVENT)) ;
783#ifndef MOT_ELM
784 /* Get the plc revision for revision dependent code */
785 plc_rev = inpw(PLC(np,PL_STATUS_A)) & PLC_REV_MASK ;
786
787 if (plc_rev != PLC_REV_SN3)
788#endif /* MOT_ELM */
789 {
790 /*
791 * No supernet III PLC, so set Xmit verctor and
792 * length BEFORE starting the state machine.
793 */
794 if (plc_send_bits(smc,phy,3)) {
795 return ;
796 }
797 }
798
799 /*
800 * Now give the Start command.
801 * - The start command shall be done before setting the bits
802 * to be signaled. (In PLC-S description and PLCS in SN3.
803 * - The start command shall be issued AFTER setting the
804 * XMIT vector and the XMIT length register.
805 *
806 * We do it exactly according this specs for the old PLC and
807 * the new PLCS inside the SN3.
808 * For the usual PLCS we try it the way it is done for the
809 * old PLC and set the XMIT registers again, if the PLC is
810 * not in SIGNAL state. This is done according to an PLCS
811 * errata workaround.
812 */
813
814 plc_go_state(smc,np,PL_PCM_START) ;
815
816 /*
817 * workaround for PLC-S eng. sample errata
818 */
819#ifdef MOT_ELM
820 if (!(inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL))
821#else /* nMOT_ELM */
822 if (((inpw(PLC(np,PL_STATUS_A)) & PLC_REV_MASK) !=
823 PLC_REVISION_A) &&
824 !(inpw(PLC(np,PL_STATUS_B)) & PL_PCM_SIGNAL))
825#endif /* nMOT_ELM */
826 {
827 /*
828 * Set register again (PLCS errata) or the first time
829 * (new SN3 PLCS).
830 */
831 (void) plc_send_bits(smc,phy,3) ;
832 }
833 /*
834 * end of workaround
835 */
836
837 GO_STATE(PC5_SIGNAL) ;
838 plc->p_state = PS_BIT3 ;
839 plc->p_bits = 3 ;
840 plc->p_start = 0 ;
841
842 break ;
843 case PC1_BREAK :
844 break ;
845 case ACTIONS(PC2_TRACE) :
846 plc_go_state(smc,np,PL_PCM_TRACE) ;
847 ACTIONS_DONE() ;
848 break ;
849 case PC2_TRACE :
850 break ;
851
852 case PC3_CONNECT : /* these states are done by hardware */
853 case PC4_NEXT :
854 break ;
855
856 case ACTIONS(PC5_SIGNAL) :
857 ACTIONS_DONE() ;
858 case PC5_SIGNAL :
859 if ((cmd != PC_SIGNAL) && (cmd != PC_TIMEOUT_LCT))
860 break ;
861 switch (plc->p_state) {
862 case PS_BIT3 :
863 for (i = 0 ; i <= 2 ; i++)
864 pc_rcode_actions(smc,i,phy) ;
865 pc_tcode_actions(smc,3,phy) ;
866 plc->p_state = PS_BIT4 ;
867 plc->p_bits = 1 ;
868 plc->p_start = 3 ;
869 phy->bitn = 3 ;
870 if (plc_send_bits(smc,phy,1)) {
871 return ;
872 }
873 break ;
874 case PS_BIT4 :
875 pc_rcode_actions(smc,3,phy) ;
876 for (i = 4 ; i <= 6 ; i++)
877 pc_tcode_actions(smc,i,phy) ;
878 plc->p_state = PS_BIT7 ;
879 plc->p_bits = 3 ;
880 plc->p_start = 4 ;
881 phy->bitn = 4 ;
882 if (plc_send_bits(smc,phy,3)) {
883 return ;
884 }
885 break ;
886 case PS_BIT7 :
887 for (i = 3 ; i <= 6 ; i++)
888 pc_rcode_actions(smc,i,phy) ;
889 plc->p_state = PS_LCT ;
890 plc->p_bits = 0 ;
891 plc->p_start = 7 ;
892 phy->bitn = 7 ;
893 sm_ph_lem_start(smc,np,(int)smc->s.lct_short) ; /* enable LEM */
894 /* start LCT */
895 i = inpw(PLC(np,PL_CNTRL_B)) & ~PL_PC_LOOP ;
896 outpw(PLC(np,PL_CNTRL_B),i) ; /* must be cleared */
897 outpw(PLC(np,PL_CNTRL_B),i | PL_RLBP) ;
898 break ;
899 case PS_LCT :
900 /* check for local LCT failure */
901 pc_tcode_actions(smc,7,phy) ;
902 /*
903 * set tval[7]
904 */
905 plc->p_state = PS_BIT8 ;
906 plc->p_bits = 1 ;
907 plc->p_start = 7 ;
908 phy->bitn = 7 ;
909 if (plc_send_bits(smc,phy,1)) {
910 return ;
911 }
912 break ;
913 case PS_BIT8 :
914 /* check for remote LCT failure */
915 pc_rcode_actions(smc,7,phy) ;
916 if (phy->t_val[7] || phy->r_val[7]) {
917 plc_go_state(smc,np,PL_PCM_STOP) ;
918 GO_STATE(PC1_BREAK) ;
919 break ;
920 }
921 for (i = 8 ; i <= 9 ; i++)
922 pc_tcode_actions(smc,i,phy) ;
923 plc->p_state = PS_JOIN ;
924 plc->p_bits = 2 ;
925 plc->p_start = 8 ;
926 phy->bitn = 8 ;
927 if (plc_send_bits(smc,phy,2)) {
928 return ;
929 }
930 break ;
931 case PS_JOIN :
932 for (i = 8 ; i <= 9 ; i++)
933 pc_rcode_actions(smc,i,phy) ;
934 plc->p_state = PS_ACTIVE ;
935 GO_STATE(PC6_JOIN) ;
936 break ;
937 }
938 break ;
939
940 case ACTIONS(PC6_JOIN) :
941 /*
942 * prevent mux error when going from WRAP_A to WRAP_B
943 */
944 if (smc->s.sas == SMT_DAS && np == PB &&
945 (smc->y[PA].pc_mode == PM_TREE ||
946 smc->y[PB].pc_mode == PM_TREE)) {
947 SETMASK(PLC(np,PL_CNTRL_A),
948 PL_SC_REM_LOOP,PL_SC_REM_LOOP) ;
949 SETMASK(PLC(np,PL_CNTRL_B),
950 PL_CONFIG_CNTRL,PL_CONFIG_CNTRL) ;
951 }
952 SETMASK(PLC(np,PL_CNTRL_B),PL_PC_JOIN,PL_PC_JOIN) ;
953 SETMASK(PLC(np,PL_CNTRL_B),PL_PC_JOIN,PL_PC_JOIN) ;
954 ACTIONS_DONE() ;
955 cmd = 0 ;
956 /* fall thru */
957 case PC6_JOIN :
958 switch (plc->p_state) {
959 case PS_ACTIVE:
960 /*PC88b*/
961 if (!phy->cf_join) {
962 phy->cf_join = TRUE ;
963 queue_event(smc,EVENT_CFM,CF_JOIN+np) ;
964 }
965 if (cmd == PC_JOIN)
966 GO_STATE(PC8_ACTIVE) ;
967 /*PC82*/
968 if (cmd == PC_TRACE) {
969 GO_STATE(PC2_TRACE) ;
970 break ;
971 }
972 break ;
973 }
974 break ;
975
976 case PC7_VERIFY :
977 break ;
978
979 case ACTIONS(PC8_ACTIVE) :
980 /*
981 * start LEM for SMT
982 */
983 sm_ph_lem_start(smc,(int)phy->np,LCT_LEM_MAX) ;
984
985 phy->tr_flag = FALSE ;
986 mib->fddiPORTConnectState = PCM_ACTIVE ;
987
988 /* Set the active interrupt mask register */
989 outpw(PLC(np,PL_INTR_MASK),plc_imsk_act) ;
990
991 ACTIONS_DONE() ;
992 break ;
993 case PC8_ACTIVE :
994 /*PC81 is done by PL_TNE_EXPIRED irq */
995 /*PC82*/
996 if (cmd == PC_TRACE) {
997 GO_STATE(PC2_TRACE) ;
998 break ;
999 }
1000 /*PC88c: is done by TRACE_PROP irq */
1001
1002 break ;
1003 case ACTIONS(PC9_MAINT) :
1004 stop_pcm_timer0(smc,phy) ;
1005 CLEAR(PLC(np,PL_CNTRL_B),PL_PC_JOIN) ;
1006 CLEAR(PLC(np,PL_CNTRL_B),PL_LONG) ;
1007 CLEAR(PLC(np,PL_INTR_MASK),PL_LE_CTR) ; /* disable LEM int. */
1008 sm_ph_lem_stop(smc,np) ; /* disable LEM */
1009 phy->cf_loop = FALSE ;
1010 phy->cf_join = FALSE ;
1011 queue_event(smc,EVENT_CFM,CF_JOIN+np) ;
1012 plc_go_state(smc,np,PL_PCM_STOP) ;
1013 mib->fddiPORTConnectState = PCM_DISABLED ;
1014 SETMASK(PLC(np,PL_CNTRL_B),PL_MAINT,PL_MAINT) ;
1015 sm_ph_linestate(smc,np,(int) MIB2LS(mib->fddiPORTMaint_LS)) ;
1016 outpw(PLC(np,PL_CNTRL_A),PL_SC_BYPASS) ;
1017 ACTIONS_DONE() ;
1018 break ;
1019 case PC9_MAINT :
1020 DB_PCMN(1,"PCM %c : MAINT\n",phy->phy_name,0) ;
1021 /*PC90*/
1022 if (cmd == PC_ENABLE) {
1023 GO_STATE(PC0_OFF) ;
1024 break ;
1025 }
1026 break ;
1027
1028 default:
1029 SMT_PANIC(smc,SMT_E0118, SMT_E0118_MSG) ;
1030 break ;
1031 }
1032}
1033
1034/*
1035 * force line state on a PHY output (only in MAINT state)
1036 */
1037static void sm_ph_linestate(struct s_smc *smc, int phy, int ls)
1038{
1039 int cntrl ;
1040
1041 SK_UNUSED(smc) ;
1042
1043 cntrl = (inpw(PLC(phy,PL_CNTRL_B)) & ~PL_MAINT_LS) |
1044 PL_PCM_STOP | PL_MAINT ;
1045 switch(ls) {
1046 case PC_QLS: /* Force Quiet */
1047 cntrl |= PL_M_QUI0 ;
1048 break ;
1049 case PC_MLS: /* Force Master */
1050 cntrl |= PL_M_MASTR ;
1051 break ;
1052 case PC_HLS: /* Force Halt */
1053 cntrl |= PL_M_HALT ;
1054 break ;
1055 default :
1056 case PC_ILS: /* Force Idle */
1057 cntrl |= PL_M_IDLE ;
1058 break ;
1059 case PC_LS_PDR: /* Enable repeat filter */
1060 cntrl |= PL_M_TPDR ;
1061 break ;
1062 }
1063 outpw(PLC(phy,PL_CNTRL_B),cntrl) ;
1064}
1065
1066static void reset_lem_struct(struct s_phy *phy)
1067{
1068 struct lem_counter *lem = &phy->lem ;
1069
1070 phy->mib->fddiPORTLer_Estimate = 15 ;
1071 lem->lem_float_ber = 15 * 100 ;
1072}
1073
1074/*
1075 * link error monitor
1076 */
1077static void lem_evaluate(struct s_smc *smc, struct s_phy *phy)
1078{
1079 int ber ;
1080 u_long errors ;
1081 struct lem_counter *lem = &phy->lem ;
1082 struct fddi_mib_p *mib ;
1083 int cond ;
1084
1085 mib = phy->mib ;
1086
1087 if (!lem->lem_on)
1088 return ;
1089
1090 errors = inpw(PLC(((int) phy->np),PL_LINK_ERR_CTR)) ;
1091 lem->lem_errors += errors ;
1092 mib->fddiPORTLem_Ct += errors ;
1093
1094 errors = lem->lem_errors ;
1095 /*
1096 * calculation is called on a intervall of 8 seconds
1097 * -> this means, that one error in 8 sec. is one of 8*125*10E6
1098 * the same as BER = 10E-9
1099 * Please note:
1100 * -> 9 errors in 8 seconds mean:
1101 * BER = 9 * 10E-9 and this is
1102 * < 10E-8, so the limit of 10E-8 is not reached!
1103 */
1104
1105 if (!errors) ber = 15 ;
1106 else if (errors <= 9) ber = 9 ;
1107 else if (errors <= 99) ber = 8 ;
1108 else if (errors <= 999) ber = 7 ;
1109 else if (errors <= 9999) ber = 6 ;
1110 else if (errors <= 99999) ber = 5 ;
1111 else if (errors <= 999999) ber = 4 ;
1112 else if (errors <= 9999999) ber = 3 ;
1113 else if (errors <= 99999999) ber = 2 ;
1114 else if (errors <= 999999999) ber = 1 ;
1115 else ber = 0 ;
1116
1117 /*
1118 * weighted average
1119 */
1120 ber *= 100 ;
1121 lem->lem_float_ber = lem->lem_float_ber * 7 + ber * 3 ;
1122 lem->lem_float_ber /= 10 ;
1123 mib->fddiPORTLer_Estimate = lem->lem_float_ber / 100 ;
1124 if (mib->fddiPORTLer_Estimate < 4) {
1125 mib->fddiPORTLer_Estimate = 4 ;
1126 }
1127
1128 if (lem->lem_errors) {
1129 DB_PCMN(1,"LEM %c :\n",phy->np == PB? 'B' : 'A',0) ;
1130 DB_PCMN(1,"errors : %ld\n",lem->lem_errors,0) ;
1131 DB_PCMN(1,"sum_errors : %ld\n",mib->fddiPORTLem_Ct,0) ;
1132 DB_PCMN(1,"current BER : 10E-%d\n",ber/100,0) ;
1133 DB_PCMN(1,"float BER : 10E-(%d/100)\n",lem->lem_float_ber,0) ;
1134 DB_PCMN(1,"avg. BER : 10E-%d\n",
1135 mib->fddiPORTLer_Estimate,0) ;
1136 }
1137
1138 lem->lem_errors = 0L ;
1139
1140#ifndef SLIM_SMT
1141 cond = (mib->fddiPORTLer_Estimate <= mib->fddiPORTLer_Alarm) ?
1142 TRUE : FALSE ;
1143#ifdef SMT_EXT_CUTOFF
1144 smt_ler_alarm_check(smc,phy,cond) ;
1145#endif /* nSMT_EXT_CUTOFF */
1146 if (cond != mib->fddiPORTLerFlag) {
1147 smt_srf_event(smc,SMT_COND_PORT_LER,
1148 (int) (INDEX_PORT+ phy->np) ,cond) ;
1149 }
1150#endif
1151
1152 if ( mib->fddiPORTLer_Estimate <= mib->fddiPORTLer_Cutoff) {
1153 phy->pc_lem_fail = TRUE ; /* flag */
1154 mib->fddiPORTLem_Reject_Ct++ ;
1155 /*
1156 * "forgive 10e-2" if we cutoff so we can come
1157 * up again ..
1158 */
1159 lem->lem_float_ber += 2*100 ;
1160
1161 /*PC81b*/
1162#ifdef CONCENTRATOR
1163 DB_PCMN(1,"PCM: LER cutoff on port %d cutoff %d\n",
1164 phy->np, mib->fddiPORTLer_Cutoff) ;
1165#endif
1166#ifdef SMT_EXT_CUTOFF
1167 smt_port_off_event(smc,phy->np);
1168#else /* nSMT_EXT_CUTOFF */
1169 queue_event(smc,(int)(EVENT_PCM+phy->np),PC_START) ;
1170#endif /* nSMT_EXT_CUTOFF */
1171 }
1172}
1173
1174/*
1175 * called by SMT to calculate LEM bit error rate
1176 */
1177void sm_lem_evaluate(struct s_smc *smc)
1178{
1179 int np ;
1180
1181 for (np = 0 ; np < NUMPHYS ; np++)
1182 lem_evaluate(smc,&smc->y[np]) ;
1183}
1184
1185static void lem_check_lct(struct s_smc *smc, struct s_phy *phy)
1186{
1187 struct lem_counter *lem = &phy->lem ;
1188 struct fddi_mib_p *mib ;
1189 int errors ;
1190
1191 mib = phy->mib ;
1192
1193 phy->pc_lem_fail = FALSE ; /* flag */
1194 errors = inpw(PLC(((int)phy->np),PL_LINK_ERR_CTR)) ;
1195 lem->lem_errors += errors ;
1196 mib->fddiPORTLem_Ct += errors ;
1197 if (lem->lem_errors) {
1198 switch(phy->lc_test) {
1199 case LC_SHORT:
1200 if (lem->lem_errors >= smc->s.lct_short)
1201 phy->pc_lem_fail = TRUE ;
1202 break ;
1203 case LC_MEDIUM:
1204 if (lem->lem_errors >= smc->s.lct_medium)
1205 phy->pc_lem_fail = TRUE ;
1206 break ;
1207 case LC_LONG:
1208 if (lem->lem_errors >= smc->s.lct_long)
1209 phy->pc_lem_fail = TRUE ;
1210 break ;
1211 case LC_EXTENDED:
1212 if (lem->lem_errors >= smc->s.lct_extended)
1213 phy->pc_lem_fail = TRUE ;
1214 break ;
1215 }
1216 DB_PCMN(1," >>errors : %d\n",lem->lem_errors,0) ;
1217 }
1218 if (phy->pc_lem_fail) {
1219 mib->fddiPORTLCTFail_Ct++ ;
1220 mib->fddiPORTLem_Reject_Ct++ ;
1221 }
1222 else
1223 mib->fddiPORTLCTFail_Ct = 0 ;
1224}
1225
1226/*
1227 * LEM functions
1228 */
1229static void sm_ph_lem_start(struct s_smc *smc, int np, int threshold)
1230{
1231 struct lem_counter *lem = &smc->y[np].lem ;
1232
1233 lem->lem_on = 1 ;
1234 lem->lem_errors = 0L ;
1235
1236 /* Do NOT reset mib->fddiPORTLer_Estimate here. It is called too
1237 * often.
1238 */
1239
1240 outpw(PLC(np,PL_LE_THRESHOLD),threshold) ;
1241 (void)inpw(PLC(np,PL_LINK_ERR_CTR)) ; /* clear error counter */
1242
1243 /* enable LE INT */
1244 SETMASK(PLC(np,PL_INTR_MASK),PL_LE_CTR,PL_LE_CTR) ;
1245}
1246
1247static void sm_ph_lem_stop(struct s_smc *smc, int np)
1248{
1249 struct lem_counter *lem = &smc->y[np].lem ;
1250
1251 lem->lem_on = 0 ;
1252 CLEAR(PLC(np,PL_INTR_MASK),PL_LE_CTR) ;
1253}
1254
1255/* ARGSUSED */
1256void sm_pm_ls_latch(struct s_smc *smc, int phy, int on_off)
1257/* int on_off; en- or disable ident. ls */
1258{
1259 SK_UNUSED(smc) ;
1260
1261 phy = phy ; on_off = on_off ;
1262}
1263
1264
1265/*
1266 * PCM pseudo code
1267 * receive actions are called AFTER the bit n is received,
1268 * i.e. if pc_rcode_actions(5) is called, bit 6 is the next bit to be received
1269 */
1270
1271/*
1272 * PCM pseudo code 5.1 .. 6.1
1273 */
1274static void pc_rcode_actions(struct s_smc *smc, int bit, struct s_phy *phy)
1275{
1276 struct fddi_mib_p *mib ;
1277
1278 mib = phy->mib ;
1279
1280 DB_PCMN(1,"SIG rec %x %x:\n", bit,phy->r_val[bit] ) ;
1281 bit++ ;
1282
1283 switch(bit) {
1284 case 0:
1285 case 1:
1286 case 2:
1287 break ;
1288 case 3 :
1289 if (phy->r_val[1] == 0 && phy->r_val[2] == 0)
1290 mib->fddiPORTNeighborType = TA ;
1291 else if (phy->r_val[1] == 0 && phy->r_val[2] == 1)
1292 mib->fddiPORTNeighborType = TB ;
1293 else if (phy->r_val[1] == 1 && phy->r_val[2] == 0)
1294 mib->fddiPORTNeighborType = TS ;
1295 else if (phy->r_val[1] == 1 && phy->r_val[2] == 1)
1296 mib->fddiPORTNeighborType = TM ;
1297 break ;
1298 case 4:
1299 if (mib->fddiPORTMy_Type == TM &&
1300 mib->fddiPORTNeighborType == TM) {
1301 DB_PCMN(1,"PCM %c : E100 withhold M-M\n",
1302 phy->phy_name,0) ;
1303 mib->fddiPORTPC_Withhold = PC_WH_M_M ;
1304 RS_SET(smc,RS_EVENT) ;
1305 }
1306 else if (phy->t_val[3] || phy->r_val[3]) {
1307 mib->fddiPORTPC_Withhold = PC_WH_NONE ;
1308 if (mib->fddiPORTMy_Type == TM ||
1309 mib->fddiPORTNeighborType == TM)
1310 phy->pc_mode = PM_TREE ;
1311 else
1312 phy->pc_mode = PM_PEER ;
1313
1314 /* reevaluate the selection criteria (wc_flag) */
1315 all_selection_criteria (smc);
1316
1317 if (phy->wc_flag) {
1318 mib->fddiPORTPC_Withhold = PC_WH_PATH ;
1319 }
1320 }
1321 else {
1322 mib->fddiPORTPC_Withhold = PC_WH_OTHER ;
1323 RS_SET(smc,RS_EVENT) ;
1324 DB_PCMN(1,"PCM %c : E101 withhold other\n",
1325 phy->phy_name,0) ;
1326 }
1327 phy->twisted = ((mib->fddiPORTMy_Type != TS) &&
1328 (mib->fddiPORTMy_Type != TM) &&
1329 (mib->fddiPORTNeighborType ==
1330 mib->fddiPORTMy_Type)) ;
1331 if (phy->twisted) {
1332 DB_PCMN(1,"PCM %c : E102 !!! TWISTED !!!\n",
1333 phy->phy_name,0) ;
1334 }
1335 break ;
1336 case 5 :
1337 break ;
1338 case 6:
1339 if (phy->t_val[4] || phy->r_val[4]) {
1340 if ((phy->t_val[4] && phy->t_val[5]) ||
1341 (phy->r_val[4] && phy->r_val[5]) )
1342 phy->lc_test = LC_EXTENDED ;
1343 else
1344 phy->lc_test = LC_LONG ;
1345 }
1346 else if (phy->t_val[5] || phy->r_val[5])
1347 phy->lc_test = LC_MEDIUM ;
1348 else
1349 phy->lc_test = LC_SHORT ;
1350 switch (phy->lc_test) {
1351 case LC_SHORT : /* 50ms */
1352 outpw(PLC((int)phy->np,PL_LC_LENGTH), TP_LC_LENGTH ) ;
1353 phy->t_next[7] = smc->s.pcm_lc_short ;
1354 break ;
1355 case LC_MEDIUM : /* 500ms */
1356 outpw(PLC((int)phy->np,PL_LC_LENGTH), TP_LC_LONGLN ) ;
1357 phy->t_next[7] = smc->s.pcm_lc_medium ;
1358 break ;
1359 case LC_LONG :
1360 SETMASK(PLC((int)phy->np,PL_CNTRL_B),PL_LONG,PL_LONG) ;
1361 phy->t_next[7] = smc->s.pcm_lc_long ;
1362 break ;
1363 case LC_EXTENDED :
1364 SETMASK(PLC((int)phy->np,PL_CNTRL_B),PL_LONG,PL_LONG) ;
1365 phy->t_next[7] = smc->s.pcm_lc_extended ;
1366 break ;
1367 }
1368 if (phy->t_next[7] > smc->s.pcm_lc_medium) {
1369 start_pcm_timer0(smc,phy->t_next[7],PC_TIMEOUT_LCT,phy);
1370 }
1371 DB_PCMN(1,"LCT timer = %ld us\n", phy->t_next[7], 0) ;
1372 phy->t_next[9] = smc->s.pcm_t_next_9 ;
1373 break ;
1374 case 7:
1375 if (phy->t_val[6]) {
1376 phy->cf_loop = TRUE ;
1377 }
1378 phy->td_flag = TRUE ;
1379 break ;
1380 case 8:
1381 if (phy->t_val[7] || phy->r_val[7]) {
1382 DB_PCMN(1,"PCM %c : E103 LCT fail %s\n",
1383 phy->phy_name,phy->t_val[7]? "local":"remote") ;
1384 queue_event(smc,(int)(EVENT_PCM+phy->np),PC_START) ;
1385 }
1386 break ;
1387 case 9:
1388 if (phy->t_val[8] || phy->r_val[8]) {
1389 if (phy->t_val[8])
1390 phy->cf_loop = TRUE ;
1391 phy->td_flag = TRUE ;
1392 }
1393 break ;
1394 case 10:
1395 if (phy->r_val[9]) {
1396 /* neighbor intends to have MAC on output */ ;
1397 mib->fddiPORTMacIndicated.R_val = TRUE ;
1398 }
1399 else {
1400 /* neighbor does not intend to have MAC on output */ ;
1401 mib->fddiPORTMacIndicated.R_val = FALSE ;
1402 }
1403 break ;
1404 }
1405}
1406
1407/*
1408 * PCM pseudo code 5.1 .. 6.1
1409 */
1410static void pc_tcode_actions(struct s_smc *smc, const int bit, struct s_phy *phy)
1411{
1412 int np = phy->np ;
1413 struct fddi_mib_p *mib ;
1414
1415 mib = phy->mib ;
1416
1417 switch(bit) {
1418 case 0:
1419 phy->t_val[0] = 0 ; /* no escape used */
1420 break ;
1421 case 1:
1422 if (mib->fddiPORTMy_Type == TS || mib->fddiPORTMy_Type == TM)
1423 phy->t_val[1] = 1 ;
1424 else
1425 phy->t_val[1] = 0 ;
1426 break ;
1427 case 2 :
1428 if (mib->fddiPORTMy_Type == TB || mib->fddiPORTMy_Type == TM)
1429 phy->t_val[2] = 1 ;
1430 else
1431 phy->t_val[2] = 0 ;
1432 break ;
1433 case 3:
1434 {
1435 int type,ne ;
1436 int policy ;
1437
1438 type = mib->fddiPORTMy_Type ;
1439 ne = mib->fddiPORTNeighborType ;
1440 policy = smc->mib.fddiSMTConnectionPolicy ;
1441
1442 phy->t_val[3] = 1 ; /* Accept connection */
1443 switch (type) {
1444 case TA :
1445 if (
1446 ((policy & POLICY_AA) && ne == TA) ||
1447 ((policy & POLICY_AB) && ne == TB) ||
1448 ((policy & POLICY_AS) && ne == TS) ||
1449 ((policy & POLICY_AM) && ne == TM) )
1450 phy->t_val[3] = 0 ; /* Reject */
1451 break ;
1452 case TB :
1453 if (
1454 ((policy & POLICY_BA) && ne == TA) ||
1455 ((policy & POLICY_BB) && ne == TB) ||
1456 ((policy & POLICY_BS) && ne == TS) ||
1457 ((policy & POLICY_BM) && ne == TM) )
1458 phy->t_val[3] = 0 ; /* Reject */
1459 break ;
1460 case TS :
1461 if (
1462 ((policy & POLICY_SA) && ne == TA) ||
1463 ((policy & POLICY_SB) && ne == TB) ||
1464 ((policy & POLICY_SS) && ne == TS) ||
1465 ((policy & POLICY_SM) && ne == TM) )
1466 phy->t_val[3] = 0 ; /* Reject */
1467 break ;
1468 case TM :
1469 if ( ne == TM ||
1470 ((policy & POLICY_MA) && ne == TA) ||
1471 ((policy & POLICY_MB) && ne == TB) ||
1472 ((policy & POLICY_MS) && ne == TS) ||
1473 ((policy & POLICY_MM) && ne == TM) )
1474 phy->t_val[3] = 0 ; /* Reject */
1475 break ;
1476 }
1477#ifndef SLIM_SMT
1478 /*
1479 * detect undesirable connection attempt event
1480 */
1481 if ( (type == TA && ne == TA ) ||
1482 (type == TA && ne == TS ) ||
1483 (type == TB && ne == TB ) ||
1484 (type == TB && ne == TS ) ||
1485 (type == TS && ne == TA ) ||
1486 (type == TS && ne == TB ) ) {
1487 smt_srf_event(smc,SMT_EVENT_PORT_CONNECTION,
1488 (int) (INDEX_PORT+ phy->np) ,0) ;
1489 }
1490#endif
1491 }
1492 break ;
1493 case 4:
1494 if (mib->fddiPORTPC_Withhold == PC_WH_NONE) {
1495 if (phy->pc_lem_fail) {
1496 phy->t_val[4] = 1 ; /* long */
1497 phy->t_val[5] = 0 ;
1498 }
1499 else {
1500 phy->t_val[4] = 0 ;
1501 if (mib->fddiPORTLCTFail_Ct > 0)
1502 phy->t_val[5] = 1 ; /* medium */
1503 else
1504 phy->t_val[5] = 0 ; /* short */
1505
1506 /*
1507 * Implementers choice: use medium
1508 * instead of short when undesired
1509 * connection attempt is made.
1510 */
1511 if (phy->wc_flag)
1512 phy->t_val[5] = 1 ; /* medium */
1513 }
1514 mib->fddiPORTConnectState = PCM_CONNECTING ;
1515 }
1516 else {
1517 mib->fddiPORTConnectState = PCM_STANDBY ;
1518 phy->t_val[4] = 1 ; /* extended */
1519 phy->t_val[5] = 1 ;
1520 }
1521 break ;
1522 case 5:
1523 break ;
1524 case 6:
1525 /* we do NOT have a MAC for LCT */
1526 phy->t_val[6] = 0 ;
1527 break ;
1528 case 7:
1529 phy->cf_loop = FALSE ;
1530 lem_check_lct(smc,phy) ;
1531 if (phy->pc_lem_fail) {
1532 DB_PCMN(1,"PCM %c : E104 LCT failed\n",
1533 phy->phy_name,0) ;
1534 phy->t_val[7] = 1 ;
1535 }
1536 else
1537 phy->t_val[7] = 0 ;
1538 break ;
1539 case 8:
1540 phy->t_val[8] = 0 ; /* Don't request MAC loopback */
1541 break ;
1542 case 9:
1543 phy->cf_loop = 0 ;
1544 if ((mib->fddiPORTPC_Withhold != PC_WH_NONE) ||
1545 ((smc->s.sas == SMT_DAS) && (phy->wc_flag))) {
1546 queue_event(smc,EVENT_PCM+np,PC_START) ;
1547 break ;
1548 }
1549 phy->t_val[9] = FALSE ;
1550 switch (smc->s.sas) {
1551 case SMT_DAS :
1552 /*
1553 * MAC intended on output
1554 */
1555 if (phy->pc_mode == PM_TREE) {
1556 if ((np == PB) || ((np == PA) &&
1557 (smc->y[PB].mib->fddiPORTConnectState !=
1558 PCM_ACTIVE)))
1559 phy->t_val[9] = TRUE ;
1560 }
1561 else {
1562 if (np == PB)
1563 phy->t_val[9] = TRUE ;
1564 }
1565 break ;
1566 case SMT_SAS :
1567 if (np == PS)
1568 phy->t_val[9] = TRUE ;
1569 break ;
1570#ifdef CONCENTRATOR
1571 case SMT_NAC :
1572 /*
1573 * MAC intended on output
1574 */
1575 if (np == PB)
1576 phy->t_val[9] = TRUE ;
1577 break ;
1578#endif
1579 }
1580 mib->fddiPORTMacIndicated.T_val = phy->t_val[9] ;
1581 break ;
1582 }
1583 DB_PCMN(1,"SIG snd %x %x:\n", bit,phy->t_val[bit] ) ;
1584}
1585
1586/*
1587 * return status twisted (called by SMT)
1588 */
1589int pcm_status_twisted(struct s_smc *smc)
1590{
1591 int twist = 0 ;
1592 if (smc->s.sas != SMT_DAS)
1593 return 0;
1594 if (smc->y[PA].twisted && (smc->y[PA].mib->fddiPORTPCMState == PC8_ACTIVE))
1595 twist |= 1 ;
1596 if (smc->y[PB].twisted && (smc->y[PB].mib->fddiPORTPCMState == PC8_ACTIVE))
1597 twist |= 2 ;
1598 return twist;
1599}
1600
1601/*
1602 * return status (called by SMT)
1603 * type
1604 * state
1605 * remote phy type
1606 * remote mac yes/no
1607 */
1608void pcm_status_state(struct s_smc *smc, int np, int *type, int *state,
1609 int *remote, int *mac)
1610{
1611 struct s_phy *phy = &smc->y[np] ;
1612 struct fddi_mib_p *mib ;
1613
1614 mib = phy->mib ;
1615
1616 /* remote PHY type and MAC - set only if active */
1617 *mac = 0 ;
1618 *type = mib->fddiPORTMy_Type ; /* our PHY type */
1619 *state = mib->fddiPORTConnectState ;
1620 *remote = mib->fddiPORTNeighborType ;
1621
1622 switch(mib->fddiPORTPCMState) {
1623 case PC8_ACTIVE :
1624 *mac = mib->fddiPORTMacIndicated.R_val ;
1625 break ;
1626 }
1627}
1628
1629/*
1630 * return rooted station status (called by SMT)
1631 */
1632int pcm_rooted_station(struct s_smc *smc)
1633{
1634 int n ;
1635
1636 for (n = 0 ; n < NUMPHYS ; n++) {
1637 if (smc->y[n].mib->fddiPORTPCMState == PC8_ACTIVE &&
1638 smc->y[n].mib->fddiPORTNeighborType == TM)
1639 return 0;
1640 }
1641 return 1;
1642}
1643
1644/*
1645 * Interrupt actions for PLC & PCM events
1646 */
1647void plc_irq(struct s_smc *smc, int np, unsigned int cmd)
1648/* int np; PHY index */
1649{
1650 struct s_phy *phy = &smc->y[np] ;
1651 struct s_plc *plc = &phy->plc ;
1652 int n ;
1653#ifdef SUPERNET_3
1654 int corr_mask ;
1655#endif /* SUPERNET_3 */
1656 int i ;
1657
1658 if (np >= smc->s.numphys) {
1659 plc->soft_err++ ;
1660 return ;
1661 }
1662 if (cmd & PL_EBUF_ERR) { /* elastic buff. det. over-|underflow*/
1663 /*
1664 * Check whether the SRF Condition occurred.
1665 */
1666 if (!plc->ebuf_cont && phy->mib->fddiPORTPCMState == PC8_ACTIVE){
1667 /*
1668 * This is the real Elasticity Error.
1669 * More than one in a row are treated as a
1670 * single one.
1671 * Only count this in the active state.
1672 */
1673 phy->mib->fddiPORTEBError_Ct ++ ;
1674
1675 }
1676
1677 plc->ebuf_err++ ;
1678 if (plc->ebuf_cont <= 1000) {
1679 /*
1680 * Prevent counter from being wrapped after
1681 * hanging years in that interrupt.
1682 */
1683 plc->ebuf_cont++ ; /* Ebuf continuous error */
1684 }
1685
1686#ifdef SUPERNET_3
1687 if (plc->ebuf_cont == 1000 &&
1688 ((inpw(PLC(np,PL_STATUS_A)) & PLC_REV_MASK) ==
1689 PLC_REV_SN3)) {
1690 /*
1691 * This interrupt remeained high for at least
1692 * 1000 consecutive interrupt calls.
1693 *
1694 * This is caused by a hardware error of the
1695 * ORION part of the Supernet III chipset.
1696 *
1697 * Disable this bit from the mask.
1698 */
1699 corr_mask = (plc_imsk_na & ~PL_EBUF_ERR) ;
1700 outpw(PLC(np,PL_INTR_MASK),corr_mask);
1701
1702 /*
1703 * Disconnect from the ring.
1704 * Call the driver with the reset indication.
1705 */
1706 queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
1707
1708 /*
1709 * Make an error log entry.
1710 */
1711 SMT_ERR_LOG(smc,SMT_E0136, SMT_E0136_MSG) ;
1712
1713 /*
1714 * Indicate the Reset.
1715 */
1716 drv_reset_indication(smc) ;
1717 }
1718#endif /* SUPERNET_3 */
1719 } else {
1720 /* Reset the continuous error variable */
1721 plc->ebuf_cont = 0 ; /* reset Ebuf continuous error */
1722 }
1723 if (cmd & PL_PHYINV) { /* physical layer invalid signal */
1724 plc->phyinv++ ;
1725 }
1726 if (cmd & PL_VSYM_CTR) { /* violation symbol counter has incr.*/
1727 plc->vsym_ctr++ ;
1728 }
1729 if (cmd & PL_MINI_CTR) { /* dep. on PLC_CNTRL_A's MINI_CTR_INT*/
1730 plc->mini_ctr++ ;
1731 }
1732 if (cmd & PL_LE_CTR) { /* link error event counter */
1733 int j ;
1734
1735 /*
1736 * note: PL_LINK_ERR_CTR MUST be read to clear it
1737 */
1738 j = inpw(PLC(np,PL_LE_THRESHOLD)) ;
1739 i = inpw(PLC(np,PL_LINK_ERR_CTR)) ;
1740
1741 if (i < j) {
1742 /* wrapped around */
1743 i += 256 ;
1744 }
1745
1746 if (phy->lem.lem_on) {
1747 /* Note: Lem errors shall only be counted when
1748 * link is ACTIVE or LCT is active.
1749 */
1750 phy->lem.lem_errors += i ;
1751 phy->mib->fddiPORTLem_Ct += i ;
1752 }
1753 }
1754 if (cmd & PL_TPC_EXPIRED) { /* TPC timer reached zero */
1755 if (plc->p_state == PS_LCT) {
1756 /*
1757 * end of LCT
1758 */
1759 ;
1760 }
1761 plc->tpc_exp++ ;
1762 }
1763 if (cmd & PL_LS_MATCH) { /* LS == LS in PLC_CNTRL_B's MATCH_LS*/
1764 switch (inpw(PLC(np,PL_CNTRL_B)) & PL_MATCH_LS) {
1765 case PL_I_IDLE : phy->curr_ls = PC_ILS ; break ;
1766 case PL_I_HALT : phy->curr_ls = PC_HLS ; break ;
1767 case PL_I_MASTR : phy->curr_ls = PC_MLS ; break ;
1768 case PL_I_QUIET : phy->curr_ls = PC_QLS ; break ;
1769 }
1770 }
1771 if (cmd & PL_PCM_BREAK) { /* PCM has entered the BREAK state */
1772 int reason;
1773
1774 reason = inpw(PLC(np,PL_STATUS_B)) & PL_BREAK_REASON ;
1775
1776 switch (reason) {
1777 case PL_B_PCS : plc->b_pcs++ ; break ;
1778 case PL_B_TPC : plc->b_tpc++ ; break ;
1779 case PL_B_TNE : plc->b_tne++ ; break ;
1780 case PL_B_QLS : plc->b_qls++ ; break ;
1781 case PL_B_ILS : plc->b_ils++ ; break ;
1782 case PL_B_HLS : plc->b_hls++ ; break ;
1783 }
1784
1785 /*jd 05-Aug-1999 changed: Bug #10419 */
1786 DB_PCMN(1,"PLC %d: MDcF = %x\n", np, smc->e.DisconnectFlag);
1787 if (smc->e.DisconnectFlag == FALSE) {
1788 DB_PCMN(1,"PLC %d: restart (reason %x)\n", np, reason);
1789 queue_event(smc,EVENT_PCM+np,PC_START) ;
1790 }
1791 else {
1792 DB_PCMN(1,"PLC %d: NO!! restart (reason %x)\n", np, reason);
1793 }
1794 return ;
1795 }
1796 /*
1797 * If both CODE & ENABLE are set ignore enable
1798 */
1799 if (cmd & PL_PCM_CODE) { /* receive last sign.-bit | LCT complete */
1800 queue_event(smc,EVENT_PCM+np,PC_SIGNAL) ;
1801 n = inpw(PLC(np,PL_RCV_VECTOR)) ;
1802 for (i = 0 ; i < plc->p_bits ; i++) {
1803 phy->r_val[plc->p_start+i] = n & 1 ;
1804 n >>= 1 ;
1805 }
1806 }
1807 else if (cmd & PL_PCM_ENABLED) { /* asserted SC_JOIN, scrub.completed*/
1808 queue_event(smc,EVENT_PCM+np,PC_JOIN) ;
1809 }
1810 if (cmd & PL_TRACE_PROP) { /* MLS while PC8_ACTIV || PC2_TRACE */
1811 /*PC22b*/
1812 if (!phy->tr_flag) {
1813 DB_PCMN(1,"PCM : irq TRACE_PROP %d %d\n",
1814 np,smc->mib.fddiSMTECMState) ;
1815 phy->tr_flag = TRUE ;
1816 smc->e.trace_prop |= ENTITY_BIT(ENTITY_PHY(np)) ;
1817 queue_event(smc,EVENT_ECM,EC_TRACE_PROP) ;
1818 }
1819 }
1820 /*
1821 * filter PLC glitch ???
1822 * QLS || HLS only while in PC2_TRACE state
1823 */
1824 if ((cmd & PL_SELF_TEST) && (phy->mib->fddiPORTPCMState == PC2_TRACE)) {
1825 /*PC22a*/
1826 if (smc->e.path_test == PT_PASSED) {
1827 DB_PCMN(1,"PCM : state = %s %d\n", get_pcmstate(smc,np),
1828 phy->mib->fddiPORTPCMState) ;
1829
1830 smc->e.path_test = PT_PENDING ;
1831 queue_event(smc,EVENT_ECM,EC_PATH_TEST) ;
1832 }
1833 }
1834 if (cmd & PL_TNE_EXPIRED) { /* TNE: length of noise events */
1835 /* break_required (TNE > NS_Max) */
1836 if (phy->mib->fddiPORTPCMState == PC8_ACTIVE) {
1837 if (!phy->tr_flag) {
1838 DB_PCMN(1,"PCM %c : PC81 %s\n",phy->phy_name,"NSE");
1839 queue_event(smc,EVENT_PCM+np,PC_START) ;
1840 return ;
1841 }
1842 }
1843 }
1844#if 0
1845 if (cmd & PL_NP_ERR) { /* NP has requested to r/w an inv reg*/
1846 /*
1847 * It's a bug by AMD
1848 */
1849 plc->np_err++ ;
1850 }
1851 /* pin inactiv (GND) */
1852 if (cmd & PL_PARITY_ERR) { /* p. error dedected on TX9-0 inp */
1853 plc->parity_err++ ;
1854 }
1855 if (cmd & PL_LSDO) { /* carrier detected */
1856 ;
1857 }
1858#endif
1859}
1860
1861#ifdef DEBUG
1862/*
1863 * fill state struct
1864 */
1865void pcm_get_state(struct s_smc *smc, struct smt_state *state)
1866{
1867 struct s_phy *phy ;
1868 struct pcm_state *pcs ;
1869 int i ;
1870 int ii ;
1871 short rbits ;
1872 short tbits ;
1873 struct fddi_mib_p *mib ;
1874
1875 for (i = 0, phy = smc->y, pcs = state->pcm_state ; i < NUMPHYS ;
1876 i++ , phy++, pcs++ ) {
1877 mib = phy->mib ;
1878 pcs->pcm_type = (u_char) mib->fddiPORTMy_Type ;
1879 pcs->pcm_state = (u_char) mib->fddiPORTPCMState ;
1880 pcs->pcm_mode = phy->pc_mode ;
1881 pcs->pcm_neighbor = (u_char) mib->fddiPORTNeighborType ;
1882 pcs->pcm_bsf = mib->fddiPORTBS_Flag ;
1883 pcs->pcm_lsf = phy->ls_flag ;
1884 pcs->pcm_lct_fail = (u_char) mib->fddiPORTLCTFail_Ct ;
1885 pcs->pcm_ls_rx = LS2MIB(sm_pm_get_ls(smc,i)) ;
1886 for (ii = 0, rbits = tbits = 0 ; ii < NUMBITS ; ii++) {
1887 rbits <<= 1 ;
1888 tbits <<= 1 ;
1889 if (phy->r_val[NUMBITS-1-ii])
1890 rbits |= 1 ;
1891 if (phy->t_val[NUMBITS-1-ii])
1892 tbits |= 1 ;
1893 }
1894 pcs->pcm_r_val = rbits ;
1895 pcs->pcm_t_val = tbits ;
1896 }
1897}
1898
1899int get_pcm_state(struct s_smc *smc, int np)
1900{
1901 int pcs ;
1902
1903 SK_UNUSED(smc) ;
1904
1905 switch (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_STATE) {
1906 case PL_PC0 : pcs = PC_STOP ; break ;
1907 case PL_PC1 : pcs = PC_START ; break ;
1908 case PL_PC2 : pcs = PC_TRACE ; break ;
1909 case PL_PC3 : pcs = PC_SIGNAL ; break ;
1910 case PL_PC4 : pcs = PC_SIGNAL ; break ;
1911 case PL_PC5 : pcs = PC_SIGNAL ; break ;
1912 case PL_PC6 : pcs = PC_JOIN ; break ;
1913 case PL_PC7 : pcs = PC_JOIN ; break ;
1914 case PL_PC8 : pcs = PC_ENABLE ; break ;
1915 case PL_PC9 : pcs = PC_MAINT ; break ;
1916 default : pcs = PC_DISABLE ; break ;
1917 }
1918 return pcs;
1919}
1920
1921char *get_linestate(struct s_smc *smc, int np)
1922{
1923 char *ls = "" ;
1924
1925 SK_UNUSED(smc) ;
1926
1927 switch (inpw(PLC(np,PL_STATUS_A)) & PL_LINE_ST) {
1928 case PL_L_NLS : ls = "NOISE" ; break ;
1929 case PL_L_ALS : ls = "ACTIV" ; break ;
1930 case PL_L_UND : ls = "UNDEF" ; break ;
1931 case PL_L_ILS4: ls = "ILS 4" ; break ;
1932 case PL_L_QLS : ls = "QLS" ; break ;
1933 case PL_L_MLS : ls = "MLS" ; break ;
1934 case PL_L_HLS : ls = "HLS" ; break ;
1935 case PL_L_ILS16:ls = "ILS16" ; break ;
1936#ifdef lint
1937 default: ls = "unknown" ; break ;
1938#endif
1939 }
1940 return ls;
1941}
1942
1943char *get_pcmstate(struct s_smc *smc, int np)
1944{
1945 char *pcs ;
1946
1947 SK_UNUSED(smc) ;
1948
1949 switch (inpw(PLC(np,PL_STATUS_B)) & PL_PCM_STATE) {
1950 case PL_PC0 : pcs = "OFF" ; break ;
1951 case PL_PC1 : pcs = "BREAK" ; break ;
1952 case PL_PC2 : pcs = "TRACE" ; break ;
1953 case PL_PC3 : pcs = "CONNECT"; break ;
1954 case PL_PC4 : pcs = "NEXT" ; break ;
1955 case PL_PC5 : pcs = "SIGNAL" ; break ;
1956 case PL_PC6 : pcs = "JOIN" ; break ;
1957 case PL_PC7 : pcs = "VERIFY" ; break ;
1958 case PL_PC8 : pcs = "ACTIV" ; break ;
1959 case PL_PC9 : pcs = "MAINT" ; break ;
1960 default : pcs = "UNKNOWN" ; break ;
1961 }
1962 return pcs;
1963}
1964
1965void list_phy(struct s_smc *smc)
1966{
1967 struct s_plc *plc ;
1968 int np ;
1969
1970 for (np = 0 ; np < NUMPHYS ; np++) {
1971 plc = &smc->y[np].plc ;
1972 printf("PHY %d:\tERRORS\t\t\tBREAK_REASONS\t\tSTATES:\n",np) ;
1973 printf("\tsoft_error: %ld \t\tPC_Start : %ld\n",
1974 plc->soft_err,plc->b_pcs);
1975 printf("\tparity_err: %ld \t\tTPC exp. : %ld\t\tLine: %s\n",
1976 plc->parity_err,plc->b_tpc,get_linestate(smc,np)) ;
1977 printf("\tebuf_error: %ld \t\tTNE exp. : %ld\n",
1978 plc->ebuf_err,plc->b_tne) ;
1979 printf("\tphyinvalid: %ld \t\tQLS det. : %ld\t\tPCM : %s\n",
1980 plc->phyinv,plc->b_qls,get_pcmstate(smc,np)) ;
1981 printf("\tviosym_ctr: %ld \t\tILS det. : %ld\n",
1982 plc->vsym_ctr,plc->b_ils) ;
1983 printf("\tmingap_ctr: %ld \t\tHLS det. : %ld\n",
1984 plc->mini_ctr,plc->b_hls) ;
1985 printf("\tnodepr_err: %ld\n",plc->np_err) ;
1986 printf("\tTPC_exp : %ld\n",plc->tpc_exp) ;
1987 printf("\tLEM_err : %ld\n",smc->y[np].lem.lem_errors) ;
1988 }
1989}
1990
1991
1992#ifdef CONCENTRATOR
1993void pcm_lem_dump(struct s_smc *smc)
1994{
1995 int i ;
1996 struct s_phy *phy ;
1997 struct fddi_mib_p *mib ;
1998
1999 char *entostring() ;
2000
2001 printf("PHY errors BER\n") ;
2002 printf("----------------------\n") ;
2003 for (i = 0,phy = smc->y ; i < NUMPHYS ; i++,phy++) {
2004 if (!plc_is_installed(smc,i))
2005 continue ;
2006 mib = phy->mib ;
2007 printf("%s\t%ld\t10E-%d\n",
2008 entostring(smc,ENTITY_PHY(i)),
2009 mib->fddiPORTLem_Ct,
2010 mib->fddiPORTLer_Estimate) ;
2011 }
2012}
2013#endif
2014#endif
diff --git a/drivers/net/skfp/pmf.c b/drivers/net/skfp/pmf.c
deleted file mode 100644
index 9ac4665d7411..000000000000
--- a/drivers/net/skfp/pmf.c
+++ /dev/null
@@ -1,1663 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 Parameter Management Frame processing for SMT 7.2
19*/
20
21#include "h/types.h"
22#include "h/fddi.h"
23#include "h/smc.h"
24#include "h/smt_p.h"
25
26#define KERNEL
27#include "h/smtstate.h"
28
29#ifndef SLIM_SMT
30
31#ifndef lint
32static const char ID_sccs[] = "@(#)pmf.c 1.37 97/08/04 (C) SK " ;
33#endif
34
35static int smt_authorize(struct s_smc *smc, struct smt_header *sm);
36static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm);
37static const struct s_p_tab* smt_get_ptab(u_short para);
38static int smt_mib_phys(struct s_smc *smc);
39static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
40 int local, int set);
41void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
42 int index, int local);
43static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req,
44 int set, int local);
45static int port_to_mib(struct s_smc *smc, int p);
46
47#define MOFFSS(e) offsetof(struct fddi_mib, e)
48#define MOFFMS(e) offsetof(struct fddi_mib_m, e)
49#define MOFFAS(e) offsetof(struct fddi_mib_a, e)
50#define MOFFPS(e) offsetof(struct fddi_mib_p, e)
51
52
53#define AC_G 0x01 /* Get */
54#define AC_GR 0x02 /* Get/Set */
55#define AC_S 0x04 /* Set */
56#define AC_NA 0x08
57#define AC_GROUP 0x10 /* Group */
58#define MS2BCLK(x) ((x)*12500L)
59/*
60 F LFag (byte)
61 B byte
62 S u_short 16 bit
63 C Counter 32 bit
64 L Long 32 bit
65 T Timer_2 32 bit
66 P TimeStamp ;
67 A LongAddress (6 byte)
68 E Enum 16 bit
69 R ResId 16 Bit
70*/
71static const struct s_p_tab {
72 u_short p_num ; /* parameter code */
73 u_char p_access ; /* access rights */
74 u_short p_offset ; /* offset in mib */
75 char p_swap[3] ; /* format string */
76} p_tab[] = {
77 /* StationIdGrp */
78 { SMT_P100A,AC_GROUP } ,
79 { SMT_P100B,AC_G, MOFFSS(fddiSMTStationId), "8" } ,
80 { SMT_P100D,AC_G, MOFFSS(fddiSMTOpVersionId), "S" } ,
81 { SMT_P100E,AC_G, MOFFSS(fddiSMTHiVersionId), "S" } ,
82 { SMT_P100F,AC_G, MOFFSS(fddiSMTLoVersionId), "S" } ,
83 { SMT_P1010,AC_G, MOFFSS(fddiSMTManufacturerData), "D" } ,
84 { SMT_P1011,AC_GR, MOFFSS(fddiSMTUserData), "D" } ,
85 { SMT_P1012,AC_G, MOFFSS(fddiSMTMIBVersionId), "S" } ,
86
87 /* StationConfigGrp */
88 { SMT_P1014,AC_GROUP } ,
89 { SMT_P1015,AC_G, MOFFSS(fddiSMTMac_Ct), "B" } ,
90 { SMT_P1016,AC_G, MOFFSS(fddiSMTNonMaster_Ct), "B" } ,
91 { SMT_P1017,AC_G, MOFFSS(fddiSMTMaster_Ct), "B" } ,
92 { SMT_P1018,AC_G, MOFFSS(fddiSMTAvailablePaths), "B" } ,
93 { SMT_P1019,AC_G, MOFFSS(fddiSMTConfigCapabilities),"S" } ,
94 { SMT_P101A,AC_GR, MOFFSS(fddiSMTConfigPolicy), "wS" } ,
95 { SMT_P101B,AC_GR, MOFFSS(fddiSMTConnectionPolicy),"wS" } ,
96 { SMT_P101D,AC_GR, MOFFSS(fddiSMTTT_Notify), "wS" } ,
97 { SMT_P101E,AC_GR, MOFFSS(fddiSMTStatRptPolicy), "bB" } ,
98 { SMT_P101F,AC_GR, MOFFSS(fddiSMTTrace_MaxExpiration),"lL" } ,
99 { SMT_P1020,AC_G, MOFFSS(fddiSMTPORTIndexes), "II" } ,
100 { SMT_P1021,AC_G, MOFFSS(fddiSMTMACIndexes), "I" } ,
101 { SMT_P1022,AC_G, MOFFSS(fddiSMTBypassPresent), "F" } ,
102
103 /* StatusGrp */
104 { SMT_P1028,AC_GROUP } ,
105 { SMT_P1029,AC_G, MOFFSS(fddiSMTECMState), "E" } ,
106 { SMT_P102A,AC_G, MOFFSS(fddiSMTCF_State), "E" } ,
107 { SMT_P102C,AC_G, MOFFSS(fddiSMTRemoteDisconnectFlag),"F" } ,
108 { SMT_P102D,AC_G, MOFFSS(fddiSMTStationStatus), "E" } ,
109 { SMT_P102E,AC_G, MOFFSS(fddiSMTPeerWrapFlag), "F" } ,
110
111 /* MIBOperationGrp */
112 { SMT_P1032,AC_GROUP } ,
113 { SMT_P1033,AC_G, MOFFSS(fddiSMTTimeStamp),"P" } ,
114 { SMT_P1034,AC_G, MOFFSS(fddiSMTTransitionTimeStamp),"P" } ,
115 /* NOTE : SMT_P1035 is already swapped ! SMT_P_SETCOUNT */
116 { SMT_P1035,AC_G, MOFFSS(fddiSMTSetCount),"4P" } ,
117 { SMT_P1036,AC_G, MOFFSS(fddiSMTLastSetStationId),"8" } ,
118
119 { SMT_P103C,AC_S, 0, "wS" } ,
120
121 /*
122 * PRIVATE EXTENSIONS
123 * only accessible locally to get/set passwd
124 */
125 { SMT_P10F0,AC_GR, MOFFSS(fddiPRPMFPasswd), "8" } ,
126 { SMT_P10F1,AC_GR, MOFFSS(fddiPRPMFStation), "8" } ,
127#ifdef ESS
128 { SMT_P10F2,AC_GR, MOFFSS(fddiESSPayload), "lL" } ,
129 { SMT_P10F3,AC_GR, MOFFSS(fddiESSOverhead), "lL" } ,
130 { SMT_P10F4,AC_GR, MOFFSS(fddiESSMaxTNeg), "lL" } ,
131 { SMT_P10F5,AC_GR, MOFFSS(fddiESSMinSegmentSize), "lL" } ,
132 { SMT_P10F6,AC_GR, MOFFSS(fddiESSCategory), "lL" } ,
133 { SMT_P10F7,AC_GR, MOFFSS(fddiESSSynchTxMode), "wS" } ,
134#endif
135#ifdef SBA
136 { SMT_P10F8,AC_GR, MOFFSS(fddiSBACommand), "bF" } ,
137 { SMT_P10F9,AC_GR, MOFFSS(fddiSBAAvailable), "bF" } ,
138#endif
139 /* MAC Attributes */
140 { SMT_P200A,AC_GROUP } ,
141 { SMT_P200B,AC_G, MOFFMS(fddiMACFrameStatusFunctions),"S" } ,
142 { SMT_P200D,AC_G, MOFFMS(fddiMACT_MaxCapabilitiy),"T" } ,
143 { SMT_P200E,AC_G, MOFFMS(fddiMACTVXCapabilitiy),"T" } ,
144
145 /* ConfigGrp */
146 { SMT_P2014,AC_GROUP } ,
147 { SMT_P2016,AC_G, MOFFMS(fddiMACAvailablePaths), "B" } ,
148 { SMT_P2017,AC_G, MOFFMS(fddiMACCurrentPath), "S" } ,
149 { SMT_P2018,AC_G, MOFFMS(fddiMACUpstreamNbr), "A" } ,
150 { SMT_P2019,AC_G, MOFFMS(fddiMACDownstreamNbr), "A" } ,
151 { SMT_P201A,AC_G, MOFFMS(fddiMACOldUpstreamNbr), "A" } ,
152 { SMT_P201B,AC_G, MOFFMS(fddiMACOldDownstreamNbr),"A" } ,
153 { SMT_P201D,AC_G, MOFFMS(fddiMACDupAddressTest), "E" } ,
154 { SMT_P2020,AC_GR, MOFFMS(fddiMACRequestedPaths), "wS" } ,
155 { SMT_P2021,AC_G, MOFFMS(fddiMACDownstreamPORTType),"E" } ,
156 { SMT_P2022,AC_G, MOFFMS(fddiMACIndex), "S" } ,
157
158 /* AddressGrp */
159 { SMT_P2028,AC_GROUP } ,
160 { SMT_P2029,AC_G, MOFFMS(fddiMACSMTAddress), "A" } ,
161
162 /* OperationGrp */
163 { SMT_P2032,AC_GROUP } ,
164 { SMT_P2033,AC_G, MOFFMS(fddiMACT_Req), "T" } ,
165 { SMT_P2034,AC_G, MOFFMS(fddiMACT_Neg), "T" } ,
166 { SMT_P2035,AC_G, MOFFMS(fddiMACT_Max), "T" } ,
167 { SMT_P2036,AC_G, MOFFMS(fddiMACTvxValue), "T" } ,
168 { SMT_P2038,AC_G, MOFFMS(fddiMACT_Pri0), "T" } ,
169 { SMT_P2039,AC_G, MOFFMS(fddiMACT_Pri1), "T" } ,
170 { SMT_P203A,AC_G, MOFFMS(fddiMACT_Pri2), "T" } ,
171 { SMT_P203B,AC_G, MOFFMS(fddiMACT_Pri3), "T" } ,
172 { SMT_P203C,AC_G, MOFFMS(fddiMACT_Pri4), "T" } ,
173 { SMT_P203D,AC_G, MOFFMS(fddiMACT_Pri5), "T" } ,
174 { SMT_P203E,AC_G, MOFFMS(fddiMACT_Pri6), "T" } ,
175
176
177 /* CountersGrp */
178 { SMT_P2046,AC_GROUP } ,
179 { SMT_P2047,AC_G, MOFFMS(fddiMACFrame_Ct), "C" } ,
180 { SMT_P2048,AC_G, MOFFMS(fddiMACCopied_Ct), "C" } ,
181 { SMT_P2049,AC_G, MOFFMS(fddiMACTransmit_Ct), "C" } ,
182 { SMT_P204A,AC_G, MOFFMS(fddiMACToken_Ct), "C" } ,
183 { SMT_P2051,AC_G, MOFFMS(fddiMACError_Ct), "C" } ,
184 { SMT_P2052,AC_G, MOFFMS(fddiMACLost_Ct), "C" } ,
185 { SMT_P2053,AC_G, MOFFMS(fddiMACTvxExpired_Ct), "C" } ,
186 { SMT_P2054,AC_G, MOFFMS(fddiMACNotCopied_Ct), "C" } ,
187 { SMT_P2056,AC_G, MOFFMS(fddiMACRingOp_Ct), "C" } ,
188
189 /* FrameErrorConditionGrp */
190 { SMT_P205A,AC_GROUP } ,
191 { SMT_P205F,AC_GR, MOFFMS(fddiMACFrameErrorThreshold),"wS" } ,
192 { SMT_P2060,AC_G, MOFFMS(fddiMACFrameErrorRatio), "S" } ,
193
194 /* NotCopiedConditionGrp */
195 { SMT_P2064,AC_GROUP } ,
196 { SMT_P2067,AC_GR, MOFFMS(fddiMACNotCopiedThreshold),"wS" } ,
197 { SMT_P2069,AC_G, MOFFMS(fddiMACNotCopiedRatio), "S" } ,
198
199 /* StatusGrp */
200 { SMT_P206E,AC_GROUP } ,
201 { SMT_P206F,AC_G, MOFFMS(fddiMACRMTState), "S" } ,
202 { SMT_P2070,AC_G, MOFFMS(fddiMACDA_Flag), "F" } ,
203 { SMT_P2071,AC_G, MOFFMS(fddiMACUNDA_Flag), "F" } ,
204 { SMT_P2072,AC_G, MOFFMS(fddiMACFrameErrorFlag), "F" } ,
205 { SMT_P2073,AC_G, MOFFMS(fddiMACNotCopiedFlag), "F" } ,
206 { SMT_P2074,AC_G, MOFFMS(fddiMACMA_UnitdataAvailable),"F" } ,
207 { SMT_P2075,AC_G, MOFFMS(fddiMACHardwarePresent), "F" } ,
208 { SMT_P2076,AC_GR, MOFFMS(fddiMACMA_UnitdataEnable),"bF" } ,
209
210 /*
211 * PRIVATE EXTENSIONS
212 * only accessible locally to get/set TMIN
213 */
214 { SMT_P20F0,AC_NA } ,
215 { SMT_P20F1,AC_GR, MOFFMS(fddiMACT_Min), "lT" } ,
216
217 /* Path Attributes */
218 /*
219 * DON't swap 320B,320F,3210: they are already swapped in swap_para()
220 */
221 { SMT_P320A,AC_GROUP } ,
222 { SMT_P320B,AC_G, MOFFAS(fddiPATHIndex), "r" } ,
223 { SMT_P320F,AC_GR, MOFFAS(fddiPATHSbaPayload), "l4" } ,
224 { SMT_P3210,AC_GR, MOFFAS(fddiPATHSbaOverhead), "l4" } ,
225 /* fddiPATHConfiguration */
226 { SMT_P3212,AC_G, 0, "" } ,
227 { SMT_P3213,AC_GR, MOFFAS(fddiPATHT_Rmode), "lT" } ,
228 { SMT_P3214,AC_GR, MOFFAS(fddiPATHSbaAvailable), "lL" } ,
229 { SMT_P3215,AC_GR, MOFFAS(fddiPATHTVXLowerBound), "lT" } ,
230 { SMT_P3216,AC_GR, MOFFAS(fddiPATHT_MaxLowerBound),"lT" } ,
231 { SMT_P3217,AC_GR, MOFFAS(fddiPATHMaxT_Req), "lT" } ,
232
233 /* Port Attributes */
234 /* ConfigGrp */
235 { SMT_P400A,AC_GROUP } ,
236 { SMT_P400C,AC_G, MOFFPS(fddiPORTMy_Type), "E" } ,
237 { SMT_P400D,AC_G, MOFFPS(fddiPORTNeighborType), "E" } ,
238 { SMT_P400E,AC_GR, MOFFPS(fddiPORTConnectionPolicies),"bB" } ,
239 { SMT_P400F,AC_G, MOFFPS(fddiPORTMacIndicated), "2" } ,
240 { SMT_P4010,AC_G, MOFFPS(fddiPORTCurrentPath), "E" } ,
241 { SMT_P4011,AC_GR, MOFFPS(fddiPORTRequestedPaths), "l4" } ,
242 { SMT_P4012,AC_G, MOFFPS(fddiPORTMACPlacement), "S" } ,
243 { SMT_P4013,AC_G, MOFFPS(fddiPORTAvailablePaths), "B" } ,
244 { SMT_P4016,AC_G, MOFFPS(fddiPORTPMDClass), "E" } ,
245 { SMT_P4017,AC_G, MOFFPS(fddiPORTConnectionCapabilities), "B"} ,
246 { SMT_P401D,AC_G, MOFFPS(fddiPORTIndex), "R" } ,
247
248 /* OperationGrp */
249 { SMT_P401E,AC_GROUP } ,
250 { SMT_P401F,AC_GR, MOFFPS(fddiPORTMaint_LS), "wE" } ,
251 { SMT_P4021,AC_G, MOFFPS(fddiPORTBS_Flag), "F" } ,
252 { SMT_P4022,AC_G, MOFFPS(fddiPORTPC_LS), "E" } ,
253
254 /* ErrorCtrsGrp */
255 { SMT_P4028,AC_GROUP } ,
256 { SMT_P4029,AC_G, MOFFPS(fddiPORTEBError_Ct), "C" } ,
257 { SMT_P402A,AC_G, MOFFPS(fddiPORTLCTFail_Ct), "C" } ,
258
259 /* LerGrp */
260 { SMT_P4032,AC_GROUP } ,
261 { SMT_P4033,AC_G, MOFFPS(fddiPORTLer_Estimate), "F" } ,
262 { SMT_P4034,AC_G, MOFFPS(fddiPORTLem_Reject_Ct), "C" } ,
263 { SMT_P4035,AC_G, MOFFPS(fddiPORTLem_Ct), "C" } ,
264 { SMT_P403A,AC_GR, MOFFPS(fddiPORTLer_Cutoff), "bB" } ,
265 { SMT_P403B,AC_GR, MOFFPS(fddiPORTLer_Alarm), "bB" } ,
266
267 /* StatusGrp */
268 { SMT_P403C,AC_GROUP } ,
269 { SMT_P403D,AC_G, MOFFPS(fddiPORTConnectState), "E" } ,
270 { SMT_P403E,AC_G, MOFFPS(fddiPORTPCMStateX), "E" } ,
271 { SMT_P403F,AC_G, MOFFPS(fddiPORTPC_Withhold), "E" } ,
272 { SMT_P4040,AC_G, MOFFPS(fddiPORTLerFlag), "F" } ,
273 { SMT_P4041,AC_G, MOFFPS(fddiPORTHardwarePresent),"F" } ,
274
275 { SMT_P4046,AC_S, 0, "wS" } ,
276
277 { 0, AC_GROUP } ,
278 { 0 }
279} ;
280
281void smt_pmf_received_pack(struct s_smc *smc, SMbuf *mb, int local)
282{
283 struct smt_header *sm ;
284 SMbuf *reply ;
285
286 sm = smtod(mb,struct smt_header *) ;
287 DB_SMT("SMT: processing PMF frame at %x len %d\n",sm,mb->sm_len) ;
288#ifdef DEBUG
289 dump_smt(smc,sm,"PMF Received") ;
290#endif
291 /*
292 * Start the watchdog: It may be a long, long packet and
293 * maybe the watchdog occurs ...
294 */
295 smt_start_watchdog(smc) ;
296
297 if (sm->smt_class == SMT_PMF_GET ||
298 sm->smt_class == SMT_PMF_SET) {
299 reply = smt_build_pmf_response(smc,sm,
300 sm->smt_class == SMT_PMF_SET,local) ;
301 if (reply) {
302 sm = smtod(reply,struct smt_header *) ;
303#ifdef DEBUG
304 dump_smt(smc,sm,"PMF Reply") ;
305#endif
306 smt_send_frame(smc,reply,FC_SMT_INFO,local) ;
307 }
308 }
309}
310
311static SMbuf *smt_build_pmf_response(struct s_smc *smc, struct smt_header *req,
312 int set, int local)
313{
314 SMbuf *mb ;
315 struct smt_header *smt ;
316 struct smt_para *pa ;
317 struct smt_p_reason *res ;
318 const struct s_p_tab *pt ;
319 int len ;
320 int index ;
321 int idx_end ;
322 int error ;
323 int range ;
324 SK_LOC_DECL(struct s_pcon,pcon) ;
325 SK_LOC_DECL(struct s_pcon,set_pcon) ;
326
327 /*
328 * build SMT header
329 */
330 if (!(mb = smt_get_mbuf(smc)))
331 return mb;
332
333 smt = smtod(mb, struct smt_header *) ;
334 smt->smt_dest = req->smt_source ; /* DA == source of request */
335 smt->smt_class = req->smt_class ; /* same class (GET/SET) */
336 smt->smt_type = SMT_REPLY ;
337 smt->smt_version = SMT_VID_2 ;
338 smt->smt_tid = req->smt_tid ; /* same TID */
339 smt->smt_pad = 0 ;
340 smt->smt_len = 0 ;
341
342 /*
343 * setup parameter status
344 */
345 pcon.pc_len = SMT_MAX_INFO_LEN ; /* max para length */
346 pcon.pc_err = 0 ; /* no error */
347 pcon.pc_badset = 0 ; /* no bad set count */
348 pcon.pc_p = (void *) (smt + 1) ; /* paras start here */
349
350 /*
351 * check authoriziation and set count
352 */
353 error = 0 ;
354 if (set) {
355 if (!local && smt_authorize(smc,req))
356 error = SMT_RDF_AUTHOR ;
357 else if (smt_check_set_count(smc,req))
358 pcon.pc_badset = SMT_RDF_BADSET ;
359 }
360 /*
361 * add reason code and all mandatory parameters
362 */
363 res = (struct smt_p_reason *) pcon.pc_p ;
364 smt_add_para(smc,&pcon,(u_short) SMT_P_REASON,0,0) ;
365 smt_add_para(smc,&pcon,(u_short) SMT_P1033,0,0) ;
366 /* update 1035 and 1036 later if set */
367 set_pcon = pcon ;
368 smt_add_para(smc,&pcon,(u_short) SMT_P1035,0,0) ;
369 smt_add_para(smc,&pcon,(u_short) SMT_P1036,0,0) ;
370
371 pcon.pc_err = error ;
372 len = req->smt_len ;
373 pa = (struct smt_para *) (req + 1) ;
374 /*
375 * process list of paras
376 */
377 while (!pcon.pc_err && len > 0 ) {
378 if (((u_short)len < pa->p_len + PARA_LEN) || (pa->p_len & 3)) {
379 pcon.pc_err = SMT_RDF_LENGTH ;
380 break ;
381 }
382
383 if (((range = (pa->p_type & 0xf000)) == 0x2000) ||
384 range == 0x3000 || range == 0x4000) {
385 /*
386 * get index for PART,MAC ad PATH group
387 */
388 index = *((u_char *)pa + PARA_LEN + 3) ;/* index */
389 idx_end = index ;
390 if (!set && (pa->p_len != 4)) {
391 pcon.pc_err = SMT_RDF_LENGTH ;
392 break ;
393 }
394 if (!index && !set) {
395 switch (range) {
396 case 0x2000 :
397 index = INDEX_MAC ;
398 idx_end = index - 1 + NUMMACS ;
399 break ;
400 case 0x3000 :
401 index = INDEX_PATH ;
402 idx_end = index - 1 + NUMPATHS ;
403 break ;
404 case 0x4000 :
405 index = INDEX_PORT ;
406 idx_end = index - 1 + NUMPHYS ;
407#ifndef CONCENTRATOR
408 if (smc->s.sas == SMT_SAS)
409 idx_end = INDEX_PORT ;
410#endif
411 break ;
412 }
413 }
414 }
415 else {
416 /*
417 * smt group has no index
418 */
419 if (!set && (pa->p_len != 0)) {
420 pcon.pc_err = SMT_RDF_LENGTH ;
421 break ;
422 }
423 index = 0 ;
424 idx_end = 0 ;
425 }
426 while (index <= idx_end) {
427 /*
428 * if group
429 * add all paras of group
430 */
431 pt = smt_get_ptab(pa->p_type) ;
432 if (pt && pt->p_access == AC_GROUP && !set) {
433 pt++ ;
434 while (pt->p_access == AC_G ||
435 pt->p_access == AC_GR) {
436 smt_add_para(smc,&pcon,pt->p_num,
437 index,local);
438 pt++ ;
439 }
440 }
441 /*
442 * ignore
443 * AUTHORIZATION in get/set
444 * SET COUNT in set
445 */
446 else if (pa->p_type != SMT_P_AUTHOR &&
447 (!set || (pa->p_type != SMT_P1035))) {
448 int st ;
449 if (pcon.pc_badset) {
450 smt_add_para(smc,&pcon,pa->p_type,
451 index,local) ;
452 }
453 else if (set) {
454 st = smt_set_para(smc,pa,index,local,1);
455 /*
456 * return para even if error
457 */
458 smt_add_para(smc,&pcon,pa->p_type,
459 index,local) ;
460 pcon.pc_err = st ;
461 }
462 else {
463 if (pt && pt->p_access == AC_S) {
464 pcon.pc_err =
465 SMT_RDF_ILLEGAL ;
466 }
467 smt_add_para(smc,&pcon,pa->p_type,
468 index,local) ;
469 }
470 }
471 if (pcon.pc_err)
472 break ;
473 index++ ;
474 }
475 len -= pa->p_len + PARA_LEN ;
476 pa = (struct smt_para *) ((char *)pa + pa->p_len + PARA_LEN) ;
477 }
478 smt->smt_len = SMT_MAX_INFO_LEN - pcon.pc_len ;
479 mb->sm_len = smt->smt_len + sizeof(struct smt_header) ;
480
481 /* update reason code */
482 res->rdf_reason = pcon.pc_badset ? pcon.pc_badset :
483 pcon.pc_err ? pcon.pc_err : SMT_RDF_SUCCESS ;
484 if (set && (res->rdf_reason == SMT_RDF_SUCCESS)) {
485 /*
486 * increment set count
487 * set time stamp
488 * store station id of last set
489 */
490 smc->mib.fddiSMTSetCount.count++ ;
491 smt_set_timestamp(smc,smc->mib.fddiSMTSetCount.timestamp) ;
492 smc->mib.fddiSMTLastSetStationId = req->smt_sid ;
493 smt_add_para(smc,&set_pcon,(u_short) SMT_P1035,0,0) ;
494 smt_add_para(smc,&set_pcon,(u_short) SMT_P1036,0,0) ;
495 }
496 return mb;
497}
498
499static int smt_authorize(struct s_smc *smc, struct smt_header *sm)
500{
501 struct smt_para *pa ;
502 int i ;
503 char *p ;
504
505 /*
506 * check source station id if not zero
507 */
508 p = (char *) &smc->mib.fddiPRPMFStation ;
509 for (i = 0 ; i < 8 && !p[i] ; i++)
510 ;
511 if (i != 8) {
512 if (memcmp((char *) &sm->smt_sid,
513 (char *) &smc->mib.fddiPRPMFStation,8))
514 return 1;
515 }
516 /*
517 * check authoriziation parameter if passwd not zero
518 */
519 p = (char *) smc->mib.fddiPRPMFPasswd ;
520 for (i = 0 ; i < 8 && !p[i] ; i++)
521 ;
522 if (i != 8) {
523 pa = (struct smt_para *) sm_to_para(smc,sm,SMT_P_AUTHOR) ;
524 if (!pa)
525 return 1;
526 if (pa->p_len != 8)
527 return 1;
528 if (memcmp((char *)(pa+1),(char *)smc->mib.fddiPRPMFPasswd,8))
529 return 1;
530 }
531 return 0;
532}
533
534static int smt_check_set_count(struct s_smc *smc, struct smt_header *sm)
535{
536 struct smt_para *pa ;
537 struct smt_p_setcount *sc ;
538
539 pa = (struct smt_para *) sm_to_para(smc,sm,SMT_P1035) ;
540 if (pa) {
541 sc = (struct smt_p_setcount *) pa ;
542 if ((smc->mib.fddiSMTSetCount.count != sc->count) ||
543 memcmp((char *) smc->mib.fddiSMTSetCount.timestamp,
544 (char *)sc->timestamp,8))
545 return 1;
546 }
547 return 0;
548}
549
550void smt_add_para(struct s_smc *smc, struct s_pcon *pcon, u_short para,
551 int index, int local)
552{
553 struct smt_para *pa ;
554 const struct s_p_tab *pt ;
555 struct fddi_mib_m *mib_m = NULL;
556 struct fddi_mib_p *mib_p = NULL;
557 int len ;
558 int plen ;
559 char *from ;
560 char *to ;
561 const char *swap ;
562 char c ;
563 int range ;
564 char *mib_addr ;
565 int mac ;
566 int path ;
567 int port ;
568 int sp_len ;
569
570 /*
571 * skip if error
572 */
573 if (pcon->pc_err)
574 return ;
575
576 /*
577 * actions don't have a value
578 */
579 pt = smt_get_ptab(para) ;
580 if (pt && pt->p_access == AC_S)
581 return ;
582
583 to = (char *) (pcon->pc_p) ; /* destination pointer */
584 len = pcon->pc_len ; /* free space */
585 plen = len ; /* remember start length */
586 pa = (struct smt_para *) to ; /* type/length pointer */
587 to += PARA_LEN ; /* skip smt_para */
588 len -= PARA_LEN ;
589 /*
590 * set index if required
591 */
592 if (((range = (para & 0xf000)) == 0x2000) ||
593 range == 0x3000 || range == 0x4000) {
594 if (len < 4)
595 goto wrong_error ;
596 to[0] = 0 ;
597 to[1] = 0 ;
598 to[2] = 0 ;
599 to[3] = index ;
600 len -= 4 ;
601 to += 4 ;
602 }
603 mac = index - INDEX_MAC ;
604 path = index - INDEX_PATH ;
605 port = index - INDEX_PORT ;
606 /*
607 * get pointer to mib
608 */
609 switch (range) {
610 case 0x1000 :
611 default :
612 mib_addr = (char *) (&smc->mib) ;
613 break ;
614 case 0x2000 :
615 if (mac < 0 || mac >= NUMMACS) {
616 pcon->pc_err = SMT_RDF_NOPARAM ;
617 return ;
618 }
619 mib_addr = (char *) (&smc->mib.m[mac]) ;
620 mib_m = (struct fddi_mib_m *) mib_addr ;
621 break ;
622 case 0x3000 :
623 if (path < 0 || path >= NUMPATHS) {
624 pcon->pc_err = SMT_RDF_NOPARAM ;
625 return ;
626 }
627 mib_addr = (char *) (&smc->mib.a[path]) ;
628 break ;
629 case 0x4000 :
630 if (port < 0 || port >= smt_mib_phys(smc)) {
631 pcon->pc_err = SMT_RDF_NOPARAM ;
632 return ;
633 }
634 mib_addr = (char *) (&smc->mib.p[port_to_mib(smc,port)]) ;
635 mib_p = (struct fddi_mib_p *) mib_addr ;
636 break ;
637 }
638 /*
639 * check special paras
640 */
641 swap = NULL;
642 switch (para) {
643 case SMT_P10F0 :
644 case SMT_P10F1 :
645#ifdef ESS
646 case SMT_P10F2 :
647 case SMT_P10F3 :
648 case SMT_P10F4 :
649 case SMT_P10F5 :
650 case SMT_P10F6 :
651 case SMT_P10F7 :
652#endif
653#ifdef SBA
654 case SMT_P10F8 :
655 case SMT_P10F9 :
656#endif
657 case SMT_P20F1 :
658 if (!local) {
659 pcon->pc_err = SMT_RDF_NOPARAM ;
660 return ;
661 }
662 break ;
663 case SMT_P2034 :
664 case SMT_P2046 :
665 case SMT_P2047 :
666 case SMT_P204A :
667 case SMT_P2051 :
668 case SMT_P2052 :
669 mac_update_counter(smc) ;
670 break ;
671 case SMT_P4022:
672 mib_p->fddiPORTPC_LS = LS2MIB(
673 sm_pm_get_ls(smc,port_to_mib(smc,port))) ;
674 break ;
675 case SMT_P_REASON :
676 * (u_long *) to = 0 ;
677 sp_len = 4 ;
678 goto sp_done ;
679 case SMT_P1033 : /* time stamp */
680 smt_set_timestamp(smc,smc->mib.fddiSMTTimeStamp) ;
681 break ;
682
683 case SMT_P1020: /* port indexes */
684#if NUMPHYS == 12
685 swap = "IIIIIIIIIIII" ;
686#else
687#if NUMPHYS == 2
688 if (smc->s.sas == SMT_SAS)
689 swap = "I" ;
690 else
691 swap = "II" ;
692#else
693#if NUMPHYS == 24
694 swap = "IIIIIIIIIIIIIIIIIIIIIIII" ;
695#else
696 ????
697#endif
698#endif
699#endif
700 break ;
701 case SMT_P3212 :
702 {
703 sp_len = cem_build_path(smc,to,path) ;
704 goto sp_done ;
705 }
706 case SMT_P1048 : /* peer wrap condition */
707 {
708 struct smt_p_1048 *sp ;
709 sp = (struct smt_p_1048 *) to ;
710 sp->p1048_flag = smc->mib.fddiSMTPeerWrapFlag ;
711 sp->p1048_cf_state = smc->mib.fddiSMTCF_State ;
712 sp_len = sizeof(struct smt_p_1048) ;
713 goto sp_done ;
714 }
715 case SMT_P208C :
716 {
717 struct smt_p_208c *sp ;
718 sp = (struct smt_p_208c *) to ;
719 sp->p208c_flag =
720 smc->mib.m[MAC0].fddiMACDuplicateAddressCond ;
721 sp->p208c_dupcondition =
722 (mib_m->fddiMACDA_Flag ? SMT_ST_MY_DUPA : 0) |
723 (mib_m->fddiMACUNDA_Flag ? SMT_ST_UNA_DUPA : 0);
724 sp->p208c_fddilong =
725 mib_m->fddiMACSMTAddress ;
726 sp->p208c_fddiunalong =
727 mib_m->fddiMACUpstreamNbr ;
728 sp->p208c_pad = 0 ;
729 sp_len = sizeof(struct smt_p_208c) ;
730 goto sp_done ;
731 }
732 case SMT_P208D : /* frame error condition */
733 {
734 struct smt_p_208d *sp ;
735 sp = (struct smt_p_208d *) to ;
736 sp->p208d_flag =
737 mib_m->fddiMACFrameErrorFlag ;
738 sp->p208d_frame_ct =
739 mib_m->fddiMACFrame_Ct ;
740 sp->p208d_error_ct =
741 mib_m->fddiMACError_Ct ;
742 sp->p208d_lost_ct =
743 mib_m->fddiMACLost_Ct ;
744 sp->p208d_ratio =
745 mib_m->fddiMACFrameErrorRatio ;
746 sp_len = sizeof(struct smt_p_208d) ;
747 goto sp_done ;
748 }
749 case SMT_P208E : /* not copied condition */
750 {
751 struct smt_p_208e *sp ;
752 sp = (struct smt_p_208e *) to ;
753 sp->p208e_flag =
754 mib_m->fddiMACNotCopiedFlag ;
755 sp->p208e_not_copied =
756 mib_m->fddiMACNotCopied_Ct ;
757 sp->p208e_copied =
758 mib_m->fddiMACCopied_Ct ;
759 sp->p208e_not_copied_ratio =
760 mib_m->fddiMACNotCopiedRatio ;
761 sp_len = sizeof(struct smt_p_208e) ;
762 goto sp_done ;
763 }
764 case SMT_P208F : /* neighbor change event */
765 {
766 struct smt_p_208f *sp ;
767 sp = (struct smt_p_208f *) to ;
768 sp->p208f_multiple =
769 mib_m->fddiMACMultiple_N ;
770 sp->p208f_nacondition =
771 mib_m->fddiMACDuplicateAddressCond ;
772 sp->p208f_old_una =
773 mib_m->fddiMACOldUpstreamNbr ;
774 sp->p208f_new_una =
775 mib_m->fddiMACUpstreamNbr ;
776 sp->p208f_old_dna =
777 mib_m->fddiMACOldDownstreamNbr ;
778 sp->p208f_new_dna =
779 mib_m->fddiMACDownstreamNbr ;
780 sp->p208f_curren_path =
781 mib_m->fddiMACCurrentPath ;
782 sp->p208f_smt_address =
783 mib_m->fddiMACSMTAddress ;
784 sp_len = sizeof(struct smt_p_208f) ;
785 goto sp_done ;
786 }
787 case SMT_P2090 :
788 {
789 struct smt_p_2090 *sp ;
790 sp = (struct smt_p_2090 *) to ;
791 sp->p2090_multiple =
792 mib_m->fddiMACMultiple_P ;
793 sp->p2090_availablepaths =
794 mib_m->fddiMACAvailablePaths ;
795 sp->p2090_currentpath =
796 mib_m->fddiMACCurrentPath ;
797 sp->p2090_requestedpaths =
798 mib_m->fddiMACRequestedPaths ;
799 sp_len = sizeof(struct smt_p_2090) ;
800 goto sp_done ;
801 }
802 case SMT_P4050 :
803 {
804 struct smt_p_4050 *sp ;
805 sp = (struct smt_p_4050 *) to ;
806 sp->p4050_flag =
807 mib_p->fddiPORTLerFlag ;
808 sp->p4050_pad = 0 ;
809 sp->p4050_cutoff =
810 mib_p->fddiPORTLer_Cutoff ;
811 sp->p4050_alarm =
812 mib_p->fddiPORTLer_Alarm ;
813 sp->p4050_estimate =
814 mib_p->fddiPORTLer_Estimate ;
815 sp->p4050_reject_ct =
816 mib_p->fddiPORTLem_Reject_Ct ;
817 sp->p4050_ct =
818 mib_p->fddiPORTLem_Ct ;
819 sp_len = sizeof(struct smt_p_4050) ;
820 goto sp_done ;
821 }
822
823 case SMT_P4051 :
824 {
825 struct smt_p_4051 *sp ;
826 sp = (struct smt_p_4051 *) to ;
827 sp->p4051_multiple =
828 mib_p->fddiPORTMultiple_U ;
829 sp->p4051_porttype =
830 mib_p->fddiPORTMy_Type ;
831 sp->p4051_connectstate =
832 mib_p->fddiPORTConnectState ;
833 sp->p4051_pc_neighbor =
834 mib_p->fddiPORTNeighborType ;
835 sp->p4051_pc_withhold =
836 mib_p->fddiPORTPC_Withhold ;
837 sp_len = sizeof(struct smt_p_4051) ;
838 goto sp_done ;
839 }
840 case SMT_P4052 :
841 {
842 struct smt_p_4052 *sp ;
843 sp = (struct smt_p_4052 *) to ;
844 sp->p4052_flag =
845 mib_p->fddiPORTEB_Condition ;
846 sp->p4052_eberrorcount =
847 mib_p->fddiPORTEBError_Ct ;
848 sp_len = sizeof(struct smt_p_4052) ;
849 goto sp_done ;
850 }
851 case SMT_P4053 :
852 {
853 struct smt_p_4053 *sp ;
854 sp = (struct smt_p_4053 *) to ;
855 sp->p4053_multiple =
856 mib_p->fddiPORTMultiple_P ;
857 sp->p4053_availablepaths =
858 mib_p->fddiPORTAvailablePaths ;
859 sp->p4053_currentpath =
860 mib_p->fddiPORTCurrentPath ;
861 memcpy( (char *) &sp->p4053_requestedpaths,
862 (char *) mib_p->fddiPORTRequestedPaths,4) ;
863 sp->p4053_mytype =
864 mib_p->fddiPORTMy_Type ;
865 sp->p4053_neighbortype =
866 mib_p->fddiPORTNeighborType ;
867 sp_len = sizeof(struct smt_p_4053) ;
868 goto sp_done ;
869 }
870 default :
871 break ;
872 }
873 /*
874 * in table ?
875 */
876 if (!pt) {
877 pcon->pc_err = (para & 0xff00) ? SMT_RDF_NOPARAM :
878 SMT_RDF_ILLEGAL ;
879 return ;
880 }
881 /*
882 * check access rights
883 */
884 switch (pt->p_access) {
885 case AC_G :
886 case AC_GR :
887 break ;
888 default :
889 pcon->pc_err = SMT_RDF_ILLEGAL ;
890 return ;
891 }
892 from = mib_addr + pt->p_offset ;
893 if (!swap)
894 swap = pt->p_swap ; /* pointer to swap string */
895
896 /*
897 * copy values
898 */
899 while ((c = *swap++)) {
900 switch(c) {
901 case 'b' :
902 case 'w' :
903 case 'l' :
904 break ;
905 case 'S' :
906 case 'E' :
907 case 'R' :
908 case 'r' :
909 if (len < 4)
910 goto len_error ;
911 to[0] = 0 ;
912 to[1] = 0 ;
913#ifdef LITTLE_ENDIAN
914 if (c == 'r') {
915 to[2] = *from++ ;
916 to[3] = *from++ ;
917 }
918 else {
919 to[3] = *from++ ;
920 to[2] = *from++ ;
921 }
922#else
923 to[2] = *from++ ;
924 to[3] = *from++ ;
925#endif
926 to += 4 ;
927 len -= 4 ;
928 break ;
929 case 'I' : /* for SET of port indexes */
930 if (len < 2)
931 goto len_error ;
932#ifdef LITTLE_ENDIAN
933 to[1] = *from++ ;
934 to[0] = *from++ ;
935#else
936 to[0] = *from++ ;
937 to[1] = *from++ ;
938#endif
939 to += 2 ;
940 len -= 2 ;
941 break ;
942 case 'F' :
943 case 'B' :
944 if (len < 4)
945 goto len_error ;
946 len -= 4 ;
947 to[0] = 0 ;
948 to[1] = 0 ;
949 to[2] = 0 ;
950 to[3] = *from++ ;
951 to += 4 ;
952 break ;
953 case 'C' :
954 case 'T' :
955 case 'L' :
956 if (len < 4)
957 goto len_error ;
958#ifdef LITTLE_ENDIAN
959 to[3] = *from++ ;
960 to[2] = *from++ ;
961 to[1] = *from++ ;
962 to[0] = *from++ ;
963#else
964 to[0] = *from++ ;
965 to[1] = *from++ ;
966 to[2] = *from++ ;
967 to[3] = *from++ ;
968#endif
969 len -= 4 ;
970 to += 4 ;
971 break ;
972 case '2' : /* PortMacIndicated */
973 if (len < 4)
974 goto len_error ;
975 to[0] = 0 ;
976 to[1] = 0 ;
977 to[2] = *from++ ;
978 to[3] = *from++ ;
979 len -= 4 ;
980 to += 4 ;
981 break ;
982 case '4' :
983 if (len < 4)
984 goto len_error ;
985 to[0] = *from++ ;
986 to[1] = *from++ ;
987 to[2] = *from++ ;
988 to[3] = *from++ ;
989 len -= 4 ;
990 to += 4 ;
991 break ;
992 case 'A' :
993 if (len < 8)
994 goto len_error ;
995 to[0] = 0 ;
996 to[1] = 0 ;
997 memcpy((char *) to+2,(char *) from,6) ;
998 to += 8 ;
999 from += 8 ;
1000 len -= 8 ;
1001 break ;
1002 case '8' :
1003 if (len < 8)
1004 goto len_error ;
1005 memcpy((char *) to,(char *) from,8) ;
1006 to += 8 ;
1007 from += 8 ;
1008 len -= 8 ;
1009 break ;
1010 case 'D' :
1011 if (len < 32)
1012 goto len_error ;
1013 memcpy((char *) to,(char *) from,32) ;
1014 to += 32 ;
1015 from += 32 ;
1016 len -= 32 ;
1017 break ;
1018 case 'P' : /* timestamp is NOT swapped */
1019 if (len < 8)
1020 goto len_error ;
1021 to[0] = *from++ ;
1022 to[1] = *from++ ;
1023 to[2] = *from++ ;
1024 to[3] = *from++ ;
1025 to[4] = *from++ ;
1026 to[5] = *from++ ;
1027 to[6] = *from++ ;
1028 to[7] = *from++ ;
1029 to += 8 ;
1030 len -= 8 ;
1031 break ;
1032 default :
1033 SMT_PANIC(smc,SMT_E0119, SMT_E0119_MSG) ;
1034 break ;
1035 }
1036 }
1037
1038done:
1039 /*
1040 * make it even (in case of 'I' encoding)
1041 * note: len is DECREMENTED
1042 */
1043 if (len & 3) {
1044 to[0] = 0 ;
1045 to[1] = 0 ;
1046 to += 4 - (len & 3 ) ;
1047 len = len & ~ 3 ;
1048 }
1049
1050 /* set type and length */
1051 pa->p_type = para ;
1052 pa->p_len = plen - len - PARA_LEN ;
1053 /* return values */
1054 pcon->pc_p = (void *) to ;
1055 pcon->pc_len = len ;
1056 return ;
1057
1058sp_done:
1059 len -= sp_len ;
1060 to += sp_len ;
1061 goto done ;
1062
1063len_error:
1064 /* parameter does not fit in frame */
1065 pcon->pc_err = SMT_RDF_TOOLONG ;
1066 return ;
1067
1068wrong_error:
1069 pcon->pc_err = SMT_RDF_LENGTH ;
1070}
1071
1072/*
1073 * set parameter
1074 */
1075static int smt_set_para(struct s_smc *smc, struct smt_para *pa, int index,
1076 int local, int set)
1077{
1078#define IFSET(x) if (set) (x)
1079
1080 const struct s_p_tab *pt ;
1081 int len ;
1082 char *from ;
1083 char *to ;
1084 const char *swap ;
1085 char c ;
1086 char *mib_addr ;
1087 struct fddi_mib *mib ;
1088 struct fddi_mib_m *mib_m = NULL;
1089 struct fddi_mib_a *mib_a = NULL;
1090 struct fddi_mib_p *mib_p = NULL;
1091 int mac ;
1092 int path ;
1093 int port ;
1094 SK_LOC_DECL(u_char,byte_val) ;
1095 SK_LOC_DECL(u_short,word_val) ;
1096 SK_LOC_DECL(u_long,long_val) ;
1097
1098 mac = index - INDEX_MAC ;
1099 path = index - INDEX_PATH ;
1100 port = index - INDEX_PORT ;
1101 len = pa->p_len ;
1102 from = (char *) (pa + 1 ) ;
1103
1104 mib = &smc->mib ;
1105 switch (pa->p_type & 0xf000) {
1106 case 0x1000 :
1107 default :
1108 mib_addr = (char *) mib ;
1109 break ;
1110 case 0x2000 :
1111 if (mac < 0 || mac >= NUMMACS) {
1112 return SMT_RDF_NOPARAM;
1113 }
1114 mib_m = &smc->mib.m[mac] ;
1115 mib_addr = (char *) mib_m ;
1116 from += 4 ; /* skip index */
1117 len -= 4 ;
1118 break ;
1119 case 0x3000 :
1120 if (path < 0 || path >= NUMPATHS) {
1121 return SMT_RDF_NOPARAM;
1122 }
1123 mib_a = &smc->mib.a[path] ;
1124 mib_addr = (char *) mib_a ;
1125 from += 4 ; /* skip index */
1126 len -= 4 ;
1127 break ;
1128 case 0x4000 :
1129 if (port < 0 || port >= smt_mib_phys(smc)) {
1130 return SMT_RDF_NOPARAM;
1131 }
1132 mib_p = &smc->mib.p[port_to_mib(smc,port)] ;
1133 mib_addr = (char *) mib_p ;
1134 from += 4 ; /* skip index */
1135 len -= 4 ;
1136 break ;
1137 }
1138 switch (pa->p_type) {
1139 case SMT_P10F0 :
1140 case SMT_P10F1 :
1141#ifdef ESS
1142 case SMT_P10F2 :
1143 case SMT_P10F3 :
1144 case SMT_P10F4 :
1145 case SMT_P10F5 :
1146 case SMT_P10F6 :
1147 case SMT_P10F7 :
1148#endif
1149#ifdef SBA
1150 case SMT_P10F8 :
1151 case SMT_P10F9 :
1152#endif
1153 case SMT_P20F1 :
1154 if (!local)
1155 return SMT_RDF_NOPARAM;
1156 break ;
1157 }
1158 pt = smt_get_ptab(pa->p_type) ;
1159 if (!pt)
1160 return (pa->p_type & 0xff00) ? SMT_RDF_NOPARAM :
1161 SMT_RDF_ILLEGAL;
1162 switch (pt->p_access) {
1163 case AC_GR :
1164 case AC_S :
1165 break ;
1166 default :
1167 return SMT_RDF_ILLEGAL;
1168 }
1169 to = mib_addr + pt->p_offset ;
1170 swap = pt->p_swap ; /* pointer to swap string */
1171
1172 while (swap && (c = *swap++)) {
1173 switch(c) {
1174 case 'b' :
1175 to = (char *) &byte_val ;
1176 break ;
1177 case 'w' :
1178 to = (char *) &word_val ;
1179 break ;
1180 case 'l' :
1181 to = (char *) &long_val ;
1182 break ;
1183 case 'S' :
1184 case 'E' :
1185 case 'R' :
1186 case 'r' :
1187 if (len < 4) {
1188 goto len_error ;
1189 }
1190 if (from[0] | from[1])
1191 goto val_error ;
1192#ifdef LITTLE_ENDIAN
1193 if (c == 'r') {
1194 to[0] = from[2] ;
1195 to[1] = from[3] ;
1196 }
1197 else {
1198 to[1] = from[2] ;
1199 to[0] = from[3] ;
1200 }
1201#else
1202 to[0] = from[2] ;
1203 to[1] = from[3] ;
1204#endif
1205 from += 4 ;
1206 to += 2 ;
1207 len -= 4 ;
1208 break ;
1209 case 'F' :
1210 case 'B' :
1211 if (len < 4) {
1212 goto len_error ;
1213 }
1214 if (from[0] | from[1] | from[2])
1215 goto val_error ;
1216 to[0] = from[3] ;
1217 len -= 4 ;
1218 from += 4 ;
1219 to += 4 ;
1220 break ;
1221 case 'C' :
1222 case 'T' :
1223 case 'L' :
1224 if (len < 4) {
1225 goto len_error ;
1226 }
1227#ifdef LITTLE_ENDIAN
1228 to[3] = *from++ ;
1229 to[2] = *from++ ;
1230 to[1] = *from++ ;
1231 to[0] = *from++ ;
1232#else
1233 to[0] = *from++ ;
1234 to[1] = *from++ ;
1235 to[2] = *from++ ;
1236 to[3] = *from++ ;
1237#endif
1238 len -= 4 ;
1239 to += 4 ;
1240 break ;
1241 case 'A' :
1242 if (len < 8)
1243 goto len_error ;
1244 if (set)
1245 memcpy((char *) to,(char *) from+2,6) ;
1246 to += 8 ;
1247 from += 8 ;
1248 len -= 8 ;
1249 break ;
1250 case '4' :
1251 if (len < 4)
1252 goto len_error ;
1253 if (set)
1254 memcpy((char *) to,(char *) from,4) ;
1255 to += 4 ;
1256 from += 4 ;
1257 len -= 4 ;
1258 break ;
1259 case '8' :
1260 if (len < 8)
1261 goto len_error ;
1262 if (set)
1263 memcpy((char *) to,(char *) from,8) ;
1264 to += 8 ;
1265 from += 8 ;
1266 len -= 8 ;
1267 break ;
1268 case 'D' :
1269 if (len < 32)
1270 goto len_error ;
1271 if (set)
1272 memcpy((char *) to,(char *) from,32) ;
1273 to += 32 ;
1274 from += 32 ;
1275 len -= 32 ;
1276 break ;
1277 case 'P' : /* timestamp is NOT swapped */
1278 if (set) {
1279 to[0] = *from++ ;
1280 to[1] = *from++ ;
1281 to[2] = *from++ ;
1282 to[3] = *from++ ;
1283 to[4] = *from++ ;
1284 to[5] = *from++ ;
1285 to[6] = *from++ ;
1286 to[7] = *from++ ;
1287 }
1288 to += 8 ;
1289 len -= 8 ;
1290 break ;
1291 default :
1292 SMT_PANIC(smc,SMT_E0120, SMT_E0120_MSG) ;
1293 return SMT_RDF_ILLEGAL;
1294 }
1295 }
1296 /*
1297 * actions and internal updates
1298 */
1299 switch (pa->p_type) {
1300 case SMT_P101A: /* fddiSMTConfigPolicy */
1301 if (word_val & ~1)
1302 goto val_error ;
1303 IFSET(mib->fddiSMTConfigPolicy = word_val) ;
1304 break ;
1305 case SMT_P101B : /* fddiSMTConnectionPolicy */
1306 if (!(word_val & POLICY_MM))
1307 goto val_error ;
1308 IFSET(mib->fddiSMTConnectionPolicy = word_val) ;
1309 break ;
1310 case SMT_P101D : /* fddiSMTTT_Notify */
1311 if (word_val < 2 || word_val > 30)
1312 goto val_error ;
1313 IFSET(mib->fddiSMTTT_Notify = word_val) ;
1314 break ;
1315 case SMT_P101E : /* fddiSMTStatRptPolicy */
1316 if (byte_val & ~1)
1317 goto val_error ;
1318 IFSET(mib->fddiSMTStatRptPolicy = byte_val) ;
1319 break ;
1320 case SMT_P101F : /* fddiSMTTrace_MaxExpiration */
1321 /*
1322 * note: lower limit trace_max = 6.001773... s
1323 * NO upper limit
1324 */
1325 if (long_val < (long)0x478bf51L)
1326 goto val_error ;
1327 IFSET(mib->fddiSMTTrace_MaxExpiration = long_val) ;
1328 break ;
1329#ifdef ESS
1330 case SMT_P10F2 : /* fddiESSPayload */
1331 if (long_val > 1562)
1332 goto val_error ;
1333 if (set && smc->mib.fddiESSPayload != long_val) {
1334 smc->ess.raf_act_timer_poll = TRUE ;
1335 smc->mib.fddiESSPayload = long_val ;
1336 }
1337 break ;
1338 case SMT_P10F3 : /* fddiESSOverhead */
1339 if (long_val < 50 || long_val > 5000)
1340 goto val_error ;
1341 if (set && smc->mib.fddiESSPayload &&
1342 smc->mib.fddiESSOverhead != long_val) {
1343 smc->ess.raf_act_timer_poll = TRUE ;
1344 smc->mib.fddiESSOverhead = long_val ;
1345 }
1346 break ;
1347 case SMT_P10F4 : /* fddiESSMaxTNeg */
1348 if (long_val > -MS2BCLK(5) || long_val < -MS2BCLK(165))
1349 goto val_error ;
1350 IFSET(mib->fddiESSMaxTNeg = long_val) ;
1351 break ;
1352 case SMT_P10F5 : /* fddiESSMinSegmentSize */
1353 if (long_val < 1 || long_val > 4478)
1354 goto val_error ;
1355 IFSET(mib->fddiESSMinSegmentSize = long_val) ;
1356 break ;
1357 case SMT_P10F6 : /* fddiESSCategory */
1358 if ((long_val & 0xffff) != 1)
1359 goto val_error ;
1360 IFSET(mib->fddiESSCategory = long_val) ;
1361 break ;
1362 case SMT_P10F7 : /* fddiESSSyncTxMode */
1363 if (word_val > 1)
1364 goto val_error ;
1365 IFSET(mib->fddiESSSynchTxMode = word_val) ;
1366 break ;
1367#endif
1368#ifdef SBA
1369 case SMT_P10F8 : /* fddiSBACommand */
1370 if (byte_val != SB_STOP && byte_val != SB_START)
1371 goto val_error ;
1372 IFSET(mib->fddiSBACommand = byte_val) ;
1373 break ;
1374 case SMT_P10F9 : /* fddiSBAAvailable */
1375 if (byte_val > 100)
1376 goto val_error ;
1377 IFSET(mib->fddiSBAAvailable = byte_val) ;
1378 break ;
1379#endif
1380 case SMT_P2020 : /* fddiMACRequestedPaths */
1381 if ((word_val & (MIB_P_PATH_PRIM_PREFER |
1382 MIB_P_PATH_PRIM_ALTER)) == 0 )
1383 goto val_error ;
1384 IFSET(mib_m->fddiMACRequestedPaths = word_val) ;
1385 break ;
1386 case SMT_P205F : /* fddiMACFrameErrorThreshold */
1387 /* 0 .. ffff acceptable */
1388 IFSET(mib_m->fddiMACFrameErrorThreshold = word_val) ;
1389 break ;
1390 case SMT_P2067 : /* fddiMACNotCopiedThreshold */
1391 /* 0 .. ffff acceptable */
1392 IFSET(mib_m->fddiMACNotCopiedThreshold = word_val) ;
1393 break ;
1394 case SMT_P2076: /* fddiMACMA_UnitdataEnable */
1395 if (byte_val & ~1)
1396 goto val_error ;
1397 if (set) {
1398 mib_m->fddiMACMA_UnitdataEnable = byte_val ;
1399 queue_event(smc,EVENT_RMT,RM_ENABLE_FLAG) ;
1400 }
1401 break ;
1402 case SMT_P20F1 : /* fddiMACT_Min */
1403 IFSET(mib_m->fddiMACT_Min = long_val) ;
1404 break ;
1405 case SMT_P320F :
1406 if (long_val > 1562)
1407 goto val_error ;
1408 IFSET(mib_a->fddiPATHSbaPayload = long_val) ;
1409#ifdef ESS
1410 if (set)
1411 ess_para_change(smc) ;
1412#endif
1413 break ;
1414 case SMT_P3210 :
1415 if (long_val > 5000)
1416 goto val_error ;
1417
1418 if (long_val != 0 && mib_a->fddiPATHSbaPayload == 0)
1419 goto val_error ;
1420
1421 IFSET(mib_a->fddiPATHSbaOverhead = long_val) ;
1422#ifdef ESS
1423 if (set)
1424 ess_para_change(smc) ;
1425#endif
1426 break ;
1427 case SMT_P3213: /* fddiPATHT_Rmode */
1428 /* no limit :
1429 * 0 .. 343.597 => 0 .. 2e32 * 80nS
1430 */
1431 if (set) {
1432 mib_a->fddiPATHT_Rmode = long_val ;
1433 rtm_set_timer(smc) ;
1434 }
1435 break ;
1436 case SMT_P3214 : /* fddiPATHSbaAvailable */
1437 if (long_val > 0x00BEBC20L)
1438 goto val_error ;
1439#ifdef SBA
1440 if (set && mib->fddiSBACommand == SB_STOP)
1441 goto val_error ;
1442#endif
1443 IFSET(mib_a->fddiPATHSbaAvailable = long_val) ;
1444 break ;
1445 case SMT_P3215 : /* fddiPATHTVXLowerBound */
1446 IFSET(mib_a->fddiPATHTVXLowerBound = long_val) ;
1447 goto change_mac_para ;
1448 case SMT_P3216 : /* fddiPATHT_MaxLowerBound */
1449 IFSET(mib_a->fddiPATHT_MaxLowerBound = long_val) ;
1450 goto change_mac_para ;
1451 case SMT_P3217 : /* fddiPATHMaxT_Req */
1452 IFSET(mib_a->fddiPATHMaxT_Req = long_val) ;
1453
1454change_mac_para:
1455 if (set && smt_set_mac_opvalues(smc)) {
1456 RS_SET(smc,RS_EVENT) ;
1457 smc->sm.please_reconnect = 1 ;
1458 queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
1459 }
1460 break ;
1461 case SMT_P400E : /* fddiPORTConnectionPolicies */
1462 if (byte_val > 1)
1463 goto val_error ;
1464 IFSET(mib_p->fddiPORTConnectionPolicies = byte_val) ;
1465 break ;
1466 case SMT_P4011 : /* fddiPORTRequestedPaths */
1467 /* all 3*8 bits allowed */
1468 IFSET(memcpy((char *)mib_p->fddiPORTRequestedPaths,
1469 (char *)&long_val,4)) ;
1470 break ;
1471 case SMT_P401F: /* fddiPORTMaint_LS */
1472 if (word_val > 4)
1473 goto val_error ;
1474 IFSET(mib_p->fddiPORTMaint_LS = word_val) ;
1475 break ;
1476 case SMT_P403A : /* fddiPORTLer_Cutoff */
1477 if (byte_val < 4 || byte_val > 15)
1478 goto val_error ;
1479 IFSET(mib_p->fddiPORTLer_Cutoff = byte_val) ;
1480 break ;
1481 case SMT_P403B : /* fddiPORTLer_Alarm */
1482 if (byte_val < 4 || byte_val > 15)
1483 goto val_error ;
1484 IFSET(mib_p->fddiPORTLer_Alarm = byte_val) ;
1485 break ;
1486
1487 /*
1488 * Actions
1489 */
1490 case SMT_P103C : /* fddiSMTStationAction */
1491 if (smt_action(smc,SMT_STATION_ACTION, (int) word_val, 0))
1492 goto val_error ;
1493 break ;
1494 case SMT_P4046: /* fddiPORTAction */
1495 if (smt_action(smc,SMT_PORT_ACTION, (int) word_val,
1496 port_to_mib(smc,port)))
1497 goto val_error ;
1498 break ;
1499 default :
1500 break ;
1501 }
1502 return 0;
1503
1504val_error:
1505 /* parameter value in frame is out of range */
1506 return SMT_RDF_RANGE;
1507
1508len_error:
1509 /* parameter value in frame is too short */
1510 return SMT_RDF_LENGTH;
1511
1512#if 0
1513no_author_error:
1514 /* parameter not setable, because the SBA is not active
1515 * Please note: we give the return code 'not authorizeed
1516 * because SBA denied is not a valid return code in the
1517 * PMF protocol.
1518 */
1519 return SMT_RDF_AUTHOR;
1520#endif
1521}
1522
1523static const struct s_p_tab *smt_get_ptab(u_short para)
1524{
1525 const struct s_p_tab *pt ;
1526 for (pt = p_tab ; pt->p_num && pt->p_num != para ; pt++)
1527 ;
1528 return pt->p_num ? pt : NULL;
1529}
1530
1531static int smt_mib_phys(struct s_smc *smc)
1532{
1533#ifdef CONCENTRATOR
1534 SK_UNUSED(smc) ;
1535
1536 return NUMPHYS;
1537#else
1538 if (smc->s.sas == SMT_SAS)
1539 return 1;
1540 return NUMPHYS;
1541#endif
1542}
1543
1544static int port_to_mib(struct s_smc *smc, int p)
1545{
1546#ifdef CONCENTRATOR
1547 SK_UNUSED(smc) ;
1548
1549 return p;
1550#else
1551 if (smc->s.sas == SMT_SAS)
1552 return PS;
1553 return p;
1554#endif
1555}
1556
1557
1558#ifdef DEBUG
1559#ifndef BOOT
1560void dump_smt(struct s_smc *smc, struct smt_header *sm, char *text)
1561{
1562 int len ;
1563 struct smt_para *pa ;
1564 char *c ;
1565 int n ;
1566 int nn ;
1567#ifdef LITTLE_ENDIAN
1568 int smtlen ;
1569#endif
1570
1571 SK_UNUSED(smc) ;
1572
1573#ifdef DEBUG_BRD
1574 if (smc->debug.d_smtf < 2)
1575#else
1576 if (debug.d_smtf < 2)
1577#endif
1578 return ;
1579#ifdef LITTLE_ENDIAN
1580 smtlen = sm->smt_len + sizeof(struct smt_header) ;
1581#endif
1582 printf("SMT Frame [%s]:\nDA ",text) ;
1583 dump_hex((char *) &sm->smt_dest,6) ;
1584 printf("\tSA ") ;
1585 dump_hex((char *) &sm->smt_source,6) ;
1586 printf(" Class %x Type %x Version %x\n",
1587 sm->smt_class,sm->smt_type,sm->smt_version) ;
1588 printf("TID %lx\t\tSID ",sm->smt_tid) ;
1589 dump_hex((char *) &sm->smt_sid,8) ;
1590 printf(" LEN %x\n",sm->smt_len) ;
1591
1592 len = sm->smt_len ;
1593 pa = (struct smt_para *) (sm + 1) ;
1594 while (len > 0 ) {
1595 int plen ;
1596#ifdef UNIX
1597 printf("TYPE %x LEN %x VALUE\t",pa->p_type,pa->p_len) ;
1598#else
1599 printf("TYPE %04x LEN %2x VALUE\t",pa->p_type,pa->p_len) ;
1600#endif
1601 n = pa->p_len ;
1602 if ( (n < 0 ) || (n > (int)(len - PARA_LEN))) {
1603 n = len - PARA_LEN ;
1604 printf(" BAD LENGTH\n") ;
1605 break ;
1606 }
1607#ifdef LITTLE_ENDIAN
1608 smt_swap_para(sm,smtlen,0) ;
1609#endif
1610 if (n < 24) {
1611 dump_hex((char *)(pa+1),(int) n) ;
1612 printf("\n") ;
1613 }
1614 else {
1615 int first = 0 ;
1616 c = (char *)(pa+1) ;
1617 dump_hex(c,16) ;
1618 printf("\n") ;
1619 n -= 16 ;
1620 c += 16 ;
1621 while (n > 0) {
1622 nn = (n > 16) ? 16 : n ;
1623 if (n > 64) {
1624 if (first == 0)
1625 printf("\t\t\t...\n") ;
1626 first = 1 ;
1627 }
1628 else {
1629 printf("\t\t\t") ;
1630 dump_hex(c,nn) ;
1631 printf("\n") ;
1632 }
1633 n -= nn ;
1634 c += 16 ;
1635 }
1636 }
1637#ifdef LITTLE_ENDIAN
1638 smt_swap_para(sm,smtlen,1) ;
1639#endif
1640 plen = (pa->p_len + PARA_LEN + 3) & ~3 ;
1641 len -= plen ;
1642 pa = (struct smt_para *)((char *)pa + plen) ;
1643 }
1644 printf("-------------------------------------------------\n\n") ;
1645}
1646
1647void dump_hex(char *p, int len)
1648{
1649 int n = 0 ;
1650 while (len--) {
1651 n++ ;
1652#ifdef UNIX
1653 printf("%x%s",*p++ & 0xff,len ? ( (n & 7) ? " " : "-") : "") ;
1654#else
1655 printf("%02x%s",*p++ & 0xff,len ? ( (n & 7) ? " " : "-") : "") ;
1656#endif
1657 }
1658}
1659#endif /* no BOOT */
1660#endif /* DEBUG */
1661
1662
1663#endif /* no SLIM_SMT */
diff --git a/drivers/net/skfp/queue.c b/drivers/net/skfp/queue.c
deleted file mode 100644
index c1a0df455a59..000000000000
--- a/drivers/net/skfp/queue.c
+++ /dev/null
@@ -1,173 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 SMT Event Queue Management
19*/
20
21#include "h/types.h"
22#include "h/fddi.h"
23#include "h/smc.h"
24
25#ifndef lint
26static const char ID_sccs[] = "@(#)queue.c 2.9 97/08/04 (C) SK " ;
27#endif
28
29#define PRINTF(a,b,c)
30
31/*
32 * init event queue management
33 */
34void ev_init(struct s_smc *smc)
35{
36 smc->q.ev_put = smc->q.ev_get = smc->q.ev_queue ;
37}
38
39/*
40 * add event to queue
41 */
42void queue_event(struct s_smc *smc, int class, int event)
43{
44 PRINTF("queue class %d event %d\n",class,event) ;
45 smc->q.ev_put->class = class ;
46 smc->q.ev_put->event = event ;
47 if (++smc->q.ev_put == &smc->q.ev_queue[MAX_EVENT])
48 smc->q.ev_put = smc->q.ev_queue ;
49
50 if (smc->q.ev_put == smc->q.ev_get) {
51 SMT_ERR_LOG(smc,SMT_E0137, SMT_E0137_MSG) ;
52 }
53}
54
55/*
56 * timer_event is called from HW timer package.
57 */
58void timer_event(struct s_smc *smc, u_long token)
59{
60 PRINTF("timer event class %d token %d\n",
61 EV_T_CLASS(token),
62 EV_T_EVENT(token)) ;
63 queue_event(smc,EV_T_CLASS(token),EV_T_EVENT(token));
64}
65
66/*
67 * event dispatcher
68 * while event queue is not empty
69 * get event from queue
70 * send command to state machine
71 * end
72 */
73void ev_dispatcher(struct s_smc *smc)
74{
75 struct event_queue *ev ; /* pointer into queue */
76 int class ;
77
78 ev = smc->q.ev_get ;
79 PRINTF("dispatch get %x put %x\n",ev,smc->q.ev_put) ;
80 while (ev != smc->q.ev_put) {
81 PRINTF("dispatch class %d event %d\n",ev->class,ev->event) ;
82 switch(class = ev->class) {
83 case EVENT_ECM : /* Entity Corordination Man. */
84 ecm(smc,(int)ev->event) ;
85 break ;
86 case EVENT_CFM : /* Configuration Man. */
87 cfm(smc,(int)ev->event) ;
88 break ;
89 case EVENT_RMT : /* Ring Man. */
90 rmt(smc,(int)ev->event) ;
91 break ;
92 case EVENT_SMT :
93 smt_event(smc,(int)ev->event) ;
94 break ;
95#ifdef CONCENTRATOR
96 case 99 :
97 timer_test_event(smc,(int)ev->event) ;
98 break ;
99#endif
100 case EVENT_PCMA : /* PHY A */
101 case EVENT_PCMB : /* PHY B */
102 default :
103 if (class >= EVENT_PCMA &&
104 class < EVENT_PCMA + NUMPHYS) {
105 pcm(smc,class - EVENT_PCMA,(int)ev->event) ;
106 break ;
107 }
108 SMT_PANIC(smc,SMT_E0121, SMT_E0121_MSG) ;
109 return ;
110 }
111
112 if (++ev == &smc->q.ev_queue[MAX_EVENT])
113 ev = smc->q.ev_queue ;
114
115 /* Renew get: it is used in queue_events to detect overruns */
116 smc->q.ev_get = ev;
117 }
118}
119
120/*
121 * smt_online connects to or disconnects from the ring
122 * MUST be called to initiate connection establishment
123 *
124 * on 0 disconnect
125 * on 1 connect
126 */
127u_short smt_online(struct s_smc *smc, int on)
128{
129 queue_event(smc,EVENT_ECM,on ? EC_CONNECT : EC_DISCONNECT) ;
130 ev_dispatcher(smc) ;
131 return smc->mib.fddiSMTCF_State;
132}
133
134/*
135 * set SMT flag to value
136 * flag flag name
137 * value flag value
138 * dump current flag setting
139 */
140#ifdef CONCENTRATOR
141void do_smt_flag(struct s_smc *smc, char *flag, int value)
142{
143#ifdef DEBUG
144 struct smt_debug *deb;
145
146 SK_UNUSED(smc) ;
147
148#ifdef DEBUG_BRD
149 deb = &smc->debug;
150#else
151 deb = &debug;
152#endif
153 if (!strcmp(flag,"smt"))
154 deb->d_smt = value ;
155 else if (!strcmp(flag,"smtf"))
156 deb->d_smtf = value ;
157 else if (!strcmp(flag,"pcm"))
158 deb->d_pcm = value ;
159 else if (!strcmp(flag,"rmt"))
160 deb->d_rmt = value ;
161 else if (!strcmp(flag,"cfm"))
162 deb->d_cfm = value ;
163 else if (!strcmp(flag,"ecm"))
164 deb->d_ecm = value ;
165 printf("smt %d\n",deb->d_smt) ;
166 printf("smtf %d\n",deb->d_smtf) ;
167 printf("pcm %d\n",deb->d_pcm) ;
168 printf("rmt %d\n",deb->d_rmt) ;
169 printf("cfm %d\n",deb->d_cfm) ;
170 printf("ecm %d\n",deb->d_ecm) ;
171#endif /* DEBUG */
172}
173#endif
diff --git a/drivers/net/skfp/rmt.c b/drivers/net/skfp/rmt.c
deleted file mode 100644
index ef8d5672d9e8..000000000000
--- a/drivers/net/skfp/rmt.c
+++ /dev/null
@@ -1,654 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 SMT RMT
19 Ring Management
20*/
21
22/*
23 * Hardware independent state machine implemantation
24 * The following external SMT functions are referenced :
25 *
26 * queue_event()
27 * smt_timer_start()
28 * smt_timer_stop()
29 *
30 * The following external HW dependent functions are referenced :
31 * sm_ma_control()
32 * sm_mac_check_beacon_claim()
33 *
34 * The following HW dependent events are required :
35 * RM_RING_OP
36 * RM_RING_NON_OP
37 * RM_MY_BEACON
38 * RM_OTHER_BEACON
39 * RM_MY_CLAIM
40 * RM_TRT_EXP
41 * RM_VALID_CLAIM
42 *
43 */
44
45#include "h/types.h"
46#include "h/fddi.h"
47#include "h/smc.h"
48
49#define KERNEL
50#include "h/smtstate.h"
51
52#ifndef lint
53static const char ID_sccs[] = "@(#)rmt.c 2.13 99/07/02 (C) SK " ;
54#endif
55
56/*
57 * FSM Macros
58 */
59#define AFLAG 0x10
60#define GO_STATE(x) (smc->mib.m[MAC0].fddiMACRMTState = (x)|AFLAG)
61#define ACTIONS_DONE() (smc->mib.m[MAC0].fddiMACRMTState &= ~AFLAG)
62#define ACTIONS(x) (x|AFLAG)
63
64#define RM0_ISOLATED 0
65#define RM1_NON_OP 1 /* not operational */
66#define RM2_RING_OP 2 /* ring operational */
67#define RM3_DETECT 3 /* detect dupl addresses */
68#define RM4_NON_OP_DUP 4 /* dupl. addr detected */
69#define RM5_RING_OP_DUP 5 /* ring oper. with dupl. addr */
70#define RM6_DIRECTED 6 /* sending directed beacons */
71#define RM7_TRACE 7 /* trace initiated */
72
73#ifdef DEBUG
74/*
75 * symbolic state names
76 */
77static const char * const rmt_states[] = {
78 "RM0_ISOLATED","RM1_NON_OP","RM2_RING_OP","RM3_DETECT",
79 "RM4_NON_OP_DUP","RM5_RING_OP_DUP","RM6_DIRECTED",
80 "RM7_TRACE"
81} ;
82
83/*
84 * symbolic event names
85 */
86static const char * const rmt_events[] = {
87 "NONE","RM_RING_OP","RM_RING_NON_OP","RM_MY_BEACON",
88 "RM_OTHER_BEACON","RM_MY_CLAIM","RM_TRT_EXP","RM_VALID_CLAIM",
89 "RM_JOIN","RM_LOOP","RM_DUP_ADDR","RM_ENABLE_FLAG",
90 "RM_TIMEOUT_NON_OP","RM_TIMEOUT_T_STUCK",
91 "RM_TIMEOUT_ANNOUNCE","RM_TIMEOUT_T_DIRECT",
92 "RM_TIMEOUT_D_MAX","RM_TIMEOUT_POLL","RM_TX_STATE_CHANGE"
93} ;
94#endif
95
96/*
97 * Globals
98 * in struct s_rmt
99 */
100
101
102/*
103 * function declarations
104 */
105static void rmt_fsm(struct s_smc *smc, int cmd);
106static void start_rmt_timer0(struct s_smc *smc, u_long value, int event);
107static void start_rmt_timer1(struct s_smc *smc, u_long value, int event);
108static void start_rmt_timer2(struct s_smc *smc, u_long value, int event);
109static void stop_rmt_timer0(struct s_smc *smc);
110static void stop_rmt_timer1(struct s_smc *smc);
111static void stop_rmt_timer2(struct s_smc *smc);
112static void rmt_dup_actions(struct s_smc *smc);
113static void rmt_reinsert_actions(struct s_smc *smc);
114static void rmt_leave_actions(struct s_smc *smc);
115static void rmt_new_dup_actions(struct s_smc *smc);
116
117#ifndef SUPERNET_3
118extern void restart_trt_for_dbcn() ;
119#endif /*SUPERNET_3*/
120
121/*
122 init RMT state machine
123 clear all RMT vars and flags
124*/
125void rmt_init(struct s_smc *smc)
126{
127 smc->mib.m[MAC0].fddiMACRMTState = ACTIONS(RM0_ISOLATED) ;
128 smc->r.dup_addr_test = DA_NONE ;
129 smc->r.da_flag = 0 ;
130 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
131 smc->r.sm_ma_avail = FALSE ;
132 smc->r.loop_avail = 0 ;
133 smc->r.bn_flag = 0 ;
134 smc->r.jm_flag = 0 ;
135 smc->r.no_flag = TRUE ;
136}
137
138/*
139 RMT state machine
140 called by dispatcher
141
142 do
143 display state change
144 process event
145 until SM is stable
146*/
147void rmt(struct s_smc *smc, int event)
148{
149 int state ;
150
151 do {
152 DB_RMT("RMT : state %s%s",
153 (smc->mib.m[MAC0].fddiMACRMTState & AFLAG) ? "ACTIONS " : "",
154 rmt_states[smc->mib.m[MAC0].fddiMACRMTState & ~AFLAG]) ;
155 DB_RMT(" event %s\n",rmt_events[event],0) ;
156 state = smc->mib.m[MAC0].fddiMACRMTState ;
157 rmt_fsm(smc,event) ;
158 event = 0 ;
159 } while (state != smc->mib.m[MAC0].fddiMACRMTState) ;
160 rmt_state_change(smc,(int)smc->mib.m[MAC0].fddiMACRMTState) ;
161}
162
163/*
164 process RMT event
165*/
166static void rmt_fsm(struct s_smc *smc, int cmd)
167{
168 /*
169 * RM00-RM70 : from all states
170 */
171 if (!smc->r.rm_join && !smc->r.rm_loop &&
172 smc->mib.m[MAC0].fddiMACRMTState != ACTIONS(RM0_ISOLATED) &&
173 smc->mib.m[MAC0].fddiMACRMTState != RM0_ISOLATED) {
174 RS_SET(smc,RS_NORINGOP) ;
175 rmt_indication(smc,0) ;
176 GO_STATE(RM0_ISOLATED) ;
177 return ;
178 }
179
180 switch(smc->mib.m[MAC0].fddiMACRMTState) {
181 case ACTIONS(RM0_ISOLATED) :
182 stop_rmt_timer0(smc) ;
183 stop_rmt_timer1(smc) ;
184 stop_rmt_timer2(smc) ;
185
186 /*
187 * Disable MAC.
188 */
189 sm_ma_control(smc,MA_OFFLINE) ;
190 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
191 smc->r.loop_avail = FALSE ;
192 smc->r.sm_ma_avail = FALSE ;
193 smc->r.no_flag = TRUE ;
194 DB_RMTN(1,"RMT : ISOLATED\n",0,0) ;
195 ACTIONS_DONE() ;
196 break ;
197 case RM0_ISOLATED :
198 /*RM01*/
199 if (smc->r.rm_join || smc->r.rm_loop) {
200 /*
201 * According to the standard the MAC must be reset
202 * here. The FORMAC will be initialized and Claim
203 * and Beacon Frames will be uploaded to the MAC.
204 * So any change of Treq will take effect NOW.
205 */
206 sm_ma_control(smc,MA_RESET) ;
207 GO_STATE(RM1_NON_OP) ;
208 break ;
209 }
210 break ;
211 case ACTIONS(RM1_NON_OP) :
212 start_rmt_timer0(smc,smc->s.rmt_t_non_op,RM_TIMEOUT_NON_OP) ;
213 stop_rmt_timer1(smc) ;
214 stop_rmt_timer2(smc) ;
215 sm_ma_control(smc,MA_BEACON) ;
216 DB_RMTN(1,"RMT : RING DOWN\n",0,0) ;
217 RS_SET(smc,RS_NORINGOP) ;
218 smc->r.sm_ma_avail = FALSE ;
219 rmt_indication(smc,0) ;
220 ACTIONS_DONE() ;
221 break ;
222 case RM1_NON_OP :
223 /*RM12*/
224 if (cmd == RM_RING_OP) {
225 RS_SET(smc,RS_RINGOPCHANGE) ;
226 GO_STATE(RM2_RING_OP) ;
227 break ;
228 }
229 /*RM13*/
230 else if (cmd == RM_TIMEOUT_NON_OP) {
231 smc->r.bn_flag = FALSE ;
232 smc->r.no_flag = TRUE ;
233 GO_STATE(RM3_DETECT) ;
234 break ;
235 }
236 break ;
237 case ACTIONS(RM2_RING_OP) :
238 stop_rmt_timer0(smc) ;
239 stop_rmt_timer1(smc) ;
240 stop_rmt_timer2(smc) ;
241 smc->r.no_flag = FALSE ;
242 if (smc->r.rm_loop)
243 smc->r.loop_avail = TRUE ;
244 if (smc->r.rm_join) {
245 smc->r.sm_ma_avail = TRUE ;
246 if (smc->mib.m[MAC0].fddiMACMA_UnitdataEnable)
247 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = TRUE ;
248 else
249 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
250 }
251 DB_RMTN(1,"RMT : RING UP\n",0,0) ;
252 RS_CLEAR(smc,RS_NORINGOP) ;
253 RS_SET(smc,RS_RINGOPCHANGE) ;
254 rmt_indication(smc,1) ;
255 smt_stat_counter(smc,0) ;
256 ACTIONS_DONE() ;
257 break ;
258 case RM2_RING_OP :
259 /*RM21*/
260 if (cmd == RM_RING_NON_OP) {
261 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
262 smc->r.loop_avail = FALSE ;
263 RS_SET(smc,RS_RINGOPCHANGE) ;
264 GO_STATE(RM1_NON_OP) ;
265 break ;
266 }
267 /*RM22a*/
268 else if (cmd == RM_ENABLE_FLAG) {
269 if (smc->mib.m[MAC0].fddiMACMA_UnitdataEnable)
270 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = TRUE ;
271 else
272 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
273 }
274 /*RM25*/
275 else if (smc->r.dup_addr_test == DA_FAILED) {
276 smc->mib.m[MAC0].fddiMACMA_UnitdataAvailable = FALSE ;
277 smc->r.loop_avail = FALSE ;
278 smc->r.da_flag = TRUE ;
279 GO_STATE(RM5_RING_OP_DUP) ;
280 break ;
281 }
282 break ;
283 case ACTIONS(RM3_DETECT) :
284 start_rmt_timer0(smc,smc->s.mac_d_max*2,RM_TIMEOUT_D_MAX) ;
285 start_rmt_timer1(smc,smc->s.rmt_t_stuck,RM_TIMEOUT_T_STUCK) ;
286 start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL) ;
287 sm_mac_check_beacon_claim(smc) ;
288 DB_RMTN(1,"RMT : RM3_DETECT\n",0,0) ;
289 ACTIONS_DONE() ;
290 break ;
291 case RM3_DETECT :
292 if (cmd == RM_TIMEOUT_POLL) {
293 start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL);
294 sm_mac_check_beacon_claim(smc) ;
295 break ;
296 }
297 if (cmd == RM_TIMEOUT_D_MAX) {
298 smc->r.timer0_exp = TRUE ;
299 }
300 /*
301 *jd(22-Feb-1999)
302 * We need a time ">= 2*mac_d_max" since we had finished
303 * Claim or Beacon state. So we will restart timer0 at
304 * every state change.
305 */
306 if (cmd == RM_TX_STATE_CHANGE) {
307 start_rmt_timer0(smc,
308 smc->s.mac_d_max*2,
309 RM_TIMEOUT_D_MAX) ;
310 }
311 /*RM32*/
312 if (cmd == RM_RING_OP) {
313 GO_STATE(RM2_RING_OP) ;
314 break ;
315 }
316 /*RM33a*/
317 else if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON)
318 && smc->r.bn_flag) {
319 smc->r.bn_flag = FALSE ;
320 }
321 /*RM33b*/
322 else if (cmd == RM_TRT_EXP && !smc->r.bn_flag) {
323 int tx ;
324 /*
325 * set bn_flag only if in state T4 or T5:
326 * only if we're the beaconer should we start the
327 * trace !
328 */
329 if ((tx = sm_mac_get_tx_state(smc)) == 4 || tx == 5) {
330 DB_RMTN(2,"RMT : DETECT && TRT_EXPIRED && T4/T5\n",0,0);
331 smc->r.bn_flag = TRUE ;
332 /*
333 * If one of the upstream stations beaconed
334 * and the link to the upstream neighbor is
335 * lost we need to restart the stuck timer to
336 * check the "stuck beacon" condition.
337 */
338 start_rmt_timer1(smc,smc->s.rmt_t_stuck,
339 RM_TIMEOUT_T_STUCK) ;
340 }
341 /*
342 * We do NOT need to clear smc->r.bn_flag in case of
343 * not being in state T4 or T5, because the flag
344 * must be cleared in order to get in this condition.
345 */
346
347 DB_RMTN(2,
348 "RMT : sm_mac_get_tx_state() = %d (bn_flag = %d)\n",
349 tx,smc->r.bn_flag) ;
350 }
351 /*RM34a*/
352 else if (cmd == RM_MY_CLAIM && smc->r.timer0_exp) {
353 rmt_new_dup_actions(smc) ;
354 GO_STATE(RM4_NON_OP_DUP) ;
355 break ;
356 }
357 /*RM34b*/
358 else if (cmd == RM_MY_BEACON && smc->r.timer0_exp) {
359 rmt_new_dup_actions(smc) ;
360 GO_STATE(RM4_NON_OP_DUP) ;
361 break ;
362 }
363 /*RM34c*/
364 else if (cmd == RM_VALID_CLAIM) {
365 rmt_new_dup_actions(smc) ;
366 GO_STATE(RM4_NON_OP_DUP) ;
367 break ;
368 }
369 /*RM36*/
370 else if (cmd == RM_TIMEOUT_T_STUCK &&
371 smc->r.rm_join && smc->r.bn_flag) {
372 GO_STATE(RM6_DIRECTED) ;
373 break ;
374 }
375 break ;
376 case ACTIONS(RM4_NON_OP_DUP) :
377 start_rmt_timer0(smc,smc->s.rmt_t_announce,RM_TIMEOUT_ANNOUNCE);
378 start_rmt_timer1(smc,smc->s.rmt_t_stuck,RM_TIMEOUT_T_STUCK) ;
379 start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL) ;
380 sm_mac_check_beacon_claim(smc) ;
381 DB_RMTN(1,"RMT : RM4_NON_OP_DUP\n",0,0) ;
382 ACTIONS_DONE() ;
383 break ;
384 case RM4_NON_OP_DUP :
385 if (cmd == RM_TIMEOUT_POLL) {
386 start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL);
387 sm_mac_check_beacon_claim(smc) ;
388 break ;
389 }
390 /*RM41*/
391 if (!smc->r.da_flag) {
392 GO_STATE(RM1_NON_OP) ;
393 break ;
394 }
395 /*RM44a*/
396 else if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON) &&
397 smc->r.bn_flag) {
398 smc->r.bn_flag = FALSE ;
399 }
400 /*RM44b*/
401 else if (cmd == RM_TRT_EXP && !smc->r.bn_flag) {
402 int tx ;
403 /*
404 * set bn_flag only if in state T4 or T5:
405 * only if we're the beaconer should we start the
406 * trace !
407 */
408 if ((tx = sm_mac_get_tx_state(smc)) == 4 || tx == 5) {
409 DB_RMTN(2,"RMT : NOPDUP && TRT_EXPIRED && T4/T5\n",0,0);
410 smc->r.bn_flag = TRUE ;
411 /*
412 * If one of the upstream stations beaconed
413 * and the link to the upstream neighbor is
414 * lost we need to restart the stuck timer to
415 * check the "stuck beacon" condition.
416 */
417 start_rmt_timer1(smc,smc->s.rmt_t_stuck,
418 RM_TIMEOUT_T_STUCK) ;
419 }
420 /*
421 * We do NOT need to clear smc->r.bn_flag in case of
422 * not being in state T4 or T5, because the flag
423 * must be cleared in order to get in this condition.
424 */
425
426 DB_RMTN(2,
427 "RMT : sm_mac_get_tx_state() = %d (bn_flag = %d)\n",
428 tx,smc->r.bn_flag) ;
429 }
430 /*RM44c*/
431 else if (cmd == RM_TIMEOUT_ANNOUNCE && !smc->r.bn_flag) {
432 rmt_dup_actions(smc) ;
433 }
434 /*RM45*/
435 else if (cmd == RM_RING_OP) {
436 smc->r.no_flag = FALSE ;
437 GO_STATE(RM5_RING_OP_DUP) ;
438 break ;
439 }
440 /*RM46*/
441 else if (cmd == RM_TIMEOUT_T_STUCK &&
442 smc->r.rm_join && smc->r.bn_flag) {
443 GO_STATE(RM6_DIRECTED) ;
444 break ;
445 }
446 break ;
447 case ACTIONS(RM5_RING_OP_DUP) :
448 stop_rmt_timer0(smc) ;
449 stop_rmt_timer1(smc) ;
450 stop_rmt_timer2(smc) ;
451 DB_RMTN(1,"RMT : RM5_RING_OP_DUP\n",0,0) ;
452 ACTIONS_DONE() ;
453 break;
454 case RM5_RING_OP_DUP :
455 /*RM52*/
456 if (smc->r.dup_addr_test == DA_PASSED) {
457 smc->r.da_flag = FALSE ;
458 GO_STATE(RM2_RING_OP) ;
459 break ;
460 }
461 /*RM54*/
462 else if (cmd == RM_RING_NON_OP) {
463 smc->r.jm_flag = FALSE ;
464 smc->r.bn_flag = FALSE ;
465 GO_STATE(RM4_NON_OP_DUP) ;
466 break ;
467 }
468 break ;
469 case ACTIONS(RM6_DIRECTED) :
470 start_rmt_timer0(smc,smc->s.rmt_t_direct,RM_TIMEOUT_T_DIRECT) ;
471 stop_rmt_timer1(smc) ;
472 start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL) ;
473 sm_ma_control(smc,MA_DIRECTED) ;
474 RS_SET(smc,RS_BEACON) ;
475 DB_RMTN(1,"RMT : RM6_DIRECTED\n",0,0) ;
476 ACTIONS_DONE() ;
477 break ;
478 case RM6_DIRECTED :
479 /*RM63*/
480 if (cmd == RM_TIMEOUT_POLL) {
481 start_rmt_timer2(smc,smc->s.rmt_t_poll,RM_TIMEOUT_POLL);
482 sm_mac_check_beacon_claim(smc) ;
483#ifndef SUPERNET_3
484 /* Because of problems with the Supernet II chip set
485 * sending of Directed Beacon will stop after 165ms
486 * therefore restart_trt_for_dbcn(smc) will be called
487 * to prevent this.
488 */
489 restart_trt_for_dbcn(smc) ;
490#endif /*SUPERNET_3*/
491 break ;
492 }
493 if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON) &&
494 !smc->r.da_flag) {
495 smc->r.bn_flag = FALSE ;
496 GO_STATE(RM3_DETECT) ;
497 break ;
498 }
499 /*RM64*/
500 else if ((cmd == RM_MY_BEACON || cmd == RM_OTHER_BEACON) &&
501 smc->r.da_flag) {
502 smc->r.bn_flag = FALSE ;
503 GO_STATE(RM4_NON_OP_DUP) ;
504 break ;
505 }
506 /*RM67*/
507 else if (cmd == RM_TIMEOUT_T_DIRECT) {
508 GO_STATE(RM7_TRACE) ;
509 break ;
510 }
511 break ;
512 case ACTIONS(RM7_TRACE) :
513 stop_rmt_timer0(smc) ;
514 stop_rmt_timer1(smc) ;
515 stop_rmt_timer2(smc) ;
516 smc->e.trace_prop |= ENTITY_BIT(ENTITY_MAC) ;
517 queue_event(smc,EVENT_ECM,EC_TRACE_PROP) ;
518 DB_RMTN(1,"RMT : RM7_TRACE\n",0,0) ;
519 ACTIONS_DONE() ;
520 break ;
521 case RM7_TRACE :
522 break ;
523 default:
524 SMT_PANIC(smc,SMT_E0122, SMT_E0122_MSG) ;
525 break;
526 }
527}
528
529/*
530 * (jd) RMT duplicate address actions
531 * leave the ring or reinsert just as configured
532 */
533static void rmt_dup_actions(struct s_smc *smc)
534{
535 if (smc->r.jm_flag) {
536 }
537 else {
538 if (smc->s.rmt_dup_mac_behavior) {
539 SMT_ERR_LOG(smc,SMT_E0138, SMT_E0138_MSG) ;
540 rmt_reinsert_actions(smc) ;
541 }
542 else {
543 SMT_ERR_LOG(smc,SMT_E0135, SMT_E0135_MSG) ;
544 rmt_leave_actions(smc) ;
545 }
546 }
547}
548
549/*
550 * Reconnect to the Ring
551 */
552static void rmt_reinsert_actions(struct s_smc *smc)
553{
554 queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
555 queue_event(smc,EVENT_ECM,EC_CONNECT) ;
556}
557
558/*
559 * duplicate address detected
560 */
561static void rmt_new_dup_actions(struct s_smc *smc)
562{
563 smc->r.da_flag = TRUE ;
564 smc->r.bn_flag = FALSE ;
565 smc->r.jm_flag = FALSE ;
566 /*
567 * we have three options : change address, jam or leave
568 * we leave the ring as default
569 * Optionally it's possible to reinsert after leaving the Ring
570 * but this will not conform with SMT Spec.
571 */
572 if (smc->s.rmt_dup_mac_behavior) {
573 SMT_ERR_LOG(smc,SMT_E0138, SMT_E0138_MSG) ;
574 rmt_reinsert_actions(smc) ;
575 }
576 else {
577 SMT_ERR_LOG(smc,SMT_E0135, SMT_E0135_MSG) ;
578 rmt_leave_actions(smc) ;
579 }
580}
581
582
583/*
584 * leave the ring
585 */
586static void rmt_leave_actions(struct s_smc *smc)
587{
588 queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
589 /*
590 * Note: Do NOT try again later. (with please reconnect)
591 * The station must be left from the ring!
592 */
593}
594
595/*
596 * SMT timer interface
597 * start RMT timer 0
598 */
599static void start_rmt_timer0(struct s_smc *smc, u_long value, int event)
600{
601 smc->r.timer0_exp = FALSE ; /* clear timer event flag */
602 smt_timer_start(smc,&smc->r.rmt_timer0,value,EV_TOKEN(EVENT_RMT,event));
603}
604
605/*
606 * SMT timer interface
607 * start RMT timer 1
608 */
609static void start_rmt_timer1(struct s_smc *smc, u_long value, int event)
610{
611 smc->r.timer1_exp = FALSE ; /* clear timer event flag */
612 smt_timer_start(smc,&smc->r.rmt_timer1,value,EV_TOKEN(EVENT_RMT,event));
613}
614
615/*
616 * SMT timer interface
617 * start RMT timer 2
618 */
619static void start_rmt_timer2(struct s_smc *smc, u_long value, int event)
620{
621 smc->r.timer2_exp = FALSE ; /* clear timer event flag */
622 smt_timer_start(smc,&smc->r.rmt_timer2,value,EV_TOKEN(EVENT_RMT,event));
623}
624
625/*
626 * SMT timer interface
627 * stop RMT timer 0
628 */
629static void stop_rmt_timer0(struct s_smc *smc)
630{
631 if (smc->r.rmt_timer0.tm_active)
632 smt_timer_stop(smc,&smc->r.rmt_timer0) ;
633}
634
635/*
636 * SMT timer interface
637 * stop RMT timer 1
638 */
639static void stop_rmt_timer1(struct s_smc *smc)
640{
641 if (smc->r.rmt_timer1.tm_active)
642 smt_timer_stop(smc,&smc->r.rmt_timer1) ;
643}
644
645/*
646 * SMT timer interface
647 * stop RMT timer 2
648 */
649static void stop_rmt_timer2(struct s_smc *smc)
650{
651 if (smc->r.rmt_timer2.tm_active)
652 smt_timer_stop(smc,&smc->r.rmt_timer2) ;
653}
654
diff --git a/drivers/net/skfp/skfddi.c b/drivers/net/skfp/skfddi.c
deleted file mode 100644
index 3d9a4596a423..000000000000
--- a/drivers/net/skfp/skfddi.c
+++ /dev/null
@@ -1,2260 +0,0 @@
1/*
2 * File Name:
3 * skfddi.c
4 *
5 * Copyright Information:
6 * Copyright SysKonnect 1998,1999.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 * Abstract:
16 * A Linux device driver supporting the SysKonnect FDDI PCI controller
17 * familie.
18 *
19 * Maintainers:
20 * CG Christoph Goos (cgoos@syskonnect.de)
21 *
22 * Contributors:
23 * DM David S. Miller
24 *
25 * Address all question to:
26 * linux@syskonnect.de
27 *
28 * The technical manual for the adapters is available from SysKonnect's
29 * web pages: www.syskonnect.com
30 * Goto "Support" and search Knowledge Base for "manual".
31 *
32 * Driver Architecture:
33 * The driver architecture is based on the DEC FDDI driver by
34 * Lawrence V. Stefani and several ethernet drivers.
35 * I also used an existing Windows NT miniport driver.
36 * All hardware dependent functions are handled by the SysKonnect
37 * Hardware Module.
38 * The only headerfiles that are directly related to this source
39 * are skfddi.c, h/types.h, h/osdef1st.h, h/targetos.h.
40 * The others belong to the SysKonnect FDDI Hardware Module and
41 * should better not be changed.
42 *
43 * Modification History:
44 * Date Name Description
45 * 02-Mar-98 CG Created.
46 *
47 * 10-Mar-99 CG Support for 2.2.x added.
48 * 25-Mar-99 CG Corrected IRQ routing for SMP (APIC)
49 * 26-Oct-99 CG Fixed compilation error on 2.2.13
50 * 12-Nov-99 CG Source code release
51 * 22-Nov-99 CG Included in kernel source.
52 * 07-May-00 DM 64 bit fixes, new dma interface
53 * 31-Jul-03 DB Audit copy_*_user in skfp_ioctl
54 * Daniele Bellucci <bellucda@tiscali.it>
55 * 03-Dec-03 SH Convert to PCI device model
56 *
57 * Compilation options (-Dxxx):
58 * DRIVERDEBUG print lots of messages to log file
59 * DUMPPACKETS print received/transmitted packets to logfile
60 *
61 * Tested cpu architectures:
62 * - i386
63 * - sparc64
64 */
65
66/* Version information string - should be updated prior to */
67/* each new release!!! */
68#define VERSION "2.07"
69
70static const char * const boot_msg =
71 "SysKonnect FDDI PCI Adapter driver v" VERSION " for\n"
72 " SK-55xx/SK-58xx adapters (SK-NET FDDI-FP/UP/LP)";
73
74/* Include files */
75
76#include <linux/capability.h>
77#include <linux/module.h>
78#include <linux/kernel.h>
79#include <linux/errno.h>
80#include <linux/ioport.h>
81#include <linux/interrupt.h>
82#include <linux/pci.h>
83#include <linux/netdevice.h>
84#include <linux/fddidevice.h>
85#include <linux/skbuff.h>
86#include <linux/bitops.h>
87#include <linux/gfp.h>
88
89#include <asm/byteorder.h>
90#include <asm/io.h>
91#include <asm/uaccess.h>
92
93#include "h/types.h"
94#undef ADDR // undo Linux definition
95#include "h/skfbi.h"
96#include "h/fddi.h"
97#include "h/smc.h"
98#include "h/smtstate.h"
99
100
101// Define module-wide (static) routines
102static int skfp_driver_init(struct net_device *dev);
103static int skfp_open(struct net_device *dev);
104static int skfp_close(struct net_device *dev);
105static irqreturn_t skfp_interrupt(int irq, void *dev_id);
106static struct net_device_stats *skfp_ctl_get_stats(struct net_device *dev);
107static void skfp_ctl_set_multicast_list(struct net_device *dev);
108static void skfp_ctl_set_multicast_list_wo_lock(struct net_device *dev);
109static int skfp_ctl_set_mac_address(struct net_device *dev, void *addr);
110static int skfp_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
111static netdev_tx_t skfp_send_pkt(struct sk_buff *skb,
112 struct net_device *dev);
113static void send_queued_packets(struct s_smc *smc);
114static void CheckSourceAddress(unsigned char *frame, unsigned char *hw_addr);
115static void ResetAdapter(struct s_smc *smc);
116
117
118// Functions needed by the hardware module
119void *mac_drv_get_space(struct s_smc *smc, u_int size);
120void *mac_drv_get_desc_mem(struct s_smc *smc, u_int size);
121unsigned long mac_drv_virt2phys(struct s_smc *smc, void *virt);
122unsigned long dma_master(struct s_smc *smc, void *virt, int len, int flag);
123void dma_complete(struct s_smc *smc, volatile union s_fp_descr *descr,
124 int flag);
125void mac_drv_tx_complete(struct s_smc *smc, volatile struct s_smt_fp_txd *txd);
126void llc_restart_tx(struct s_smc *smc);
127void mac_drv_rx_complete(struct s_smc *smc, volatile struct s_smt_fp_rxd *rxd,
128 int frag_count, int len);
129void mac_drv_requeue_rxd(struct s_smc *smc, volatile struct s_smt_fp_rxd *rxd,
130 int frag_count);
131void mac_drv_fill_rxd(struct s_smc *smc);
132void mac_drv_clear_rxd(struct s_smc *smc, volatile struct s_smt_fp_rxd *rxd,
133 int frag_count);
134int mac_drv_rx_init(struct s_smc *smc, int len, int fc, char *look_ahead,
135 int la_len);
136void dump_data(unsigned char *Data, int length);
137
138// External functions from the hardware module
139extern u_int mac_drv_check_space(void);
140extern int mac_drv_init(struct s_smc *smc);
141extern void hwm_tx_frag(struct s_smc *smc, char far * virt, u_long phys,
142 int len, int frame_status);
143extern int hwm_tx_init(struct s_smc *smc, u_char fc, int frag_count,
144 int frame_len, int frame_status);
145extern void fddi_isr(struct s_smc *smc);
146extern void hwm_rx_frag(struct s_smc *smc, char far * virt, u_long phys,
147 int len, int frame_status);
148extern void mac_drv_rx_mode(struct s_smc *smc, int mode);
149extern void mac_drv_clear_rx_queue(struct s_smc *smc);
150extern void enable_tx_irq(struct s_smc *smc, u_short queue);
151
152static DEFINE_PCI_DEVICE_TABLE(skfddi_pci_tbl) = {
153 { PCI_VENDOR_ID_SK, PCI_DEVICE_ID_SK_FP, PCI_ANY_ID, PCI_ANY_ID, },
154 { } /* Terminating entry */
155};
156MODULE_DEVICE_TABLE(pci, skfddi_pci_tbl);
157MODULE_LICENSE("GPL");
158MODULE_AUTHOR("Mirko Lindner <mlindner@syskonnect.de>");
159
160// Define module-wide (static) variables
161
162static int num_boards; /* total number of adapters configured */
163
164static const struct net_device_ops skfp_netdev_ops = {
165 .ndo_open = skfp_open,
166 .ndo_stop = skfp_close,
167 .ndo_start_xmit = skfp_send_pkt,
168 .ndo_get_stats = skfp_ctl_get_stats,
169 .ndo_change_mtu = fddi_change_mtu,
170 .ndo_set_rx_mode = skfp_ctl_set_multicast_list,
171 .ndo_set_mac_address = skfp_ctl_set_mac_address,
172 .ndo_do_ioctl = skfp_ioctl,
173};
174
175/*
176 * =================
177 * = skfp_init_one =
178 * =================
179 *
180 * Overview:
181 * Probes for supported FDDI PCI controllers
182 *
183 * Returns:
184 * Condition code
185 *
186 * Arguments:
187 * pdev - pointer to PCI device information
188 *
189 * Functional Description:
190 * This is now called by PCI driver registration process
191 * for each board found.
192 *
193 * Return Codes:
194 * 0 - This device (fddi0, fddi1, etc) configured successfully
195 * -ENODEV - No devices present, or no SysKonnect FDDI PCI device
196 * present for this device name
197 *
198 *
199 * Side Effects:
200 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
201 * initialized and the board resources are read and stored in
202 * the device structure.
203 */
204static int skfp_init_one(struct pci_dev *pdev,
205 const struct pci_device_id *ent)
206{
207 struct net_device *dev;
208 struct s_smc *smc; /* board pointer */
209 void __iomem *mem;
210 int err;
211
212 pr_debug("entering skfp_init_one\n");
213
214 if (num_boards == 0)
215 printk("%s\n", boot_msg);
216
217 err = pci_enable_device(pdev);
218 if (err)
219 return err;
220
221 err = pci_request_regions(pdev, "skfddi");
222 if (err)
223 goto err_out1;
224
225 pci_set_master(pdev);
226
227#ifdef MEM_MAPPED_IO
228 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
229 printk(KERN_ERR "skfp: region is not an MMIO resource\n");
230 err = -EIO;
231 goto err_out2;
232 }
233
234 mem = ioremap(pci_resource_start(pdev, 0), 0x4000);
235#else
236 if (!(pci_resource_flags(pdev, 1) & IO_RESOURCE_IO)) {
237 printk(KERN_ERR "skfp: region is not PIO resource\n");
238 err = -EIO;
239 goto err_out2;
240 }
241
242 mem = ioport_map(pci_resource_start(pdev, 1), FP_IO_LEN);
243#endif
244 if (!mem) {
245 printk(KERN_ERR "skfp: Unable to map register, "
246 "FDDI adapter will be disabled.\n");
247 err = -EIO;
248 goto err_out2;
249 }
250
251 dev = alloc_fddidev(sizeof(struct s_smc));
252 if (!dev) {
253 printk(KERN_ERR "skfp: Unable to allocate fddi device, "
254 "FDDI adapter will be disabled.\n");
255 err = -ENOMEM;
256 goto err_out3;
257 }
258
259 dev->irq = pdev->irq;
260 dev->netdev_ops = &skfp_netdev_ops;
261
262 SET_NETDEV_DEV(dev, &pdev->dev);
263
264 /* Initialize board structure with bus-specific info */
265 smc = netdev_priv(dev);
266 smc->os.dev = dev;
267 smc->os.bus_type = SK_BUS_TYPE_PCI;
268 smc->os.pdev = *pdev;
269 smc->os.QueueSkb = MAX_TX_QUEUE_LEN;
270 smc->os.MaxFrameSize = MAX_FRAME_SIZE;
271 smc->os.dev = dev;
272 smc->hw.slot = -1;
273 smc->hw.iop = mem;
274 smc->os.ResetRequested = FALSE;
275 skb_queue_head_init(&smc->os.SendSkbQueue);
276
277 dev->base_addr = (unsigned long)mem;
278
279 err = skfp_driver_init(dev);
280 if (err)
281 goto err_out4;
282
283 err = register_netdev(dev);
284 if (err)
285 goto err_out5;
286
287 ++num_boards;
288 pci_set_drvdata(pdev, dev);
289
290 if ((pdev->subsystem_device & 0xff00) == 0x5500 ||
291 (pdev->subsystem_device & 0xff00) == 0x5800)
292 printk("%s: SysKonnect FDDI PCI adapter"
293 " found (SK-%04X)\n", dev->name,
294 pdev->subsystem_device);
295 else
296 printk("%s: FDDI PCI adapter found\n", dev->name);
297
298 return 0;
299err_out5:
300 if (smc->os.SharedMemAddr)
301 pci_free_consistent(pdev, smc->os.SharedMemSize,
302 smc->os.SharedMemAddr,
303 smc->os.SharedMemDMA);
304 pci_free_consistent(pdev, MAX_FRAME_SIZE,
305 smc->os.LocalRxBuffer, smc->os.LocalRxBufferDMA);
306err_out4:
307 free_netdev(dev);
308err_out3:
309#ifdef MEM_MAPPED_IO
310 iounmap(mem);
311#else
312 ioport_unmap(mem);
313#endif
314err_out2:
315 pci_release_regions(pdev);
316err_out1:
317 pci_disable_device(pdev);
318 return err;
319}
320
321/*
322 * Called for each adapter board from pci_unregister_driver
323 */
324static void __devexit skfp_remove_one(struct pci_dev *pdev)
325{
326 struct net_device *p = pci_get_drvdata(pdev);
327 struct s_smc *lp = netdev_priv(p);
328
329 unregister_netdev(p);
330
331 if (lp->os.SharedMemAddr) {
332 pci_free_consistent(&lp->os.pdev,
333 lp->os.SharedMemSize,
334 lp->os.SharedMemAddr,
335 lp->os.SharedMemDMA);
336 lp->os.SharedMemAddr = NULL;
337 }
338 if (lp->os.LocalRxBuffer) {
339 pci_free_consistent(&lp->os.pdev,
340 MAX_FRAME_SIZE,
341 lp->os.LocalRxBuffer,
342 lp->os.LocalRxBufferDMA);
343 lp->os.LocalRxBuffer = NULL;
344 }
345#ifdef MEM_MAPPED_IO
346 iounmap(lp->hw.iop);
347#else
348 ioport_unmap(lp->hw.iop);
349#endif
350 pci_release_regions(pdev);
351 free_netdev(p);
352
353 pci_disable_device(pdev);
354 pci_set_drvdata(pdev, NULL);
355}
356
357/*
358 * ====================
359 * = skfp_driver_init =
360 * ====================
361 *
362 * Overview:
363 * Initializes remaining adapter board structure information
364 * and makes sure adapter is in a safe state prior to skfp_open().
365 *
366 * Returns:
367 * Condition code
368 *
369 * Arguments:
370 * dev - pointer to device information
371 *
372 * Functional Description:
373 * This function allocates additional resources such as the host memory
374 * blocks needed by the adapter.
375 * The adapter is also reset. The OS must call skfp_open() to open
376 * the adapter and bring it on-line.
377 *
378 * Return Codes:
379 * 0 - initialization succeeded
380 * -1 - initialization failed
381 */
382static int skfp_driver_init(struct net_device *dev)
383{
384 struct s_smc *smc = netdev_priv(dev);
385 skfddi_priv *bp = &smc->os;
386 int err = -EIO;
387
388 pr_debug("entering skfp_driver_init\n");
389
390 // set the io address in private structures
391 bp->base_addr = dev->base_addr;
392
393 // Get the interrupt level from the PCI Configuration Table
394 smc->hw.irq = dev->irq;
395
396 spin_lock_init(&bp->DriverLock);
397
398 // Allocate invalid frame
399 bp->LocalRxBuffer = pci_alloc_consistent(&bp->pdev, MAX_FRAME_SIZE, &bp->LocalRxBufferDMA);
400 if (!bp->LocalRxBuffer) {
401 printk("could not allocate mem for ");
402 printk("LocalRxBuffer: %d byte\n", MAX_FRAME_SIZE);
403 goto fail;
404 }
405
406 // Determine the required size of the 'shared' memory area.
407 bp->SharedMemSize = mac_drv_check_space();
408 pr_debug("Memory for HWM: %ld\n", bp->SharedMemSize);
409 if (bp->SharedMemSize > 0) {
410 bp->SharedMemSize += 16; // for descriptor alignment
411
412 bp->SharedMemAddr = pci_alloc_consistent(&bp->pdev,
413 bp->SharedMemSize,
414 &bp->SharedMemDMA);
415 if (!bp->SharedMemAddr) {
416 printk("could not allocate mem for ");
417 printk("hardware module: %ld byte\n",
418 bp->SharedMemSize);
419 goto fail;
420 }
421 bp->SharedMemHeap = 0; // Nothing used yet.
422
423 } else {
424 bp->SharedMemAddr = NULL;
425 bp->SharedMemHeap = 0;
426 } // SharedMemSize > 0
427
428 memset(bp->SharedMemAddr, 0, bp->SharedMemSize);
429
430 card_stop(smc); // Reset adapter.
431
432 pr_debug("mac_drv_init()..\n");
433 if (mac_drv_init(smc) != 0) {
434 pr_debug("mac_drv_init() failed\n");
435 goto fail;
436 }
437 read_address(smc, NULL);
438 pr_debug("HW-Addr: %pMF\n", smc->hw.fddi_canon_addr.a);
439 memcpy(dev->dev_addr, smc->hw.fddi_canon_addr.a, 6);
440
441 smt_reset_defaults(smc, 0);
442
443 return 0;
444
445fail:
446 if (bp->SharedMemAddr) {
447 pci_free_consistent(&bp->pdev,
448 bp->SharedMemSize,
449 bp->SharedMemAddr,
450 bp->SharedMemDMA);
451 bp->SharedMemAddr = NULL;
452 }
453 if (bp->LocalRxBuffer) {
454 pci_free_consistent(&bp->pdev, MAX_FRAME_SIZE,
455 bp->LocalRxBuffer, bp->LocalRxBufferDMA);
456 bp->LocalRxBuffer = NULL;
457 }
458 return err;
459} // skfp_driver_init
460
461
462/*
463 * =============
464 * = skfp_open =
465 * =============
466 *
467 * Overview:
468 * Opens the adapter
469 *
470 * Returns:
471 * Condition code
472 *
473 * Arguments:
474 * dev - pointer to device information
475 *
476 * Functional Description:
477 * This function brings the adapter to an operational state.
478 *
479 * Return Codes:
480 * 0 - Adapter was successfully opened
481 * -EAGAIN - Could not register IRQ
482 */
483static int skfp_open(struct net_device *dev)
484{
485 struct s_smc *smc = netdev_priv(dev);
486 int err;
487
488 pr_debug("entering skfp_open\n");
489 /* Register IRQ - support shared interrupts by passing device ptr */
490 err = request_irq(dev->irq, skfp_interrupt, IRQF_SHARED,
491 dev->name, dev);
492 if (err)
493 return err;
494
495 /*
496 * Set current address to factory MAC address
497 *
498 * Note: We've already done this step in skfp_driver_init.
499 * However, it's possible that a user has set a node
500 * address override, then closed and reopened the
501 * adapter. Unless we reset the device address field
502 * now, we'll continue to use the existing modified
503 * address.
504 */
505 read_address(smc, NULL);
506 memcpy(dev->dev_addr, smc->hw.fddi_canon_addr.a, 6);
507
508 init_smt(smc, NULL);
509 smt_online(smc, 1);
510 STI_FBI();
511
512 /* Clear local multicast address tables */
513 mac_clear_multicast(smc);
514
515 /* Disable promiscuous filter settings */
516 mac_drv_rx_mode(smc, RX_DISABLE_PROMISC);
517
518 netif_start_queue(dev);
519 return 0;
520} // skfp_open
521
522
523/*
524 * ==============
525 * = skfp_close =
526 * ==============
527 *
528 * Overview:
529 * Closes the device/module.
530 *
531 * Returns:
532 * Condition code
533 *
534 * Arguments:
535 * dev - pointer to device information
536 *
537 * Functional Description:
538 * This routine closes the adapter and brings it to a safe state.
539 * The interrupt service routine is deregistered with the OS.
540 * The adapter can be opened again with another call to skfp_open().
541 *
542 * Return Codes:
543 * Always return 0.
544 *
545 * Assumptions:
546 * No further requests for this adapter are made after this routine is
547 * called. skfp_open() can be called to reset and reinitialize the
548 * adapter.
549 */
550static int skfp_close(struct net_device *dev)
551{
552 struct s_smc *smc = netdev_priv(dev);
553 skfddi_priv *bp = &smc->os;
554
555 CLI_FBI();
556 smt_reset_defaults(smc, 1);
557 card_stop(smc);
558 mac_drv_clear_tx_queue(smc);
559 mac_drv_clear_rx_queue(smc);
560
561 netif_stop_queue(dev);
562 /* Deregister (free) IRQ */
563 free_irq(dev->irq, dev);
564
565 skb_queue_purge(&bp->SendSkbQueue);
566 bp->QueueSkb = MAX_TX_QUEUE_LEN;
567
568 return 0;
569} // skfp_close
570
571
572/*
573 * ==================
574 * = skfp_interrupt =
575 * ==================
576 *
577 * Overview:
578 * Interrupt processing routine
579 *
580 * Returns:
581 * None
582 *
583 * Arguments:
584 * irq - interrupt vector
585 * dev_id - pointer to device information
586 *
587 * Functional Description:
588 * This routine calls the interrupt processing routine for this adapter. It
589 * disables and reenables adapter interrupts, as appropriate. We can support
590 * shared interrupts since the incoming dev_id pointer provides our device
591 * structure context. All the real work is done in the hardware module.
592 *
593 * Return Codes:
594 * None
595 *
596 * Assumptions:
597 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
598 * on Intel-based systems) is done by the operating system outside this
599 * routine.
600 *
601 * System interrupts are enabled through this call.
602 *
603 * Side Effects:
604 * Interrupts are disabled, then reenabled at the adapter.
605 */
606
607static irqreturn_t skfp_interrupt(int irq, void *dev_id)
608{
609 struct net_device *dev = dev_id;
610 struct s_smc *smc; /* private board structure pointer */
611 skfddi_priv *bp;
612
613 smc = netdev_priv(dev);
614 bp = &smc->os;
615
616 // IRQs enabled or disabled ?
617 if (inpd(ADDR(B0_IMSK)) == 0) {
618 // IRQs are disabled: must be shared interrupt
619 return IRQ_NONE;
620 }
621 // Note: At this point, IRQs are enabled.
622 if ((inpd(ISR_A) & smc->hw.is_imask) == 0) { // IRQ?
623 // Adapter did not issue an IRQ: must be shared interrupt
624 return IRQ_NONE;
625 }
626 CLI_FBI(); // Disable IRQs from our adapter.
627 spin_lock(&bp->DriverLock);
628
629 // Call interrupt handler in hardware module (HWM).
630 fddi_isr(smc);
631
632 if (smc->os.ResetRequested) {
633 ResetAdapter(smc);
634 smc->os.ResetRequested = FALSE;
635 }
636 spin_unlock(&bp->DriverLock);
637 STI_FBI(); // Enable IRQs from our adapter.
638
639 return IRQ_HANDLED;
640} // skfp_interrupt
641
642
643/*
644 * ======================
645 * = skfp_ctl_get_stats =
646 * ======================
647 *
648 * Overview:
649 * Get statistics for FDDI adapter
650 *
651 * Returns:
652 * Pointer to FDDI statistics structure
653 *
654 * Arguments:
655 * dev - pointer to device information
656 *
657 * Functional Description:
658 * Gets current MIB objects from adapter, then
659 * returns FDDI statistics structure as defined
660 * in if_fddi.h.
661 *
662 * Note: Since the FDDI statistics structure is
663 * still new and the device structure doesn't
664 * have an FDDI-specific get statistics handler,
665 * we'll return the FDDI statistics structure as
666 * a pointer to an Ethernet statistics structure.
667 * That way, at least the first part of the statistics
668 * structure can be decoded properly.
669 * We'll have to pay attention to this routine as the
670 * device structure becomes more mature and LAN media
671 * independent.
672 *
673 */
674static struct net_device_stats *skfp_ctl_get_stats(struct net_device *dev)
675{
676 struct s_smc *bp = netdev_priv(dev);
677
678 /* Fill the bp->stats structure with driver-maintained counters */
679
680 bp->os.MacStat.port_bs_flag[0] = 0x1234;
681 bp->os.MacStat.port_bs_flag[1] = 0x5678;
682// goos: need to fill out fddi statistic
683#if 0
684 /* Get FDDI SMT MIB objects */
685
686/* Fill the bp->stats structure with the SMT MIB object values */
687
688 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
689 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
690 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
691 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
692 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
693 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
694 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
695 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
696 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
697 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
698 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
699 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
700 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
701 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
702 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
703 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
704 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
705 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
706 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
707 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
708 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
709 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
710 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
711 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
712 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
713 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
714 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
715 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
716 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
717 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
718 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
719 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
720 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
721 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
722 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
723 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
724 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
725 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
726 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
727 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
728 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
729 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
730 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
731 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
732 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
733 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
734 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
735 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
736 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
737 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
738 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
739 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
740 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
741 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
742 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
743 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
744 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
745 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
746 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
747 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
748 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
749 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
750 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
751 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
752 memcpy(&bp->stats.port_requested_paths[0 * 3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
753 memcpy(&bp->stats.port_requested_paths[1 * 3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
754 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
755 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
756 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
757 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
758 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
759 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
760 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
761 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
762 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
763 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
764 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
765 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
766 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
767 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
768 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
769 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
770 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
771 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
772 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
773 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
774 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
775 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
776 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
777 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
778 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
779 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
780
781
782 /* Fill the bp->stats structure with the FDDI counter values */
783
784 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
785 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
786 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
787 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
788 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
789 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
790 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
791 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
792 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
793 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
794 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
795
796#endif
797 return (struct net_device_stats *)&bp->os.MacStat;
798} // ctl_get_stat
799
800
801/*
802 * ==============================
803 * = skfp_ctl_set_multicast_list =
804 * ==============================
805 *
806 * Overview:
807 * Enable/Disable LLC frame promiscuous mode reception
808 * on the adapter and/or update multicast address table.
809 *
810 * Returns:
811 * None
812 *
813 * Arguments:
814 * dev - pointer to device information
815 *
816 * Functional Description:
817 * This function acquires the driver lock and only calls
818 * skfp_ctl_set_multicast_list_wo_lock then.
819 * This routine follows a fairly simple algorithm for setting the
820 * adapter filters and CAM:
821 *
822 * if IFF_PROMISC flag is set
823 * enable promiscuous mode
824 * else
825 * disable promiscuous mode
826 * if number of multicast addresses <= max. multicast number
827 * add mc addresses to adapter table
828 * else
829 * enable promiscuous mode
830 * update adapter filters
831 *
832 * Assumptions:
833 * Multicast addresses are presented in canonical (LSB) format.
834 *
835 * Side Effects:
836 * On-board adapter filters are updated.
837 */
838static void skfp_ctl_set_multicast_list(struct net_device *dev)
839{
840 struct s_smc *smc = netdev_priv(dev);
841 skfddi_priv *bp = &smc->os;
842 unsigned long Flags;
843
844 spin_lock_irqsave(&bp->DriverLock, Flags);
845 skfp_ctl_set_multicast_list_wo_lock(dev);
846 spin_unlock_irqrestore(&bp->DriverLock, Flags);
847} // skfp_ctl_set_multicast_list
848
849
850
851static void skfp_ctl_set_multicast_list_wo_lock(struct net_device *dev)
852{
853 struct s_smc *smc = netdev_priv(dev);
854 struct netdev_hw_addr *ha;
855
856 /* Enable promiscuous mode, if necessary */
857 if (dev->flags & IFF_PROMISC) {
858 mac_drv_rx_mode(smc, RX_ENABLE_PROMISC);
859 pr_debug("PROMISCUOUS MODE ENABLED\n");
860 }
861 /* Else, update multicast address table */
862 else {
863 mac_drv_rx_mode(smc, RX_DISABLE_PROMISC);
864 pr_debug("PROMISCUOUS MODE DISABLED\n");
865
866 // Reset all MC addresses
867 mac_clear_multicast(smc);
868 mac_drv_rx_mode(smc, RX_DISABLE_ALLMULTI);
869
870 if (dev->flags & IFF_ALLMULTI) {
871 mac_drv_rx_mode(smc, RX_ENABLE_ALLMULTI);
872 pr_debug("ENABLE ALL MC ADDRESSES\n");
873 } else if (!netdev_mc_empty(dev)) {
874 if (netdev_mc_count(dev) <= FPMAX_MULTICAST) {
875 /* use exact filtering */
876
877 // point to first multicast addr
878 netdev_for_each_mc_addr(ha, dev) {
879 mac_add_multicast(smc,
880 (struct fddi_addr *)ha->addr,
881 1);
882
883 pr_debug("ENABLE MC ADDRESS: %pMF\n",
884 ha->addr);
885 }
886
887 } else { // more MC addresses than HW supports
888
889 mac_drv_rx_mode(smc, RX_ENABLE_ALLMULTI);
890 pr_debug("ENABLE ALL MC ADDRESSES\n");
891 }
892 } else { // no MC addresses
893
894 pr_debug("DISABLE ALL MC ADDRESSES\n");
895 }
896
897 /* Update adapter filters */
898 mac_update_multicast(smc);
899 }
900} // skfp_ctl_set_multicast_list_wo_lock
901
902
903/*
904 * ===========================
905 * = skfp_ctl_set_mac_address =
906 * ===========================
907 *
908 * Overview:
909 * set new mac address on adapter and update dev_addr field in device table.
910 *
911 * Returns:
912 * None
913 *
914 * Arguments:
915 * dev - pointer to device information
916 * addr - pointer to sockaddr structure containing unicast address to set
917 *
918 * Assumptions:
919 * The address pointed to by addr->sa_data is a valid unicast
920 * address and is presented in canonical (LSB) format.
921 */
922static int skfp_ctl_set_mac_address(struct net_device *dev, void *addr)
923{
924 struct s_smc *smc = netdev_priv(dev);
925 struct sockaddr *p_sockaddr = (struct sockaddr *) addr;
926 skfddi_priv *bp = &smc->os;
927 unsigned long Flags;
928
929
930 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN);
931 spin_lock_irqsave(&bp->DriverLock, Flags);
932 ResetAdapter(smc);
933 spin_unlock_irqrestore(&bp->DriverLock, Flags);
934
935 return 0; /* always return zero */
936} // skfp_ctl_set_mac_address
937
938
939/*
940 * ==============
941 * = skfp_ioctl =
942 * ==============
943 *
944 * Overview:
945 *
946 * Perform IOCTL call functions here. Some are privileged operations and the
947 * effective uid is checked in those cases.
948 *
949 * Returns:
950 * status value
951 * 0 - success
952 * other - failure
953 *
954 * Arguments:
955 * dev - pointer to device information
956 * rq - pointer to ioctl request structure
957 * cmd - ?
958 *
959 */
960
961
962static int skfp_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
963{
964 struct s_smc *smc = netdev_priv(dev);
965 skfddi_priv *lp = &smc->os;
966 struct s_skfp_ioctl ioc;
967 int status = 0;
968
969 if (copy_from_user(&ioc, rq->ifr_data, sizeof(struct s_skfp_ioctl)))
970 return -EFAULT;
971
972 switch (ioc.cmd) {
973 case SKFP_GET_STATS: /* Get the driver statistics */
974 ioc.len = sizeof(lp->MacStat);
975 status = copy_to_user(ioc.data, skfp_ctl_get_stats(dev), ioc.len)
976 ? -EFAULT : 0;
977 break;
978 case SKFP_CLR_STATS: /* Zero out the driver statistics */
979 if (!capable(CAP_NET_ADMIN)) {
980 status = -EPERM;
981 } else {
982 memset(&lp->MacStat, 0, sizeof(lp->MacStat));
983 }
984 break;
985 default:
986 printk("ioctl for %s: unknown cmd: %04x\n", dev->name, ioc.cmd);
987 status = -EOPNOTSUPP;
988
989 } // switch
990
991 return status;
992} // skfp_ioctl
993
994
995/*
996 * =====================
997 * = skfp_send_pkt =
998 * =====================
999 *
1000 * Overview:
1001 * Queues a packet for transmission and try to transmit it.
1002 *
1003 * Returns:
1004 * Condition code
1005 *
1006 * Arguments:
1007 * skb - pointer to sk_buff to queue for transmission
1008 * dev - pointer to device information
1009 *
1010 * Functional Description:
1011 * Here we assume that an incoming skb transmit request
1012 * is contained in a single physically contiguous buffer
1013 * in which the virtual address of the start of packet
1014 * (skb->data) can be converted to a physical address
1015 * by using pci_map_single().
1016 *
1017 * We have an internal queue for packets we can not send
1018 * immediately. Packets in this queue can be given to the
1019 * adapter if transmit buffers are freed.
1020 *
1021 * We can't free the skb until after it's been DMA'd
1022 * out by the adapter, so we'll keep it in the driver and
1023 * return it in mac_drv_tx_complete.
1024 *
1025 * Return Codes:
1026 * 0 - driver has queued and/or sent packet
1027 * 1 - caller should requeue the sk_buff for later transmission
1028 *
1029 * Assumptions:
1030 * The entire packet is stored in one physically
1031 * contiguous buffer which is not cached and whose
1032 * 32-bit physical address can be determined.
1033 *
1034 * It's vital that this routine is NOT reentered for the
1035 * same board and that the OS is not in another section of
1036 * code (eg. skfp_interrupt) for the same board on a
1037 * different thread.
1038 *
1039 * Side Effects:
1040 * None
1041 */
1042static netdev_tx_t skfp_send_pkt(struct sk_buff *skb,
1043 struct net_device *dev)
1044{
1045 struct s_smc *smc = netdev_priv(dev);
1046 skfddi_priv *bp = &smc->os;
1047
1048 pr_debug("skfp_send_pkt\n");
1049
1050 /*
1051 * Verify that incoming transmit request is OK
1052 *
1053 * Note: The packet size check is consistent with other
1054 * Linux device drivers, although the correct packet
1055 * size should be verified before calling the
1056 * transmit routine.
1057 */
1058
1059 if (!(skb->len >= FDDI_K_LLC_ZLEN && skb->len <= FDDI_K_LLC_LEN)) {
1060 bp->MacStat.gen.tx_errors++; /* bump error counter */
1061 // dequeue packets from xmt queue and send them
1062 netif_start_queue(dev);
1063 dev_kfree_skb(skb);
1064 return NETDEV_TX_OK; /* return "success" */
1065 }
1066 if (bp->QueueSkb == 0) { // return with tbusy set: queue full
1067
1068 netif_stop_queue(dev);
1069 return NETDEV_TX_BUSY;
1070 }
1071 bp->QueueSkb--;
1072 skb_queue_tail(&bp->SendSkbQueue, skb);
1073 send_queued_packets(netdev_priv(dev));
1074 if (bp->QueueSkb == 0) {
1075 netif_stop_queue(dev);
1076 }
1077 return NETDEV_TX_OK;
1078
1079} // skfp_send_pkt
1080
1081
1082/*
1083 * =======================
1084 * = send_queued_packets =
1085 * =======================
1086 *
1087 * Overview:
1088 * Send packets from the driver queue as long as there are some and
1089 * transmit resources are available.
1090 *
1091 * Returns:
1092 * None
1093 *
1094 * Arguments:
1095 * smc - pointer to smc (adapter) structure
1096 *
1097 * Functional Description:
1098 * Take a packet from queue if there is any. If not, then we are done.
1099 * Check if there are resources to send the packet. If not, requeue it
1100 * and exit.
1101 * Set packet descriptor flags and give packet to adapter.
1102 * Check if any send resources can be freed (we do not use the
1103 * transmit complete interrupt).
1104 */
1105static void send_queued_packets(struct s_smc *smc)
1106{
1107 skfddi_priv *bp = &smc->os;
1108 struct sk_buff *skb;
1109 unsigned char fc;
1110 int queue;
1111 struct s_smt_fp_txd *txd; // Current TxD.
1112 dma_addr_t dma_address;
1113 unsigned long Flags;
1114
1115 int frame_status; // HWM tx frame status.
1116
1117 pr_debug("send queued packets\n");
1118 for (;;) {
1119 // send first buffer from queue
1120 skb = skb_dequeue(&bp->SendSkbQueue);
1121
1122 if (!skb) {
1123 pr_debug("queue empty\n");
1124 return;
1125 } // queue empty !
1126
1127 spin_lock_irqsave(&bp->DriverLock, Flags);
1128 fc = skb->data[0];
1129 queue = (fc & FC_SYNC_BIT) ? QUEUE_S : QUEUE_A0;
1130#ifdef ESS
1131 // Check if the frame may/must be sent as a synchronous frame.
1132
1133 if ((fc & ~(FC_SYNC_BIT | FC_LLC_PRIOR)) == FC_ASYNC_LLC) {
1134 // It's an LLC frame.
1135 if (!smc->ess.sync_bw_available)
1136 fc &= ~FC_SYNC_BIT; // No bandwidth available.
1137
1138 else { // Bandwidth is available.
1139
1140 if (smc->mib.fddiESSSynchTxMode) {
1141 // Send as sync. frame.
1142 fc |= FC_SYNC_BIT;
1143 }
1144 }
1145 }
1146#endif // ESS
1147 frame_status = hwm_tx_init(smc, fc, 1, skb->len, queue);
1148
1149 if ((frame_status & (LOC_TX | LAN_TX)) == 0) {
1150 // Unable to send the frame.
1151
1152 if ((frame_status & RING_DOWN) != 0) {
1153 // Ring is down.
1154 pr_debug("Tx attempt while ring down.\n");
1155 } else if ((frame_status & OUT_OF_TXD) != 0) {
1156 pr_debug("%s: out of TXDs.\n", bp->dev->name);
1157 } else {
1158 pr_debug("%s: out of transmit resources",
1159 bp->dev->name);
1160 }
1161
1162 // Note: We will retry the operation as soon as
1163 // transmit resources become available.
1164 skb_queue_head(&bp->SendSkbQueue, skb);
1165 spin_unlock_irqrestore(&bp->DriverLock, Flags);
1166 return; // Packet has been queued.
1167
1168 } // if (unable to send frame)
1169
1170 bp->QueueSkb++; // one packet less in local queue
1171
1172 // source address in packet ?
1173 CheckSourceAddress(skb->data, smc->hw.fddi_canon_addr.a);
1174
1175 txd = (struct s_smt_fp_txd *) HWM_GET_CURR_TXD(smc, queue);
1176
1177 dma_address = pci_map_single(&bp->pdev, skb->data,
1178 skb->len, PCI_DMA_TODEVICE);
1179 if (frame_status & LAN_TX) {
1180 txd->txd_os.skb = skb; // save skb
1181 txd->txd_os.dma_addr = dma_address; // save dma mapping
1182 }
1183 hwm_tx_frag(smc, skb->data, dma_address, skb->len,
1184 frame_status | FIRST_FRAG | LAST_FRAG | EN_IRQ_EOF);
1185
1186 if (!(frame_status & LAN_TX)) { // local only frame
1187 pci_unmap_single(&bp->pdev, dma_address,
1188 skb->len, PCI_DMA_TODEVICE);
1189 dev_kfree_skb_irq(skb);
1190 }
1191 spin_unlock_irqrestore(&bp->DriverLock, Flags);
1192 } // for
1193
1194 return; // never reached
1195
1196} // send_queued_packets
1197
1198
1199/************************
1200 *
1201 * CheckSourceAddress
1202 *
1203 * Verify if the source address is set. Insert it if necessary.
1204 *
1205 ************************/
1206static void CheckSourceAddress(unsigned char *frame, unsigned char *hw_addr)
1207{
1208 unsigned char SRBit;
1209
1210 if ((((unsigned long) frame[1 + 6]) & ~0x01) != 0) // source routing bit
1211
1212 return;
1213 if ((unsigned short) frame[1 + 10] != 0)
1214 return;
1215 SRBit = frame[1 + 6] & 0x01;
1216 memcpy(&frame[1 + 6], hw_addr, 6);
1217 frame[8] |= SRBit;
1218} // CheckSourceAddress
1219
1220
1221/************************
1222 *
1223 * ResetAdapter
1224 *
1225 * Reset the adapter and bring it back to operational mode.
1226 * Args
1227 * smc - A pointer to the SMT context struct.
1228 * Out
1229 * Nothing.
1230 *
1231 ************************/
1232static void ResetAdapter(struct s_smc *smc)
1233{
1234
1235 pr_debug("[fddi: ResetAdapter]\n");
1236
1237 // Stop the adapter.
1238
1239 card_stop(smc); // Stop all activity.
1240
1241 // Clear the transmit and receive descriptor queues.
1242 mac_drv_clear_tx_queue(smc);
1243 mac_drv_clear_rx_queue(smc);
1244
1245 // Restart the adapter.
1246
1247 smt_reset_defaults(smc, 1); // Initialize the SMT module.
1248
1249 init_smt(smc, (smc->os.dev)->dev_addr); // Initialize the hardware.
1250
1251 smt_online(smc, 1); // Insert into the ring again.
1252 STI_FBI();
1253
1254 // Restore original receive mode (multicasts, promiscuous, etc.).
1255 skfp_ctl_set_multicast_list_wo_lock(smc->os.dev);
1256} // ResetAdapter
1257
1258
1259//--------------- functions called by hardware module ----------------
1260
1261/************************
1262 *
1263 * llc_restart_tx
1264 *
1265 * The hardware driver calls this routine when the transmit complete
1266 * interrupt bits (end of frame) for the synchronous or asynchronous
1267 * queue is set.
1268 *
1269 * NOTE The hardware driver calls this function also if no packets are queued.
1270 * The routine must be able to handle this case.
1271 * Args
1272 * smc - A pointer to the SMT context struct.
1273 * Out
1274 * Nothing.
1275 *
1276 ************************/
1277void llc_restart_tx(struct s_smc *smc)
1278{
1279 skfddi_priv *bp = &smc->os;
1280
1281 pr_debug("[llc_restart_tx]\n");
1282
1283 // Try to send queued packets
1284 spin_unlock(&bp->DriverLock);
1285 send_queued_packets(smc);
1286 spin_lock(&bp->DriverLock);
1287 netif_start_queue(bp->dev);// system may send again if it was blocked
1288
1289} // llc_restart_tx
1290
1291
1292/************************
1293 *
1294 * mac_drv_get_space
1295 *
1296 * The hardware module calls this function to allocate the memory
1297 * for the SMT MBufs if the define MB_OUTSIDE_SMC is specified.
1298 * Args
1299 * smc - A pointer to the SMT context struct.
1300 *
1301 * size - Size of memory in bytes to allocate.
1302 * Out
1303 * != 0 A pointer to the virtual address of the allocated memory.
1304 * == 0 Allocation error.
1305 *
1306 ************************/
1307void *mac_drv_get_space(struct s_smc *smc, unsigned int size)
1308{
1309 void *virt;
1310
1311 pr_debug("mac_drv_get_space (%d bytes), ", size);
1312 virt = (void *) (smc->os.SharedMemAddr + smc->os.SharedMemHeap);
1313
1314 if ((smc->os.SharedMemHeap + size) > smc->os.SharedMemSize) {
1315 printk("Unexpected SMT memory size requested: %d\n", size);
1316 return NULL;
1317 }
1318 smc->os.SharedMemHeap += size; // Move heap pointer.
1319
1320 pr_debug("mac_drv_get_space end\n");
1321 pr_debug("virt addr: %lx\n", (ulong) virt);
1322 pr_debug("bus addr: %lx\n", (ulong)
1323 (smc->os.SharedMemDMA +
1324 ((char *) virt - (char *)smc->os.SharedMemAddr)));
1325 return virt;
1326} // mac_drv_get_space
1327
1328
1329/************************
1330 *
1331 * mac_drv_get_desc_mem
1332 *
1333 * This function is called by the hardware dependent module.
1334 * It allocates the memory for the RxD and TxD descriptors.
1335 *
1336 * This memory must be non-cached, non-movable and non-swappable.
1337 * This memory should start at a physical page boundary.
1338 * Args
1339 * smc - A pointer to the SMT context struct.
1340 *
1341 * size - Size of memory in bytes to allocate.
1342 * Out
1343 * != 0 A pointer to the virtual address of the allocated memory.
1344 * == 0 Allocation error.
1345 *
1346 ************************/
1347void *mac_drv_get_desc_mem(struct s_smc *smc, unsigned int size)
1348{
1349
1350 char *virt;
1351
1352 pr_debug("mac_drv_get_desc_mem\n");
1353
1354 // Descriptor memory must be aligned on 16-byte boundary.
1355
1356 virt = mac_drv_get_space(smc, size);
1357
1358 size = (u_int) (16 - (((unsigned long) virt) & 15UL));
1359 size = size % 16;
1360
1361 pr_debug("Allocate %u bytes alignment gap ", size);
1362 pr_debug("for descriptor memory.\n");
1363
1364 if (!mac_drv_get_space(smc, size)) {
1365 printk("fddi: Unable to align descriptor memory.\n");
1366 return NULL;
1367 }
1368 return virt + size;
1369} // mac_drv_get_desc_mem
1370
1371
1372/************************
1373 *
1374 * mac_drv_virt2phys
1375 *
1376 * Get the physical address of a given virtual address.
1377 * Args
1378 * smc - A pointer to the SMT context struct.
1379 *
1380 * virt - A (virtual) pointer into our 'shared' memory area.
1381 * Out
1382 * Physical address of the given virtual address.
1383 *
1384 ************************/
1385unsigned long mac_drv_virt2phys(struct s_smc *smc, void *virt)
1386{
1387 return smc->os.SharedMemDMA +
1388 ((char *) virt - (char *)smc->os.SharedMemAddr);
1389} // mac_drv_virt2phys
1390
1391
1392/************************
1393 *
1394 * dma_master
1395 *
1396 * The HWM calls this function, when the driver leads through a DMA
1397 * transfer. If the OS-specific module must prepare the system hardware
1398 * for the DMA transfer, it should do it in this function.
1399 *
1400 * The hardware module calls this dma_master if it wants to send an SMT
1401 * frame. This means that the virt address passed in here is part of
1402 * the 'shared' memory area.
1403 * Args
1404 * smc - A pointer to the SMT context struct.
1405 *
1406 * virt - The virtual address of the data.
1407 *
1408 * len - The length in bytes of the data.
1409 *
1410 * flag - Indicates the transmit direction and the buffer type:
1411 * DMA_RD (0x01) system RAM ==> adapter buffer memory
1412 * DMA_WR (0x02) adapter buffer memory ==> system RAM
1413 * SMT_BUF (0x80) SMT buffer
1414 *
1415 * >> NOTE: SMT_BUF and DMA_RD are always set for PCI. <<
1416 * Out
1417 * Returns the pyhsical address for the DMA transfer.
1418 *
1419 ************************/
1420u_long dma_master(struct s_smc * smc, void *virt, int len, int flag)
1421{
1422 return smc->os.SharedMemDMA +
1423 ((char *) virt - (char *)smc->os.SharedMemAddr);
1424} // dma_master
1425
1426
1427/************************
1428 *
1429 * dma_complete
1430 *
1431 * The hardware module calls this routine when it has completed a DMA
1432 * transfer. If the operating system dependent module has set up the DMA
1433 * channel via dma_master() (e.g. Windows NT or AIX) it should clean up
1434 * the DMA channel.
1435 * Args
1436 * smc - A pointer to the SMT context struct.
1437 *
1438 * descr - A pointer to a TxD or RxD, respectively.
1439 *
1440 * flag - Indicates the DMA transfer direction / SMT buffer:
1441 * DMA_RD (0x01) system RAM ==> adapter buffer memory
1442 * DMA_WR (0x02) adapter buffer memory ==> system RAM
1443 * SMT_BUF (0x80) SMT buffer (managed by HWM)
1444 * Out
1445 * Nothing.
1446 *
1447 ************************/
1448void dma_complete(struct s_smc *smc, volatile union s_fp_descr *descr, int flag)
1449{
1450 /* For TX buffers, there are two cases. If it is an SMT transmit
1451 * buffer, there is nothing to do since we use consistent memory
1452 * for the 'shared' memory area. The other case is for normal
1453 * transmit packets given to us by the networking stack, and in
1454 * that case we cleanup the PCI DMA mapping in mac_drv_tx_complete
1455 * below.
1456 *
1457 * For RX buffers, we have to unmap dynamic PCI DMA mappings here
1458 * because the hardware module is about to potentially look at
1459 * the contents of the buffer. If we did not call the PCI DMA
1460 * unmap first, the hardware module could read inconsistent data.
1461 */
1462 if (flag & DMA_WR) {
1463 skfddi_priv *bp = &smc->os;
1464 volatile struct s_smt_fp_rxd *r = &descr->r;
1465
1466 /* If SKB is NULL, we used the local buffer. */
1467 if (r->rxd_os.skb && r->rxd_os.dma_addr) {
1468 int MaxFrameSize = bp->MaxFrameSize;
1469
1470 pci_unmap_single(&bp->pdev, r->rxd_os.dma_addr,
1471 MaxFrameSize, PCI_DMA_FROMDEVICE);
1472 r->rxd_os.dma_addr = 0;
1473 }
1474 }
1475} // dma_complete
1476
1477
1478/************************
1479 *
1480 * mac_drv_tx_complete
1481 *
1482 * Transmit of a packet is complete. Release the tx staging buffer.
1483 *
1484 * Args
1485 * smc - A pointer to the SMT context struct.
1486 *
1487 * txd - A pointer to the last TxD which is used by the frame.
1488 * Out
1489 * Returns nothing.
1490 *
1491 ************************/
1492void mac_drv_tx_complete(struct s_smc *smc, volatile struct s_smt_fp_txd *txd)
1493{
1494 struct sk_buff *skb;
1495
1496 pr_debug("entering mac_drv_tx_complete\n");
1497 // Check if this TxD points to a skb
1498
1499 if (!(skb = txd->txd_os.skb)) {
1500 pr_debug("TXD with no skb assigned.\n");
1501 return;
1502 }
1503 txd->txd_os.skb = NULL;
1504
1505 // release the DMA mapping
1506 pci_unmap_single(&smc->os.pdev, txd->txd_os.dma_addr,
1507 skb->len, PCI_DMA_TODEVICE);
1508 txd->txd_os.dma_addr = 0;
1509
1510 smc->os.MacStat.gen.tx_packets++; // Count transmitted packets.
1511 smc->os.MacStat.gen.tx_bytes+=skb->len; // Count bytes
1512
1513 // free the skb
1514 dev_kfree_skb_irq(skb);
1515
1516 pr_debug("leaving mac_drv_tx_complete\n");
1517} // mac_drv_tx_complete
1518
1519
1520/************************
1521 *
1522 * dump packets to logfile
1523 *
1524 ************************/
1525#ifdef DUMPPACKETS
1526void dump_data(unsigned char *Data, int length)
1527{
1528 int i, j;
1529 unsigned char s[255], sh[10];
1530 if (length > 64) {
1531 length = 64;
1532 }
1533 printk(KERN_INFO "---Packet start---\n");
1534 for (i = 0, j = 0; i < length / 8; i++, j += 8)
1535 printk(KERN_INFO "%02x %02x %02x %02x %02x %02x %02x %02x\n",
1536 Data[j + 0], Data[j + 1], Data[j + 2], Data[j + 3],
1537 Data[j + 4], Data[j + 5], Data[j + 6], Data[j + 7]);
1538 strcpy(s, "");
1539 for (i = 0; i < length % 8; i++) {
1540 sprintf(sh, "%02x ", Data[j + i]);
1541 strcat(s, sh);
1542 }
1543 printk(KERN_INFO "%s\n", s);
1544 printk(KERN_INFO "------------------\n");
1545} // dump_data
1546#else
1547#define dump_data(data,len)
1548#endif // DUMPPACKETS
1549
1550/************************
1551 *
1552 * mac_drv_rx_complete
1553 *
1554 * The hardware module calls this function if an LLC frame is received
1555 * in a receive buffer. Also the SMT, NSA, and directed beacon frames
1556 * from the network will be passed to the LLC layer by this function
1557 * if passing is enabled.
1558 *
1559 * mac_drv_rx_complete forwards the frame to the LLC layer if it should
1560 * be received. It also fills the RxD ring with new receive buffers if
1561 * some can be queued.
1562 * Args
1563 * smc - A pointer to the SMT context struct.
1564 *
1565 * rxd - A pointer to the first RxD which is used by the receive frame.
1566 *
1567 * frag_count - Count of RxDs used by the received frame.
1568 *
1569 * len - Frame length.
1570 * Out
1571 * Nothing.
1572 *
1573 ************************/
1574void mac_drv_rx_complete(struct s_smc *smc, volatile struct s_smt_fp_rxd *rxd,
1575 int frag_count, int len)
1576{
1577 skfddi_priv *bp = &smc->os;
1578 struct sk_buff *skb;
1579 unsigned char *virt, *cp;
1580 unsigned short ri;
1581 u_int RifLength;
1582
1583 pr_debug("entering mac_drv_rx_complete (len=%d)\n", len);
1584 if (frag_count != 1) { // This is not allowed to happen.
1585
1586 printk("fddi: Multi-fragment receive!\n");
1587 goto RequeueRxd; // Re-use the given RXD(s).
1588
1589 }
1590 skb = rxd->rxd_os.skb;
1591 if (!skb) {
1592 pr_debug("No skb in rxd\n");
1593 smc->os.MacStat.gen.rx_errors++;
1594 goto RequeueRxd;
1595 }
1596 virt = skb->data;
1597
1598 // The DMA mapping was released in dma_complete above.
1599
1600 dump_data(skb->data, len);
1601
1602 /*
1603 * FDDI Frame format:
1604 * +-------+-------+-------+------------+--------+------------+
1605 * | FC[1] | DA[6] | SA[6] | RIF[0..18] | LLC[3] | Data[0..n] |
1606 * +-------+-------+-------+------------+--------+------------+
1607 *
1608 * FC = Frame Control
1609 * DA = Destination Address
1610 * SA = Source Address
1611 * RIF = Routing Information Field
1612 * LLC = Logical Link Control
1613 */
1614
1615 // Remove Routing Information Field (RIF), if present.
1616
1617 if ((virt[1 + 6] & FDDI_RII) == 0)
1618 RifLength = 0;
1619 else {
1620 int n;
1621// goos: RIF removal has still to be tested
1622 pr_debug("RIF found\n");
1623 // Get RIF length from Routing Control (RC) field.
1624 cp = virt + FDDI_MAC_HDR_LEN; // Point behind MAC header.
1625
1626 ri = ntohs(*((__be16 *) cp));
1627 RifLength = ri & FDDI_RCF_LEN_MASK;
1628 if (len < (int) (FDDI_MAC_HDR_LEN + RifLength)) {
1629 printk("fddi: Invalid RIF.\n");
1630 goto RequeueRxd; // Discard the frame.
1631
1632 }
1633 virt[1 + 6] &= ~FDDI_RII; // Clear RII bit.
1634 // regions overlap
1635
1636 virt = cp + RifLength;
1637 for (n = FDDI_MAC_HDR_LEN; n; n--)
1638 *--virt = *--cp;
1639 // adjust sbd->data pointer
1640 skb_pull(skb, RifLength);
1641 len -= RifLength;
1642 RifLength = 0;
1643 }
1644
1645 // Count statistics.
1646 smc->os.MacStat.gen.rx_packets++; // Count indicated receive
1647 // packets.
1648 smc->os.MacStat.gen.rx_bytes+=len; // Count bytes.
1649
1650 // virt points to header again
1651 if (virt[1] & 0x01) { // Check group (multicast) bit.
1652
1653 smc->os.MacStat.gen.multicast++;
1654 }
1655
1656 // deliver frame to system
1657 rxd->rxd_os.skb = NULL;
1658 skb_trim(skb, len);
1659 skb->protocol = fddi_type_trans(skb, bp->dev);
1660
1661 netif_rx(skb);
1662
1663 HWM_RX_CHECK(smc, RX_LOW_WATERMARK);
1664 return;
1665
1666 RequeueRxd:
1667 pr_debug("Rx: re-queue RXD.\n");
1668 mac_drv_requeue_rxd(smc, rxd, frag_count);
1669 smc->os.MacStat.gen.rx_errors++; // Count receive packets
1670 // not indicated.
1671
1672} // mac_drv_rx_complete
1673
1674
1675/************************
1676 *
1677 * mac_drv_requeue_rxd
1678 *
1679 * The hardware module calls this function to request the OS-specific
1680 * module to queue the receive buffer(s) represented by the pointer
1681 * to the RxD and the frag_count into the receive queue again. This
1682 * buffer was filled with an invalid frame or an SMT frame.
1683 * Args
1684 * smc - A pointer to the SMT context struct.
1685 *
1686 * rxd - A pointer to the first RxD which is used by the receive frame.
1687 *
1688 * frag_count - Count of RxDs used by the received frame.
1689 * Out
1690 * Nothing.
1691 *
1692 ************************/
1693void mac_drv_requeue_rxd(struct s_smc *smc, volatile struct s_smt_fp_rxd *rxd,
1694 int frag_count)
1695{
1696 volatile struct s_smt_fp_rxd *next_rxd;
1697 volatile struct s_smt_fp_rxd *src_rxd;
1698 struct sk_buff *skb;
1699 int MaxFrameSize;
1700 unsigned char *v_addr;
1701 dma_addr_t b_addr;
1702
1703 if (frag_count != 1) // This is not allowed to happen.
1704
1705 printk("fddi: Multi-fragment requeue!\n");
1706
1707 MaxFrameSize = smc->os.MaxFrameSize;
1708 src_rxd = rxd;
1709 for (; frag_count > 0; frag_count--) {
1710 next_rxd = src_rxd->rxd_next;
1711 rxd = HWM_GET_CURR_RXD(smc);
1712
1713 skb = src_rxd->rxd_os.skb;
1714 if (skb == NULL) { // this should not happen
1715
1716 pr_debug("Requeue with no skb in rxd!\n");
1717 skb = alloc_skb(MaxFrameSize + 3, GFP_ATOMIC);
1718 if (skb) {
1719 // we got a skb
1720 rxd->rxd_os.skb = skb;
1721 skb_reserve(skb, 3);
1722 skb_put(skb, MaxFrameSize);
1723 v_addr = skb->data;
1724 b_addr = pci_map_single(&smc->os.pdev,
1725 v_addr,
1726 MaxFrameSize,
1727 PCI_DMA_FROMDEVICE);
1728 rxd->rxd_os.dma_addr = b_addr;
1729 } else {
1730 // no skb available, use local buffer
1731 pr_debug("Queueing invalid buffer!\n");
1732 rxd->rxd_os.skb = NULL;
1733 v_addr = smc->os.LocalRxBuffer;
1734 b_addr = smc->os.LocalRxBufferDMA;
1735 }
1736 } else {
1737 // we use skb from old rxd
1738 rxd->rxd_os.skb = skb;
1739 v_addr = skb->data;
1740 b_addr = pci_map_single(&smc->os.pdev,
1741 v_addr,
1742 MaxFrameSize,
1743 PCI_DMA_FROMDEVICE);
1744 rxd->rxd_os.dma_addr = b_addr;
1745 }
1746 hwm_rx_frag(smc, v_addr, b_addr, MaxFrameSize,
1747 FIRST_FRAG | LAST_FRAG);
1748
1749 src_rxd = next_rxd;
1750 }
1751} // mac_drv_requeue_rxd
1752
1753
1754/************************
1755 *
1756 * mac_drv_fill_rxd
1757 *
1758 * The hardware module calls this function at initialization time
1759 * to fill the RxD ring with receive buffers. It is also called by
1760 * mac_drv_rx_complete if rx_free is large enough to queue some new
1761 * receive buffers into the RxD ring. mac_drv_fill_rxd queues new
1762 * receive buffers as long as enough RxDs and receive buffers are
1763 * available.
1764 * Args
1765 * smc - A pointer to the SMT context struct.
1766 * Out
1767 * Nothing.
1768 *
1769 ************************/
1770void mac_drv_fill_rxd(struct s_smc *smc)
1771{
1772 int MaxFrameSize;
1773 unsigned char *v_addr;
1774 unsigned long b_addr;
1775 struct sk_buff *skb;
1776 volatile struct s_smt_fp_rxd *rxd;
1777
1778 pr_debug("entering mac_drv_fill_rxd\n");
1779
1780 // Walk through the list of free receive buffers, passing receive
1781 // buffers to the HWM as long as RXDs are available.
1782
1783 MaxFrameSize = smc->os.MaxFrameSize;
1784 // Check if there is any RXD left.
1785 while (HWM_GET_RX_FREE(smc) > 0) {
1786 pr_debug(".\n");
1787
1788 rxd = HWM_GET_CURR_RXD(smc);
1789 skb = alloc_skb(MaxFrameSize + 3, GFP_ATOMIC);
1790 if (skb) {
1791 // we got a skb
1792 skb_reserve(skb, 3);
1793 skb_put(skb, MaxFrameSize);
1794 v_addr = skb->data;
1795 b_addr = pci_map_single(&smc->os.pdev,
1796 v_addr,
1797 MaxFrameSize,
1798 PCI_DMA_FROMDEVICE);
1799 rxd->rxd_os.dma_addr = b_addr;
1800 } else {
1801 // no skb available, use local buffer
1802 // System has run out of buffer memory, but we want to
1803 // keep the receiver running in hope of better times.
1804 // Multiple descriptors may point to this local buffer,
1805 // so data in it must be considered invalid.
1806 pr_debug("Queueing invalid buffer!\n");
1807 v_addr = smc->os.LocalRxBuffer;
1808 b_addr = smc->os.LocalRxBufferDMA;
1809 }
1810
1811 rxd->rxd_os.skb = skb;
1812
1813 // Pass receive buffer to HWM.
1814 hwm_rx_frag(smc, v_addr, b_addr, MaxFrameSize,
1815 FIRST_FRAG | LAST_FRAG);
1816 }
1817 pr_debug("leaving mac_drv_fill_rxd\n");
1818} // mac_drv_fill_rxd
1819
1820
1821/************************
1822 *
1823 * mac_drv_clear_rxd
1824 *
1825 * The hardware module calls this function to release unused
1826 * receive buffers.
1827 * Args
1828 * smc - A pointer to the SMT context struct.
1829 *
1830 * rxd - A pointer to the first RxD which is used by the receive buffer.
1831 *
1832 * frag_count - Count of RxDs used by the receive buffer.
1833 * Out
1834 * Nothing.
1835 *
1836 ************************/
1837void mac_drv_clear_rxd(struct s_smc *smc, volatile struct s_smt_fp_rxd *rxd,
1838 int frag_count)
1839{
1840
1841 struct sk_buff *skb;
1842
1843 pr_debug("entering mac_drv_clear_rxd\n");
1844
1845 if (frag_count != 1) // This is not allowed to happen.
1846
1847 printk("fddi: Multi-fragment clear!\n");
1848
1849 for (; frag_count > 0; frag_count--) {
1850 skb = rxd->rxd_os.skb;
1851 if (skb != NULL) {
1852 skfddi_priv *bp = &smc->os;
1853 int MaxFrameSize = bp->MaxFrameSize;
1854
1855 pci_unmap_single(&bp->pdev, rxd->rxd_os.dma_addr,
1856 MaxFrameSize, PCI_DMA_FROMDEVICE);
1857
1858 dev_kfree_skb(skb);
1859 rxd->rxd_os.skb = NULL;
1860 }
1861 rxd = rxd->rxd_next; // Next RXD.
1862
1863 }
1864} // mac_drv_clear_rxd
1865
1866
1867/************************
1868 *
1869 * mac_drv_rx_init
1870 *
1871 * The hardware module calls this routine when an SMT or NSA frame of the
1872 * local SMT should be delivered to the LLC layer.
1873 *
1874 * It is necessary to have this function, because there is no other way to
1875 * copy the contents of SMT MBufs into receive buffers.
1876 *
1877 * mac_drv_rx_init allocates the required target memory for this frame,
1878 * and receives the frame fragment by fragment by calling mac_drv_rx_frag.
1879 * Args
1880 * smc - A pointer to the SMT context struct.
1881 *
1882 * len - The length (in bytes) of the received frame (FC, DA, SA, Data).
1883 *
1884 * fc - The Frame Control field of the received frame.
1885 *
1886 * look_ahead - A pointer to the lookahead data buffer (may be NULL).
1887 *
1888 * la_len - The length of the lookahead data stored in the lookahead
1889 * buffer (may be zero).
1890 * Out
1891 * Always returns zero (0).
1892 *
1893 ************************/
1894int mac_drv_rx_init(struct s_smc *smc, int len, int fc,
1895 char *look_ahead, int la_len)
1896{
1897 struct sk_buff *skb;
1898
1899 pr_debug("entering mac_drv_rx_init(len=%d)\n", len);
1900
1901 // "Received" a SMT or NSA frame of the local SMT.
1902
1903 if (len != la_len || len < FDDI_MAC_HDR_LEN || !look_ahead) {
1904 pr_debug("fddi: Discard invalid local SMT frame\n");
1905 pr_debug(" len=%d, la_len=%d, (ULONG) look_ahead=%08lXh.\n",
1906 len, la_len, (unsigned long) look_ahead);
1907 return 0;
1908 }
1909 skb = alloc_skb(len + 3, GFP_ATOMIC);
1910 if (!skb) {
1911 pr_debug("fddi: Local SMT: skb memory exhausted.\n");
1912 return 0;
1913 }
1914 skb_reserve(skb, 3);
1915 skb_put(skb, len);
1916 skb_copy_to_linear_data(skb, look_ahead, len);
1917
1918 // deliver frame to system
1919 skb->protocol = fddi_type_trans(skb, smc->os.dev);
1920 netif_rx(skb);
1921
1922 return 0;
1923} // mac_drv_rx_init
1924
1925
1926/************************
1927 *
1928 * smt_timer_poll
1929 *
1930 * This routine is called periodically by the SMT module to clean up the
1931 * driver.
1932 *
1933 * Return any queued frames back to the upper protocol layers if the ring
1934 * is down.
1935 * Args
1936 * smc - A pointer to the SMT context struct.
1937 * Out
1938 * Nothing.
1939 *
1940 ************************/
1941void smt_timer_poll(struct s_smc *smc)
1942{
1943} // smt_timer_poll
1944
1945
1946/************************
1947 *
1948 * ring_status_indication
1949 *
1950 * This function indicates a change of the ring state.
1951 * Args
1952 * smc - A pointer to the SMT context struct.
1953 *
1954 * status - The current ring status.
1955 * Out
1956 * Nothing.
1957 *
1958 ************************/
1959void ring_status_indication(struct s_smc *smc, u_long status)
1960{
1961 pr_debug("ring_status_indication( ");
1962 if (status & RS_RES15)
1963 pr_debug("RS_RES15 ");
1964 if (status & RS_HARDERROR)
1965 pr_debug("RS_HARDERROR ");
1966 if (status & RS_SOFTERROR)
1967 pr_debug("RS_SOFTERROR ");
1968 if (status & RS_BEACON)
1969 pr_debug("RS_BEACON ");
1970 if (status & RS_PATHTEST)
1971 pr_debug("RS_PATHTEST ");
1972 if (status & RS_SELFTEST)
1973 pr_debug("RS_SELFTEST ");
1974 if (status & RS_RES9)
1975 pr_debug("RS_RES9 ");
1976 if (status & RS_DISCONNECT)
1977 pr_debug("RS_DISCONNECT ");
1978 if (status & RS_RES7)
1979 pr_debug("RS_RES7 ");
1980 if (status & RS_DUPADDR)
1981 pr_debug("RS_DUPADDR ");
1982 if (status & RS_NORINGOP)
1983 pr_debug("RS_NORINGOP ");
1984 if (status & RS_VERSION)
1985 pr_debug("RS_VERSION ");
1986 if (status & RS_STUCKBYPASSS)
1987 pr_debug("RS_STUCKBYPASSS ");
1988 if (status & RS_EVENT)
1989 pr_debug("RS_EVENT ");
1990 if (status & RS_RINGOPCHANGE)
1991 pr_debug("RS_RINGOPCHANGE ");
1992 if (status & RS_RES0)
1993 pr_debug("RS_RES0 ");
1994 pr_debug("]\n");
1995} // ring_status_indication
1996
1997
1998/************************
1999 *
2000 * smt_get_time
2001 *
2002 * Gets the current time from the system.
2003 * Args
2004 * None.
2005 * Out
2006 * The current time in TICKS_PER_SECOND.
2007 *
2008 * TICKS_PER_SECOND has the unit 'count of timer ticks per second'. It is
2009 * defined in "targetos.h". The definition of TICKS_PER_SECOND must comply
2010 * to the time returned by smt_get_time().
2011 *
2012 ************************/
2013unsigned long smt_get_time(void)
2014{
2015 return jiffies;
2016} // smt_get_time
2017
2018
2019/************************
2020 *
2021 * smt_stat_counter
2022 *
2023 * Status counter update (ring_op, fifo full).
2024 * Args
2025 * smc - A pointer to the SMT context struct.
2026 *
2027 * stat - = 0: A ring operational change occurred.
2028 * = 1: The FORMAC FIFO buffer is full / FIFO overflow.
2029 * Out
2030 * Nothing.
2031 *
2032 ************************/
2033void smt_stat_counter(struct s_smc *smc, int stat)
2034{
2035// BOOLEAN RingIsUp ;
2036
2037 pr_debug("smt_stat_counter\n");
2038 switch (stat) {
2039 case 0:
2040 pr_debug("Ring operational change.\n");
2041 break;
2042 case 1:
2043 pr_debug("Receive fifo overflow.\n");
2044 smc->os.MacStat.gen.rx_errors++;
2045 break;
2046 default:
2047 pr_debug("Unknown status (%d).\n", stat);
2048 break;
2049 }
2050} // smt_stat_counter
2051
2052
2053/************************
2054 *
2055 * cfm_state_change
2056 *
2057 * Sets CFM state in custom statistics.
2058 * Args
2059 * smc - A pointer to the SMT context struct.
2060 *
2061 * c_state - Possible values are:
2062 *
2063 * EC0_OUT, EC1_IN, EC2_TRACE, EC3_LEAVE, EC4_PATH_TEST,
2064 * EC5_INSERT, EC6_CHECK, EC7_DEINSERT
2065 * Out
2066 * Nothing.
2067 *
2068 ************************/
2069void cfm_state_change(struct s_smc *smc, int c_state)
2070{
2071#ifdef DRIVERDEBUG
2072 char *s;
2073
2074 switch (c_state) {
2075 case SC0_ISOLATED:
2076 s = "SC0_ISOLATED";
2077 break;
2078 case SC1_WRAP_A:
2079 s = "SC1_WRAP_A";
2080 break;
2081 case SC2_WRAP_B:
2082 s = "SC2_WRAP_B";
2083 break;
2084 case SC4_THRU_A:
2085 s = "SC4_THRU_A";
2086 break;
2087 case SC5_THRU_B:
2088 s = "SC5_THRU_B";
2089 break;
2090 case SC7_WRAP_S:
2091 s = "SC7_WRAP_S";
2092 break;
2093 case SC9_C_WRAP_A:
2094 s = "SC9_C_WRAP_A";
2095 break;
2096 case SC10_C_WRAP_B:
2097 s = "SC10_C_WRAP_B";
2098 break;
2099 case SC11_C_WRAP_S:
2100 s = "SC11_C_WRAP_S";
2101 break;
2102 default:
2103 pr_debug("cfm_state_change: unknown %d\n", c_state);
2104 return;
2105 }
2106 pr_debug("cfm_state_change: %s\n", s);
2107#endif // DRIVERDEBUG
2108} // cfm_state_change
2109
2110
2111/************************
2112 *
2113 * ecm_state_change
2114 *
2115 * Sets ECM state in custom statistics.
2116 * Args
2117 * smc - A pointer to the SMT context struct.
2118 *
2119 * e_state - Possible values are:
2120 *
2121 * SC0_ISOLATED, SC1_WRAP_A (5), SC2_WRAP_B (6), SC4_THRU_A (12),
2122 * SC5_THRU_B (7), SC7_WRAP_S (8)
2123 * Out
2124 * Nothing.
2125 *
2126 ************************/
2127void ecm_state_change(struct s_smc *smc, int e_state)
2128{
2129#ifdef DRIVERDEBUG
2130 char *s;
2131
2132 switch (e_state) {
2133 case EC0_OUT:
2134 s = "EC0_OUT";
2135 break;
2136 case EC1_IN:
2137 s = "EC1_IN";
2138 break;
2139 case EC2_TRACE:
2140 s = "EC2_TRACE";
2141 break;
2142 case EC3_LEAVE:
2143 s = "EC3_LEAVE";
2144 break;
2145 case EC4_PATH_TEST:
2146 s = "EC4_PATH_TEST";
2147 break;
2148 case EC5_INSERT:
2149 s = "EC5_INSERT";
2150 break;
2151 case EC6_CHECK:
2152 s = "EC6_CHECK";
2153 break;
2154 case EC7_DEINSERT:
2155 s = "EC7_DEINSERT";
2156 break;
2157 default:
2158 s = "unknown";
2159 break;
2160 }
2161 pr_debug("ecm_state_change: %s\n", s);
2162#endif //DRIVERDEBUG
2163} // ecm_state_change
2164
2165
2166/************************
2167 *
2168 * rmt_state_change
2169 *
2170 * Sets RMT state in custom statistics.
2171 * Args
2172 * smc - A pointer to the SMT context struct.
2173 *
2174 * r_state - Possible values are:
2175 *
2176 * RM0_ISOLATED, RM1_NON_OP, RM2_RING_OP, RM3_DETECT,
2177 * RM4_NON_OP_DUP, RM5_RING_OP_DUP, RM6_DIRECTED, RM7_TRACE
2178 * Out
2179 * Nothing.
2180 *
2181 ************************/
2182void rmt_state_change(struct s_smc *smc, int r_state)
2183{
2184#ifdef DRIVERDEBUG
2185 char *s;
2186
2187 switch (r_state) {
2188 case RM0_ISOLATED:
2189 s = "RM0_ISOLATED";
2190 break;
2191 case RM1_NON_OP:
2192 s = "RM1_NON_OP - not operational";
2193 break;
2194 case RM2_RING_OP:
2195 s = "RM2_RING_OP - ring operational";
2196 break;
2197 case RM3_DETECT:
2198 s = "RM3_DETECT - detect dupl addresses";
2199 break;
2200 case RM4_NON_OP_DUP:
2201 s = "RM4_NON_OP_DUP - dupl. addr detected";
2202 break;
2203 case RM5_RING_OP_DUP:
2204 s = "RM5_RING_OP_DUP - ring oper. with dupl. addr";
2205 break;
2206 case RM6_DIRECTED:
2207 s = "RM6_DIRECTED - sending directed beacons";
2208 break;
2209 case RM7_TRACE:
2210 s = "RM7_TRACE - trace initiated";
2211 break;
2212 default:
2213 s = "unknown";
2214 break;
2215 }
2216 pr_debug("[rmt_state_change: %s]\n", s);
2217#endif // DRIVERDEBUG
2218} // rmt_state_change
2219
2220
2221/************************
2222 *
2223 * drv_reset_indication
2224 *
2225 * This function is called by the SMT when it has detected a severe
2226 * hardware problem. The driver should perform a reset on the adapter
2227 * as soon as possible, but not from within this function.
2228 * Args
2229 * smc - A pointer to the SMT context struct.
2230 * Out
2231 * Nothing.
2232 *
2233 ************************/
2234void drv_reset_indication(struct s_smc *smc)
2235{
2236 pr_debug("entering drv_reset_indication\n");
2237
2238 smc->os.ResetRequested = TRUE; // Set flag.
2239
2240} // drv_reset_indication
2241
2242static struct pci_driver skfddi_pci_driver = {
2243 .name = "skfddi",
2244 .id_table = skfddi_pci_tbl,
2245 .probe = skfp_init_one,
2246 .remove = __devexit_p(skfp_remove_one),
2247};
2248
2249static int __init skfd_init(void)
2250{
2251 return pci_register_driver(&skfddi_pci_driver);
2252}
2253
2254static void __exit skfd_exit(void)
2255{
2256 pci_unregister_driver(&skfddi_pci_driver);
2257}
2258
2259module_init(skfd_init);
2260module_exit(skfd_exit);
diff --git a/drivers/net/skfp/smt.c b/drivers/net/skfp/smt.c
deleted file mode 100644
index 08d94329c12f..000000000000
--- a/drivers/net/skfp/smt.c
+++ /dev/null
@@ -1,2046 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17#include "h/types.h"
18#include "h/fddi.h"
19#include "h/smc.h"
20#include "h/smt_p.h"
21#include <linux/bitrev.h>
22#include <linux/kernel.h>
23
24#define KERNEL
25#include "h/smtstate.h"
26
27#ifndef lint
28static const char ID_sccs[] = "@(#)smt.c 2.43 98/11/23 (C) SK " ;
29#endif
30
31/*
32 * FC in SMbuf
33 */
34#define m_fc(mb) ((mb)->sm_data[0])
35
36#define SMT_TID_MAGIC 0x1f0a7b3c
37
38#ifdef DEBUG
39static const char *const smt_type_name[] = {
40 "SMT_00??", "SMT_INFO", "SMT_02??", "SMT_03??",
41 "SMT_04??", "SMT_05??", "SMT_06??", "SMT_07??",
42 "SMT_08??", "SMT_09??", "SMT_0A??", "SMT_0B??",
43 "SMT_0C??", "SMT_0D??", "SMT_0E??", "SMT_NSA"
44} ;
45
46static const char *const smt_class_name[] = {
47 "UNKNOWN","NIF","SIF_CONFIG","SIF_OPER","ECF","RAF","RDF",
48 "SRF","PMF_GET","PMF_SET","ESF"
49} ;
50#endif
51#define LAST_CLASS (SMT_PMF_SET)
52
53static const struct fddi_addr SMT_Unknown = {
54 { 0,0,0x1f,0,0,0 }
55} ;
56
57/*
58 * function prototypes
59 */
60#ifdef LITTLE_ENDIAN
61static int smt_swap_short(u_short s);
62#endif
63static int mac_index(struct s_smc *smc, int mac);
64static int phy_index(struct s_smc *smc, int phy);
65static int mac_con_resource_index(struct s_smc *smc, int mac);
66static int phy_con_resource_index(struct s_smc *smc, int phy);
67static void smt_send_rdf(struct s_smc *smc, SMbuf *rej, int fc, int reason,
68 int local);
69static void smt_send_nif(struct s_smc *smc, const struct fddi_addr *dest,
70 int fc, u_long tid, int type, int local);
71static void smt_send_ecf(struct s_smc *smc, struct fddi_addr *dest, int fc,
72 u_long tid, int type, int len);
73static void smt_echo_test(struct s_smc *smc, int dna);
74static void smt_send_sif_config(struct s_smc *smc, struct fddi_addr *dest,
75 u_long tid, int local);
76static void smt_send_sif_operation(struct s_smc *smc, struct fddi_addr *dest,
77 u_long tid, int local);
78#ifdef LITTLE_ENDIAN
79static void smt_string_swap(char *data, const char *format, int len);
80#endif
81static void smt_add_frame_len(SMbuf *mb, int len);
82static void smt_fill_una(struct s_smc *smc, struct smt_p_una *una);
83static void smt_fill_sde(struct s_smc *smc, struct smt_p_sde *sde);
84static void smt_fill_state(struct s_smc *smc, struct smt_p_state *state);
85static void smt_fill_timestamp(struct s_smc *smc, struct smt_p_timestamp *ts);
86static void smt_fill_policy(struct s_smc *smc, struct smt_p_policy *policy);
87static void smt_fill_latency(struct s_smc *smc, struct smt_p_latency *latency);
88static void smt_fill_neighbor(struct s_smc *smc, struct smt_p_neighbor *neighbor);
89static int smt_fill_path(struct s_smc *smc, struct smt_p_path *path);
90static void smt_fill_mac_status(struct s_smc *smc, struct smt_p_mac_status *st);
91static void smt_fill_lem(struct s_smc *smc, struct smt_p_lem *lem, int phy);
92static void smt_fill_version(struct s_smc *smc, struct smt_p_version *vers);
93static void smt_fill_fsc(struct s_smc *smc, struct smt_p_fsc *fsc);
94static void smt_fill_mac_counter(struct s_smc *smc, struct smt_p_mac_counter *mc);
95static void smt_fill_mac_fnc(struct s_smc *smc, struct smt_p_mac_fnc *fnc);
96static void smt_fill_manufacturer(struct s_smc *smc,
97 struct smp_p_manufacturer *man);
98static void smt_fill_user(struct s_smc *smc, struct smp_p_user *user);
99static void smt_fill_setcount(struct s_smc *smc, struct smt_p_setcount *setcount);
100static void smt_fill_echo(struct s_smc *smc, struct smt_p_echo *echo, u_long seed,
101 int len);
102
103static void smt_clear_una_dna(struct s_smc *smc);
104static void smt_clear_old_una_dna(struct s_smc *smc);
105#ifdef CONCENTRATOR
106static int entity_to_index(void);
107#endif
108static void update_dac(struct s_smc *smc, int report);
109static int div_ratio(u_long upper, u_long lower);
110#ifdef USE_CAN_ADDR
111static void hwm_conv_can(struct s_smc *smc, char *data, int len);
112#else
113#define hwm_conv_can(smc,data,len)
114#endif
115
116
117static inline int is_my_addr(const struct s_smc *smc,
118 const struct fddi_addr *addr)
119{
120 return(*(short *)(&addr->a[0]) ==
121 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[0])
122 && *(short *)(&addr->a[2]) ==
123 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[2])
124 && *(short *)(&addr->a[4]) ==
125 *(short *)(&smc->mib.m[MAC0].fddiMACSMTAddress.a[4])) ;
126}
127
128static inline int is_broadcast(const struct fddi_addr *addr)
129{
130 return *(u_short *)(&addr->a[0]) == 0xffff &&
131 *(u_short *)(&addr->a[2]) == 0xffff &&
132 *(u_short *)(&addr->a[4]) == 0xffff;
133}
134
135static inline int is_individual(const struct fddi_addr *addr)
136{
137 return !(addr->a[0] & GROUP_ADDR);
138}
139
140static inline int is_equal(const struct fddi_addr *addr1,
141 const struct fddi_addr *addr2)
142{
143 return *(u_short *)(&addr1->a[0]) == *(u_short *)(&addr2->a[0]) &&
144 *(u_short *)(&addr1->a[2]) == *(u_short *)(&addr2->a[2]) &&
145 *(u_short *)(&addr1->a[4]) == *(u_short *)(&addr2->a[4]);
146}
147
148/*
149 * list of mandatory paras in frames
150 */
151static const u_short plist_nif[] = { SMT_P_UNA,SMT_P_SDE,SMT_P_STATE,0 } ;
152
153/*
154 * init SMT agent
155 */
156void smt_agent_init(struct s_smc *smc)
157{
158 int i ;
159
160 /*
161 * get MAC address
162 */
163 smc->mib.m[MAC0].fddiMACSMTAddress = smc->hw.fddi_home_addr ;
164
165 /*
166 * get OUI address from driver (bia == built-in-address)
167 */
168 smc->mib.fddiSMTStationId.sid_oem[0] = 0 ;
169 smc->mib.fddiSMTStationId.sid_oem[1] = 0 ;
170 driver_get_bia(smc,&smc->mib.fddiSMTStationId.sid_node) ;
171 for (i = 0 ; i < 6 ; i ++) {
172 smc->mib.fddiSMTStationId.sid_node.a[i] =
173 bitrev8(smc->mib.fddiSMTStationId.sid_node.a[i]);
174 }
175 smc->mib.fddiSMTManufacturerData[0] =
176 smc->mib.fddiSMTStationId.sid_node.a[0] ;
177 smc->mib.fddiSMTManufacturerData[1] =
178 smc->mib.fddiSMTStationId.sid_node.a[1] ;
179 smc->mib.fddiSMTManufacturerData[2] =
180 smc->mib.fddiSMTStationId.sid_node.a[2] ;
181 smc->sm.smt_tid = 0 ;
182 smc->mib.m[MAC0].fddiMACDupAddressTest = DA_NONE ;
183 smc->mib.m[MAC0].fddiMACUNDA_Flag = FALSE ;
184#ifndef SLIM_SMT
185 smt_clear_una_dna(smc) ;
186 smt_clear_old_una_dna(smc) ;
187#endif
188 for (i = 0 ; i < SMT_MAX_TEST ; i++)
189 smc->sm.pend[i] = 0 ;
190 smc->sm.please_reconnect = 0 ;
191 smc->sm.uniq_ticks = 0 ;
192}
193
194/*
195 * SMT task
196 * forever
197 * delay 30 seconds
198 * send NIF
199 * check tvu & tvd
200 * end
201 */
202void smt_agent_task(struct s_smc *smc)
203{
204 smt_timer_start(smc,&smc->sm.smt_timer, (u_long)1000000L,
205 EV_TOKEN(EVENT_SMT,SM_TIMER)) ;
206 DB_SMT("SMT agent task\n",0,0) ;
207}
208
209#ifndef SMT_REAL_TOKEN_CT
210void smt_emulate_token_ct(struct s_smc *smc, int mac_index)
211{
212 u_long count;
213 u_long time;
214
215
216 time = smt_get_time();
217 count = ((time - smc->sm.last_tok_time[mac_index]) *
218 100)/TICKS_PER_SECOND;
219
220 /*
221 * Only when ring is up we will have a token count. The
222 * flag is unfortunately a single instance value. This
223 * doesn't matter now, because we currently have only
224 * one MAC instance.
225 */
226 if (smc->hw.mac_ring_is_up){
227 smc->mib.m[mac_index].fddiMACToken_Ct += count;
228 }
229
230 /* Remember current time */
231 smc->sm.last_tok_time[mac_index] = time;
232
233}
234#endif
235
236/*ARGSUSED1*/
237void smt_event(struct s_smc *smc, int event)
238{
239 u_long time ;
240#ifndef SMT_REAL_TOKEN_CT
241 int i ;
242#endif
243
244
245 if (smc->sm.please_reconnect) {
246 smc->sm.please_reconnect -- ;
247 if (smc->sm.please_reconnect == 0) {
248 /* Counted down */
249 queue_event(smc,EVENT_ECM,EC_CONNECT) ;
250 }
251 }
252
253 if (event == SM_FAST)
254 return ;
255
256 /*
257 * timer for periodic cleanup in driver
258 * reset and start the watchdog (FM2)
259 * ESS timer
260 * SBA timer
261 */
262 smt_timer_poll(smc) ;
263 smt_start_watchdog(smc) ;
264#ifndef SLIM_SMT
265#ifndef BOOT
266#ifdef ESS
267 ess_timer_poll(smc) ;
268#endif
269#endif
270#ifdef SBA
271 sba_timer_poll(smc) ;
272#endif
273
274 smt_srf_event(smc,0,0,0) ;
275
276#endif /* no SLIM_SMT */
277
278 time = smt_get_time() ;
279
280 if (time - smc->sm.smt_last_lem >= TICKS_PER_SECOND*8) {
281 /*
282 * Use 8 sec. for the time intervall, it simplifies the
283 * LER estimation.
284 */
285 struct fddi_mib_m *mib ;
286 u_long upper ;
287 u_long lower ;
288 int cond ;
289 int port;
290 struct s_phy *phy ;
291 /*
292 * calculate LEM bit error rate
293 */
294 sm_lem_evaluate(smc) ;
295 smc->sm.smt_last_lem = time ;
296
297 /*
298 * check conditions
299 */
300#ifndef SLIM_SMT
301 mac_update_counter(smc) ;
302 mib = smc->mib.m ;
303 upper =
304 (mib->fddiMACLost_Ct - mib->fddiMACOld_Lost_Ct) +
305 (mib->fddiMACError_Ct - mib->fddiMACOld_Error_Ct) ;
306 lower =
307 (mib->fddiMACFrame_Ct - mib->fddiMACOld_Frame_Ct) +
308 (mib->fddiMACLost_Ct - mib->fddiMACOld_Lost_Ct) ;
309 mib->fddiMACFrameErrorRatio = div_ratio(upper,lower) ;
310
311 cond =
312 ((!mib->fddiMACFrameErrorThreshold &&
313 mib->fddiMACError_Ct != mib->fddiMACOld_Error_Ct) ||
314 (mib->fddiMACFrameErrorRatio >
315 mib->fddiMACFrameErrorThreshold)) ;
316
317 if (cond != mib->fddiMACFrameErrorFlag)
318 smt_srf_event(smc,SMT_COND_MAC_FRAME_ERROR,
319 INDEX_MAC,cond) ;
320
321 upper =
322 (mib->fddiMACNotCopied_Ct - mib->fddiMACOld_NotCopied_Ct) ;
323 lower =
324 upper +
325 (mib->fddiMACCopied_Ct - mib->fddiMACOld_Copied_Ct) ;
326 mib->fddiMACNotCopiedRatio = div_ratio(upper,lower) ;
327
328 cond =
329 ((!mib->fddiMACNotCopiedThreshold &&
330 mib->fddiMACNotCopied_Ct !=
331 mib->fddiMACOld_NotCopied_Ct)||
332 (mib->fddiMACNotCopiedRatio >
333 mib->fddiMACNotCopiedThreshold)) ;
334
335 if (cond != mib->fddiMACNotCopiedFlag)
336 smt_srf_event(smc,SMT_COND_MAC_NOT_COPIED,
337 INDEX_MAC,cond) ;
338
339 /*
340 * set old values
341 */
342 mib->fddiMACOld_Frame_Ct = mib->fddiMACFrame_Ct ;
343 mib->fddiMACOld_Copied_Ct = mib->fddiMACCopied_Ct ;
344 mib->fddiMACOld_Error_Ct = mib->fddiMACError_Ct ;
345 mib->fddiMACOld_Lost_Ct = mib->fddiMACLost_Ct ;
346 mib->fddiMACOld_NotCopied_Ct = mib->fddiMACNotCopied_Ct ;
347
348 /*
349 * Check port EBError Condition
350 */
351 for (port = 0; port < NUMPHYS; port ++) {
352 phy = &smc->y[port] ;
353
354 if (!phy->mib->fddiPORTHardwarePresent) {
355 continue;
356 }
357
358 cond = (phy->mib->fddiPORTEBError_Ct -
359 phy->mib->fddiPORTOldEBError_Ct > 5) ;
360
361 /* If ratio is more than 5 in 8 seconds
362 * Set the condition.
363 */
364 smt_srf_event(smc,SMT_COND_PORT_EB_ERROR,
365 (int) (INDEX_PORT+ phy->np) ,cond) ;
366
367 /*
368 * set old values
369 */
370 phy->mib->fddiPORTOldEBError_Ct =
371 phy->mib->fddiPORTEBError_Ct ;
372 }
373
374#endif /* no SLIM_SMT */
375 }
376
377#ifndef SLIM_SMT
378
379 if (time - smc->sm.smt_last_notify >= (u_long)
380 (smc->mib.fddiSMTTT_Notify * TICKS_PER_SECOND) ) {
381 /*
382 * we can either send an announcement or a request
383 * a request will trigger a reply so that we can update
384 * our dna
385 * note: same tid must be used until reply is received
386 */
387 if (!smc->sm.pend[SMT_TID_NIF])
388 smc->sm.pend[SMT_TID_NIF] = smt_get_tid(smc) ;
389 smt_send_nif(smc,&fddi_broadcast, FC_SMT_NSA,
390 smc->sm.pend[SMT_TID_NIF], SMT_REQUEST,0) ;
391 smc->sm.smt_last_notify = time ;
392 }
393
394 /*
395 * check timer
396 */
397 if (smc->sm.smt_tvu &&
398 time - smc->sm.smt_tvu > 228*TICKS_PER_SECOND) {
399 DB_SMT("SMT : UNA expired\n",0,0) ;
400 smc->sm.smt_tvu = 0 ;
401
402 if (!is_equal(&smc->mib.m[MAC0].fddiMACUpstreamNbr,
403 &SMT_Unknown)){
404 /* Do not update unknown address */
405 smc->mib.m[MAC0].fddiMACOldUpstreamNbr=
406 smc->mib.m[MAC0].fddiMACUpstreamNbr ;
407 }
408 smc->mib.m[MAC0].fddiMACUpstreamNbr = SMT_Unknown ;
409 smc->mib.m[MAC0].fddiMACUNDA_Flag = FALSE ;
410 /*
411 * Make sure the fddiMACUNDA_Flag = FALSE is
412 * included in the SRF so we don't generate
413 * a separate SRF for the deassertion of this
414 * condition
415 */
416 update_dac(smc,0) ;
417 smt_srf_event(smc, SMT_EVENT_MAC_NEIGHBOR_CHANGE,
418 INDEX_MAC,0) ;
419 }
420 if (smc->sm.smt_tvd &&
421 time - smc->sm.smt_tvd > 228*TICKS_PER_SECOND) {
422 DB_SMT("SMT : DNA expired\n",0,0) ;
423 smc->sm.smt_tvd = 0 ;
424 if (!is_equal(&smc->mib.m[MAC0].fddiMACDownstreamNbr,
425 &SMT_Unknown)){
426 /* Do not update unknown address */
427 smc->mib.m[MAC0].fddiMACOldDownstreamNbr=
428 smc->mib.m[MAC0].fddiMACDownstreamNbr ;
429 }
430 smc->mib.m[MAC0].fddiMACDownstreamNbr = SMT_Unknown ;
431 smt_srf_event(smc, SMT_EVENT_MAC_NEIGHBOR_CHANGE,
432 INDEX_MAC,0) ;
433 }
434
435#endif /* no SLIM_SMT */
436
437#ifndef SMT_REAL_TOKEN_CT
438 /*
439 * Token counter emulation section. If hardware supports the token
440 * count, the token counter will be updated in mac_update_counter.
441 */
442 for (i = MAC0; i < NUMMACS; i++ ){
443 if (time - smc->sm.last_tok_time[i] > 2*TICKS_PER_SECOND ){
444 smt_emulate_token_ct( smc, i );
445 }
446 }
447#endif
448
449 smt_timer_start(smc,&smc->sm.smt_timer, (u_long)1000000L,
450 EV_TOKEN(EVENT_SMT,SM_TIMER)) ;
451}
452
453static int div_ratio(u_long upper, u_long lower)
454{
455 if ((upper<<16L) < upper)
456 upper = 0xffff0000L ;
457 else
458 upper <<= 16L ;
459 if (!lower)
460 return 0;
461 return (int)(upper/lower) ;
462}
463
464#ifndef SLIM_SMT
465
466/*
467 * receive packet handler
468 */
469void smt_received_pack(struct s_smc *smc, SMbuf *mb, int fs)
470/* int fs; frame status */
471{
472 struct smt_header *sm ;
473 int local ;
474
475 int illegal = 0 ;
476
477 switch (m_fc(mb)) {
478 case FC_SMT_INFO :
479 case FC_SMT_LAN_LOC :
480 case FC_SMT_LOC :
481 case FC_SMT_NSA :
482 break ;
483 default :
484 smt_free_mbuf(smc,mb) ;
485 return ;
486 }
487
488 smc->mib.m[MAC0].fddiMACSMTCopied_Ct++ ;
489 sm = smtod(mb,struct smt_header *) ;
490 local = ((fs & L_INDICATOR) != 0) ;
491 hwm_conv_can(smc,(char *)sm,12) ;
492
493 /* check destination address */
494 if (is_individual(&sm->smt_dest) && !is_my_addr(smc,&sm->smt_dest)) {
495 smt_free_mbuf(smc,mb) ;
496 return ;
497 }
498#if 0 /* for DUP recognition, do NOT filter them */
499 /* ignore loop back packets */
500 if (is_my_addr(smc,&sm->smt_source) && !local) {
501 smt_free_mbuf(smc,mb) ;
502 return ;
503 }
504#endif
505
506 smt_swap_para(sm,(int) mb->sm_len,1) ;
507 DB_SMT("SMT : received packet [%s] at 0x%x\n",
508 smt_type_name[m_fc(mb) & 0xf],sm) ;
509 DB_SMT("SMT : version %d, class %s\n",sm->smt_version,
510 smt_class_name[(sm->smt_class>LAST_CLASS)?0 : sm->smt_class]) ;
511
512#ifdef SBA
513 /*
514 * check if NSA frame
515 */
516 if (m_fc(mb) == FC_SMT_NSA && sm->smt_class == SMT_NIF &&
517 (sm->smt_type == SMT_ANNOUNCE || sm->smt_type == SMT_REQUEST)) {
518 smc->sba.sm = sm ;
519 sba(smc,NIF) ;
520 }
521#endif
522
523 /*
524 * ignore any packet with NSA and A-indicator set
525 */
526 if ( (fs & A_INDICATOR) && m_fc(mb) == FC_SMT_NSA) {
527 DB_SMT("SMT : ignoring NSA with A-indicator set from %s\n",
528 addr_to_string(&sm->smt_source),0) ;
529 smt_free_mbuf(smc,mb) ;
530 return ;
531 }
532
533 /*
534 * ignore frames with illegal length
535 */
536 if (((sm->smt_class == SMT_ECF) && (sm->smt_len > SMT_MAX_ECHO_LEN)) ||
537 ((sm->smt_class != SMT_ECF) && (sm->smt_len > SMT_MAX_INFO_LEN))) {
538 smt_free_mbuf(smc,mb) ;
539 return ;
540 }
541
542 /*
543 * check SMT version
544 */
545 switch (sm->smt_class) {
546 case SMT_NIF :
547 case SMT_SIF_CONFIG :
548 case SMT_SIF_OPER :
549 case SMT_ECF :
550 if (sm->smt_version != SMT_VID)
551 illegal = 1;
552 break ;
553 default :
554 if (sm->smt_version != SMT_VID_2)
555 illegal = 1;
556 break ;
557 }
558 if (illegal) {
559 DB_SMT("SMT : version = %d, dest = %s\n",
560 sm->smt_version,addr_to_string(&sm->smt_source)) ;
561 smt_send_rdf(smc,mb,m_fc(mb),SMT_RDF_VERSION,local) ;
562 smt_free_mbuf(smc,mb) ;
563 return ;
564 }
565 if ((sm->smt_len > mb->sm_len - sizeof(struct smt_header)) ||
566 ((sm->smt_len & 3) && (sm->smt_class != SMT_ECF))) {
567 DB_SMT("SMT: info length error, len = %d\n",sm->smt_len,0) ;
568 smt_send_rdf(smc,mb,m_fc(mb),SMT_RDF_LENGTH,local) ;
569 smt_free_mbuf(smc,mb) ;
570 return ;
571 }
572 switch (sm->smt_class) {
573 case SMT_NIF :
574 if (smt_check_para(smc,sm,plist_nif)) {
575 DB_SMT("SMT: NIF with para problem, ignoring\n",0,0) ;
576 break ;
577 }
578 switch (sm->smt_type) {
579 case SMT_ANNOUNCE :
580 case SMT_REQUEST :
581 if (!(fs & C_INDICATOR) && m_fc(mb) == FC_SMT_NSA
582 && is_broadcast(&sm->smt_dest)) {
583 struct smt_p_state *st ;
584
585 /* set my UNA */
586 if (!is_equal(
587 &smc->mib.m[MAC0].fddiMACUpstreamNbr,
588 &sm->smt_source)) {
589 DB_SMT("SMT : updated my UNA = %s\n",
590 addr_to_string(&sm->smt_source),0) ;
591 if (!is_equal(&smc->mib.m[MAC0].
592 fddiMACUpstreamNbr,&SMT_Unknown)){
593 /* Do not update unknown address */
594 smc->mib.m[MAC0].fddiMACOldUpstreamNbr=
595 smc->mib.m[MAC0].fddiMACUpstreamNbr ;
596 }
597
598 smc->mib.m[MAC0].fddiMACUpstreamNbr =
599 sm->smt_source ;
600 smt_srf_event(smc,
601 SMT_EVENT_MAC_NEIGHBOR_CHANGE,
602 INDEX_MAC,0) ;
603 smt_echo_test(smc,0) ;
604 }
605 smc->sm.smt_tvu = smt_get_time() ;
606 st = (struct smt_p_state *)
607 sm_to_para(smc,sm,SMT_P_STATE) ;
608 if (st) {
609 smc->mib.m[MAC0].fddiMACUNDA_Flag =
610 (st->st_dupl_addr & SMT_ST_MY_DUPA) ?
611 TRUE : FALSE ;
612 update_dac(smc,1) ;
613 }
614 }
615 if ((sm->smt_type == SMT_REQUEST) &&
616 is_individual(&sm->smt_source) &&
617 ((!(fs & A_INDICATOR) && m_fc(mb) == FC_SMT_NSA) ||
618 (m_fc(mb) != FC_SMT_NSA))) {
619 DB_SMT("SMT : replying to NIF request %s\n",
620 addr_to_string(&sm->smt_source),0) ;
621 smt_send_nif(smc,&sm->smt_source,
622 FC_SMT_INFO,
623 sm->smt_tid,
624 SMT_REPLY,local) ;
625 }
626 break ;
627 case SMT_REPLY :
628 DB_SMT("SMT : received NIF response from %s\n",
629 addr_to_string(&sm->smt_source),0) ;
630 if (fs & A_INDICATOR) {
631 smc->sm.pend[SMT_TID_NIF] = 0 ;
632 DB_SMT("SMT : duplicate address\n",0,0) ;
633 smc->mib.m[MAC0].fddiMACDupAddressTest =
634 DA_FAILED ;
635 smc->r.dup_addr_test = DA_FAILED ;
636 queue_event(smc,EVENT_RMT,RM_DUP_ADDR) ;
637 smc->mib.m[MAC0].fddiMACDA_Flag = TRUE ;
638 update_dac(smc,1) ;
639 break ;
640 }
641 if (sm->smt_tid == smc->sm.pend[SMT_TID_NIF]) {
642 smc->sm.pend[SMT_TID_NIF] = 0 ;
643 /* set my DNA */
644 if (!is_equal(
645 &smc->mib.m[MAC0].fddiMACDownstreamNbr,
646 &sm->smt_source)) {
647 DB_SMT("SMT : updated my DNA\n",0,0) ;
648 if (!is_equal(&smc->mib.m[MAC0].
649 fddiMACDownstreamNbr, &SMT_Unknown)){
650 /* Do not update unknown address */
651 smc->mib.m[MAC0].fddiMACOldDownstreamNbr =
652 smc->mib.m[MAC0].fddiMACDownstreamNbr ;
653 }
654
655 smc->mib.m[MAC0].fddiMACDownstreamNbr =
656 sm->smt_source ;
657 smt_srf_event(smc,
658 SMT_EVENT_MAC_NEIGHBOR_CHANGE,
659 INDEX_MAC,0) ;
660 smt_echo_test(smc,1) ;
661 }
662 smc->mib.m[MAC0].fddiMACDA_Flag = FALSE ;
663 update_dac(smc,1) ;
664 smc->sm.smt_tvd = smt_get_time() ;
665 smc->mib.m[MAC0].fddiMACDupAddressTest =
666 DA_PASSED ;
667 if (smc->r.dup_addr_test != DA_PASSED) {
668 smc->r.dup_addr_test = DA_PASSED ;
669 queue_event(smc,EVENT_RMT,RM_DUP_ADDR) ;
670 }
671 }
672 else if (sm->smt_tid ==
673 smc->sm.pend[SMT_TID_NIF_TEST]) {
674 DB_SMT("SMT : NIF test TID ok\n",0,0) ;
675 }
676 else {
677 DB_SMT("SMT : expected TID %lx, got %lx\n",
678 smc->sm.pend[SMT_TID_NIF],sm->smt_tid) ;
679 }
680 break ;
681 default :
682 illegal = 2 ;
683 break ;
684 }
685 break ;
686 case SMT_SIF_CONFIG : /* station information */
687 if (sm->smt_type != SMT_REQUEST)
688 break ;
689 DB_SMT("SMT : replying to SIF Config request from %s\n",
690 addr_to_string(&sm->smt_source),0) ;
691 smt_send_sif_config(smc,&sm->smt_source,sm->smt_tid,local) ;
692 break ;
693 case SMT_SIF_OPER : /* station information */
694 if (sm->smt_type != SMT_REQUEST)
695 break ;
696 DB_SMT("SMT : replying to SIF Operation request from %s\n",
697 addr_to_string(&sm->smt_source),0) ;
698 smt_send_sif_operation(smc,&sm->smt_source,sm->smt_tid,local) ;
699 break ;
700 case SMT_ECF : /* echo frame */
701 switch (sm->smt_type) {
702 case SMT_REPLY :
703 smc->mib.priv.fddiPRIVECF_Reply_Rx++ ;
704 DB_SMT("SMT: received ECF reply from %s\n",
705 addr_to_string(&sm->smt_source),0) ;
706 if (sm_to_para(smc,sm,SMT_P_ECHODATA) == NULL) {
707 DB_SMT("SMT: ECHODATA missing\n",0,0) ;
708 break ;
709 }
710 if (sm->smt_tid == smc->sm.pend[SMT_TID_ECF]) {
711 DB_SMT("SMT : ECF test TID ok\n",0,0) ;
712 }
713 else if (sm->smt_tid == smc->sm.pend[SMT_TID_ECF_UNA]) {
714 DB_SMT("SMT : ECF test UNA ok\n",0,0) ;
715 }
716 else if (sm->smt_tid == smc->sm.pend[SMT_TID_ECF_DNA]) {
717 DB_SMT("SMT : ECF test DNA ok\n",0,0) ;
718 }
719 else {
720 DB_SMT("SMT : expected TID %lx, got %lx\n",
721 smc->sm.pend[SMT_TID_ECF],
722 sm->smt_tid) ;
723 }
724 break ;
725 case SMT_REQUEST :
726 smc->mib.priv.fddiPRIVECF_Req_Rx++ ;
727 {
728 if (sm->smt_len && !sm_to_para(smc,sm,SMT_P_ECHODATA)) {
729 DB_SMT("SMT: ECF with para problem,sending RDF\n",0,0) ;
730 smt_send_rdf(smc,mb,m_fc(mb),SMT_RDF_LENGTH,
731 local) ;
732 break ;
733 }
734 DB_SMT("SMT - sending ECF reply to %s\n",
735 addr_to_string(&sm->smt_source),0) ;
736
737 /* set destination addr. & reply */
738 sm->smt_dest = sm->smt_source ;
739 sm->smt_type = SMT_REPLY ;
740 dump_smt(smc,sm,"ECF REPLY") ;
741 smc->mib.priv.fddiPRIVECF_Reply_Tx++ ;
742 smt_send_frame(smc,mb,FC_SMT_INFO,local) ;
743 return ; /* DON'T free mbuf */
744 }
745 default :
746 illegal = 1 ;
747 break ;
748 }
749 break ;
750#ifndef BOOT
751 case SMT_RAF : /* resource allocation */
752#ifdef ESS
753 DB_ESSN(2,"ESS: RAF frame received\n",0,0) ;
754 fs = ess_raf_received_pack(smc,mb,sm,fs) ;
755#endif
756
757#ifdef SBA
758 DB_SBAN(2,"SBA: RAF frame received\n",0,0) ;
759 sba_raf_received_pack(smc,sm,fs) ;
760#endif
761 break ;
762 case SMT_RDF : /* request denied */
763 smc->mib.priv.fddiPRIVRDF_Rx++ ;
764 break ;
765 case SMT_ESF : /* extended service - not supported */
766 if (sm->smt_type == SMT_REQUEST) {
767 DB_SMT("SMT - received ESF, sending RDF\n",0,0) ;
768 smt_send_rdf(smc,mb,m_fc(mb),SMT_RDF_CLASS,local) ;
769 }
770 break ;
771 case SMT_PMF_GET :
772 case SMT_PMF_SET :
773 if (sm->smt_type != SMT_REQUEST)
774 break ;
775 /* update statistics */
776 if (sm->smt_class == SMT_PMF_GET)
777 smc->mib.priv.fddiPRIVPMF_Get_Rx++ ;
778 else
779 smc->mib.priv.fddiPRIVPMF_Set_Rx++ ;
780 /*
781 * ignore PMF SET with I/G set
782 */
783 if ((sm->smt_class == SMT_PMF_SET) &&
784 !is_individual(&sm->smt_dest)) {
785 DB_SMT("SMT: ignoring PMF-SET with I/G set\n",0,0) ;
786 break ;
787 }
788 smt_pmf_received_pack(smc,mb, local) ;
789 break ;
790 case SMT_SRF :
791 dump_smt(smc,sm,"SRF received") ;
792 break ;
793 default :
794 if (sm->smt_type != SMT_REQUEST)
795 break ;
796 /*
797 * For frames with unknown class:
798 * we need to send a RDF frame according to 8.1.3.1.1,
799 * only if it is a REQUEST.
800 */
801 DB_SMT("SMT : class = %d, send RDF to %s\n",
802 sm->smt_class, addr_to_string(&sm->smt_source)) ;
803
804 smt_send_rdf(smc,mb,m_fc(mb),SMT_RDF_CLASS,local) ;
805 break ;
806#endif
807 }
808 if (illegal) {
809 DB_SMT("SMT: discarding invalid frame, reason = %d\n",
810 illegal,0) ;
811 }
812 smt_free_mbuf(smc,mb) ;
813}
814
815static void update_dac(struct s_smc *smc, int report)
816{
817 int cond ;
818
819 cond = ( smc->mib.m[MAC0].fddiMACUNDA_Flag |
820 smc->mib.m[MAC0].fddiMACDA_Flag) != 0 ;
821 if (report && (cond != smc->mib.m[MAC0].fddiMACDuplicateAddressCond))
822 smt_srf_event(smc, SMT_COND_MAC_DUP_ADDR,INDEX_MAC,cond) ;
823 else
824 smc->mib.m[MAC0].fddiMACDuplicateAddressCond = cond ;
825}
826
827/*
828 * send SMT frame
829 * set source address
830 * set station ID
831 * send frame
832 */
833void smt_send_frame(struct s_smc *smc, SMbuf *mb, int fc, int local)
834/* SMbuf *mb; buffer to send */
835/* int fc; FC value */
836{
837 struct smt_header *sm ;
838
839 if (!smc->r.sm_ma_avail && !local) {
840 smt_free_mbuf(smc,mb) ;
841 return ;
842 }
843 sm = smtod(mb,struct smt_header *) ;
844 sm->smt_source = smc->mib.m[MAC0].fddiMACSMTAddress ;
845 sm->smt_sid = smc->mib.fddiSMTStationId ;
846
847 smt_swap_para(sm,(int) mb->sm_len,0) ; /* swap para & header */
848 hwm_conv_can(smc,(char *)sm,12) ; /* convert SA and DA */
849 smc->mib.m[MAC0].fddiMACSMTTransmit_Ct++ ;
850 smt_send_mbuf(smc,mb,local ? FC_SMT_LOC : fc) ;
851}
852
853/*
854 * generate and send RDF
855 */
856static void smt_send_rdf(struct s_smc *smc, SMbuf *rej, int fc, int reason,
857 int local)
858/* SMbuf *rej; mbuf of offending frame */
859/* int fc; FC of denied frame */
860/* int reason; reason code */
861{
862 SMbuf *mb ;
863 struct smt_header *sm ; /* header of offending frame */
864 struct smt_rdf *rdf ;
865 int len ;
866 int frame_len ;
867
868 sm = smtod(rej,struct smt_header *) ;
869 if (sm->smt_type != SMT_REQUEST)
870 return ;
871
872 DB_SMT("SMT: sending RDF to %s,reason = 0x%x\n",
873 addr_to_string(&sm->smt_source),reason) ;
874
875
876 /*
877 * note: get framelength from MAC length, NOT from SMT header
878 * smt header length is included in sm_len
879 */
880 frame_len = rej->sm_len ;
881
882 if (!(mb=smt_build_frame(smc,SMT_RDF,SMT_REPLY,sizeof(struct smt_rdf))))
883 return ;
884 rdf = smtod(mb,struct smt_rdf *) ;
885 rdf->smt.smt_tid = sm->smt_tid ; /* use TID from sm */
886 rdf->smt.smt_dest = sm->smt_source ; /* set dest = source */
887
888 /* set P12 */
889 rdf->reason.para.p_type = SMT_P_REASON ;
890 rdf->reason.para.p_len = sizeof(struct smt_p_reason) - PARA_LEN ;
891 rdf->reason.rdf_reason = reason ;
892
893 /* set P14 */
894 rdf->version.para.p_type = SMT_P_VERSION ;
895 rdf->version.para.p_len = sizeof(struct smt_p_version) - PARA_LEN ;
896 rdf->version.v_pad = 0 ;
897 rdf->version.v_n = 1 ;
898 rdf->version.v_index = 1 ;
899 rdf->version.v_version[0] = SMT_VID_2 ;
900 rdf->version.v_pad2 = 0 ;
901
902 /* set P13 */
903 if ((unsigned) frame_len <= SMT_MAX_INFO_LEN - sizeof(*rdf) +
904 2*sizeof(struct smt_header))
905 len = frame_len ;
906 else
907 len = SMT_MAX_INFO_LEN - sizeof(*rdf) +
908 2*sizeof(struct smt_header) ;
909 /* make length multiple of 4 */
910 len &= ~3 ;
911 rdf->refused.para.p_type = SMT_P_REFUSED ;
912 /* length of para is smt_frame + ref_fc */
913 rdf->refused.para.p_len = len + 4 ;
914 rdf->refused.ref_fc = fc ;
915
916 /* swap it back */
917 smt_swap_para(sm,frame_len,0) ;
918
919 memcpy((char *) &rdf->refused.ref_header,(char *) sm,len) ;
920
921 len -= sizeof(struct smt_header) ;
922 mb->sm_len += len ;
923 rdf->smt.smt_len += len ;
924
925 dump_smt(smc,(struct smt_header *)rdf,"RDF") ;
926 smc->mib.priv.fddiPRIVRDF_Tx++ ;
927 smt_send_frame(smc,mb,FC_SMT_INFO,local) ;
928}
929
930/*
931 * generate and send NIF
932 */
933static void smt_send_nif(struct s_smc *smc, const struct fddi_addr *dest,
934 int fc, u_long tid, int type, int local)
935/* struct fddi_addr *dest; dest address */
936/* int fc; frame control */
937/* u_long tid; transaction id */
938/* int type; frame type */
939{
940 struct smt_nif *nif ;
941 SMbuf *mb ;
942
943 if (!(mb = smt_build_frame(smc,SMT_NIF,type,sizeof(struct smt_nif))))
944 return ;
945 nif = smtod(mb, struct smt_nif *) ;
946 smt_fill_una(smc,&nif->una) ; /* set UNA */
947 smt_fill_sde(smc,&nif->sde) ; /* set station descriptor */
948 smt_fill_state(smc,&nif->state) ; /* set state information */
949#ifdef SMT6_10
950 smt_fill_fsc(smc,&nif->fsc) ; /* set frame status cap. */
951#endif
952 nif->smt.smt_dest = *dest ; /* destination address */
953 nif->smt.smt_tid = tid ; /* transaction ID */
954 dump_smt(smc,(struct smt_header *)nif,"NIF") ;
955 smt_send_frame(smc,mb,fc,local) ;
956}
957
958#ifdef DEBUG
959/*
960 * send NIF request (test purpose)
961 */
962static void smt_send_nif_request(struct s_smc *smc, struct fddi_addr *dest)
963{
964 smc->sm.pend[SMT_TID_NIF_TEST] = smt_get_tid(smc) ;
965 smt_send_nif(smc,dest, FC_SMT_INFO, smc->sm.pend[SMT_TID_NIF_TEST],
966 SMT_REQUEST,0) ;
967}
968
969/*
970 * send ECF request (test purpose)
971 */
972static void smt_send_ecf_request(struct s_smc *smc, struct fddi_addr *dest,
973 int len)
974{
975 smc->sm.pend[SMT_TID_ECF] = smt_get_tid(smc) ;
976 smt_send_ecf(smc,dest, FC_SMT_INFO, smc->sm.pend[SMT_TID_ECF],
977 SMT_REQUEST,len) ;
978}
979#endif
980
981/*
982 * echo test
983 */
984static void smt_echo_test(struct s_smc *smc, int dna)
985{
986 u_long tid ;
987
988 smc->sm.pend[dna ? SMT_TID_ECF_DNA : SMT_TID_ECF_UNA] =
989 tid = smt_get_tid(smc) ;
990 smt_send_ecf(smc, dna ?
991 &smc->mib.m[MAC0].fddiMACDownstreamNbr :
992 &smc->mib.m[MAC0].fddiMACUpstreamNbr,
993 FC_SMT_INFO,tid, SMT_REQUEST, (SMT_TEST_ECHO_LEN & ~3)-8) ;
994}
995
996/*
997 * generate and send ECF
998 */
999static void smt_send_ecf(struct s_smc *smc, struct fddi_addr *dest, int fc,
1000 u_long tid, int type, int len)
1001/* struct fddi_addr *dest; dest address */
1002/* int fc; frame control */
1003/* u_long tid; transaction id */
1004/* int type; frame type */
1005/* int len; frame length */
1006{
1007 struct smt_ecf *ecf ;
1008 SMbuf *mb ;
1009
1010 if (!(mb = smt_build_frame(smc,SMT_ECF,type,SMT_ECF_LEN + len)))
1011 return ;
1012 ecf = smtod(mb, struct smt_ecf *) ;
1013
1014 smt_fill_echo(smc,&ecf->ec_echo,tid,len) ; /* set ECHO */
1015 ecf->smt.smt_dest = *dest ; /* destination address */
1016 ecf->smt.smt_tid = tid ; /* transaction ID */
1017 smc->mib.priv.fddiPRIVECF_Req_Tx++ ;
1018 smt_send_frame(smc,mb,fc,0) ;
1019}
1020
1021/*
1022 * generate and send SIF config response
1023 */
1024
1025static void smt_send_sif_config(struct s_smc *smc, struct fddi_addr *dest,
1026 u_long tid, int local)
1027/* struct fddi_addr *dest; dest address */
1028/* u_long tid; transaction id */
1029{
1030 struct smt_sif_config *sif ;
1031 SMbuf *mb ;
1032 int len ;
1033 if (!(mb = smt_build_frame(smc,SMT_SIF_CONFIG,SMT_REPLY,
1034 SIZEOF_SMT_SIF_CONFIG)))
1035 return ;
1036
1037 sif = smtod(mb, struct smt_sif_config *) ;
1038 smt_fill_timestamp(smc,&sif->ts) ; /* set time stamp */
1039 smt_fill_sde(smc,&sif->sde) ; /* set station descriptor */
1040 smt_fill_version(smc,&sif->version) ; /* set version information */
1041 smt_fill_state(smc,&sif->state) ; /* set state information */
1042 smt_fill_policy(smc,&sif->policy) ; /* set station policy */
1043 smt_fill_latency(smc,&sif->latency); /* set station latency */
1044 smt_fill_neighbor(smc,&sif->neighbor); /* set station neighbor */
1045 smt_fill_setcount(smc,&sif->setcount) ; /* set count */
1046 len = smt_fill_path(smc,&sif->path); /* set station path descriptor*/
1047 sif->smt.smt_dest = *dest ; /* destination address */
1048 sif->smt.smt_tid = tid ; /* transaction ID */
1049 smt_add_frame_len(mb,len) ; /* adjust length fields */
1050 dump_smt(smc,(struct smt_header *)sif,"SIF Configuration Reply") ;
1051 smt_send_frame(smc,mb,FC_SMT_INFO,local) ;
1052}
1053
1054/*
1055 * generate and send SIF operation response
1056 */
1057
1058static void smt_send_sif_operation(struct s_smc *smc, struct fddi_addr *dest,
1059 u_long tid, int local)
1060/* struct fddi_addr *dest; dest address */
1061/* u_long tid; transaction id */
1062{
1063 struct smt_sif_operation *sif ;
1064 SMbuf *mb ;
1065 int ports ;
1066 int i ;
1067
1068 ports = NUMPHYS ;
1069#ifndef CONCENTRATOR
1070 if (smc->s.sas == SMT_SAS)
1071 ports = 1 ;
1072#endif
1073
1074 if (!(mb = smt_build_frame(smc,SMT_SIF_OPER,SMT_REPLY,
1075 SIZEOF_SMT_SIF_OPERATION+ports*sizeof(struct smt_p_lem))))
1076 return ;
1077 sif = smtod(mb, struct smt_sif_operation *) ;
1078 smt_fill_timestamp(smc,&sif->ts) ; /* set time stamp */
1079 smt_fill_mac_status(smc,&sif->status) ; /* set mac status */
1080 smt_fill_mac_counter(smc,&sif->mc) ; /* set mac counter field */
1081 smt_fill_mac_fnc(smc,&sif->fnc) ; /* set frame not copied counter */
1082 smt_fill_manufacturer(smc,&sif->man) ; /* set manufacturer field */
1083 smt_fill_user(smc,&sif->user) ; /* set user field */
1084 smt_fill_setcount(smc,&sif->setcount) ; /* set count */
1085 /*
1086 * set link error mon information
1087 */
1088 if (ports == 1) {
1089 smt_fill_lem(smc,sif->lem,PS) ;
1090 }
1091 else {
1092 for (i = 0 ; i < ports ; i++) {
1093 smt_fill_lem(smc,&sif->lem[i],i) ;
1094 }
1095 }
1096
1097 sif->smt.smt_dest = *dest ; /* destination address */
1098 sif->smt.smt_tid = tid ; /* transaction ID */
1099 dump_smt(smc,(struct smt_header *)sif,"SIF Operation Reply") ;
1100 smt_send_frame(smc,mb,FC_SMT_INFO,local) ;
1101}
1102
1103/*
1104 * get and initialize SMT frame
1105 */
1106SMbuf *smt_build_frame(struct s_smc *smc, int class, int type,
1107 int length)
1108{
1109 SMbuf *mb ;
1110 struct smt_header *smt ;
1111
1112#if 0
1113 if (!smc->r.sm_ma_avail) {
1114 return 0;
1115 }
1116#endif
1117 if (!(mb = smt_get_mbuf(smc)))
1118 return mb;
1119
1120 mb->sm_len = length ;
1121 smt = smtod(mb, struct smt_header *) ;
1122 smt->smt_dest = fddi_broadcast ; /* set dest = broadcast */
1123 smt->smt_class = class ;
1124 smt->smt_type = type ;
1125 switch (class) {
1126 case SMT_NIF :
1127 case SMT_SIF_CONFIG :
1128 case SMT_SIF_OPER :
1129 case SMT_ECF :
1130 smt->smt_version = SMT_VID ;
1131 break ;
1132 default :
1133 smt->smt_version = SMT_VID_2 ;
1134 break ;
1135 }
1136 smt->smt_tid = smt_get_tid(smc) ; /* set transaction ID */
1137 smt->smt_pad = 0 ;
1138 smt->smt_len = length - sizeof(struct smt_header) ;
1139 return mb;
1140}
1141
1142static void smt_add_frame_len(SMbuf *mb, int len)
1143{
1144 struct smt_header *smt ;
1145
1146 smt = smtod(mb, struct smt_header *) ;
1147 smt->smt_len += len ;
1148 mb->sm_len += len ;
1149}
1150
1151
1152
1153/*
1154 * fill values in UNA parameter
1155 */
1156static void smt_fill_una(struct s_smc *smc, struct smt_p_una *una)
1157{
1158 SMTSETPARA(una,SMT_P_UNA) ;
1159 una->una_pad = 0 ;
1160 una->una_node = smc->mib.m[MAC0].fddiMACUpstreamNbr ;
1161}
1162
1163/*
1164 * fill values in SDE parameter
1165 */
1166static void smt_fill_sde(struct s_smc *smc, struct smt_p_sde *sde)
1167{
1168 SMTSETPARA(sde,SMT_P_SDE) ;
1169 sde->sde_non_master = smc->mib.fddiSMTNonMaster_Ct ;
1170 sde->sde_master = smc->mib.fddiSMTMaster_Ct ;
1171 sde->sde_mac_count = NUMMACS ; /* only 1 MAC */
1172#ifdef CONCENTRATOR
1173 sde->sde_type = SMT_SDE_CONCENTRATOR ;
1174#else
1175 sde->sde_type = SMT_SDE_STATION ;
1176#endif
1177}
1178
1179/*
1180 * fill in values in station state parameter
1181 */
1182static void smt_fill_state(struct s_smc *smc, struct smt_p_state *state)
1183{
1184 int top ;
1185 int twist ;
1186
1187 SMTSETPARA(state,SMT_P_STATE) ;
1188 state->st_pad = 0 ;
1189
1190 /* determine topology */
1191 top = 0 ;
1192 if (smc->mib.fddiSMTPeerWrapFlag) {
1193 top |= SMT_ST_WRAPPED ; /* state wrapped */
1194 }
1195#ifdef CONCENTRATOR
1196 if (cfm_status_unattached(smc)) {
1197 top |= SMT_ST_UNATTACHED ; /* unattached concentrator */
1198 }
1199#endif
1200 if ((twist = pcm_status_twisted(smc)) & 1) {
1201 top |= SMT_ST_TWISTED_A ; /* twisted cable */
1202 }
1203 if (twist & 2) {
1204 top |= SMT_ST_TWISTED_B ; /* twisted cable */
1205 }
1206#ifdef OPT_SRF
1207 top |= SMT_ST_SRF ;
1208#endif
1209 if (pcm_rooted_station(smc))
1210 top |= SMT_ST_ROOTED_S ;
1211 if (smc->mib.a[0].fddiPATHSbaPayload != 0)
1212 top |= SMT_ST_SYNC_SERVICE ;
1213 state->st_topology = top ;
1214 state->st_dupl_addr =
1215 ((smc->mib.m[MAC0].fddiMACDA_Flag ? SMT_ST_MY_DUPA : 0 ) |
1216 (smc->mib.m[MAC0].fddiMACUNDA_Flag ? SMT_ST_UNA_DUPA : 0)) ;
1217}
1218
1219/*
1220 * fill values in timestamp parameter
1221 */
1222static void smt_fill_timestamp(struct s_smc *smc, struct smt_p_timestamp *ts)
1223{
1224
1225 SMTSETPARA(ts,SMT_P_TIMESTAMP) ;
1226 smt_set_timestamp(smc,ts->ts_time) ;
1227}
1228
1229void smt_set_timestamp(struct s_smc *smc, u_char *p)
1230{
1231 u_long time ;
1232 u_long utime ;
1233
1234 /*
1235 * timestamp is 64 bits long ; resolution is 80 nS
1236 * our clock resolution is 10mS
1237 * 10mS/80ns = 125000 ~ 2^17 = 131072
1238 */
1239 utime = smt_get_time() ;
1240 time = utime * 100 ;
1241 time /= TICKS_PER_SECOND ;
1242 p[0] = 0 ;
1243 p[1] = (u_char)((time>>(8+8+8+8-1)) & 1) ;
1244 p[2] = (u_char)(time>>(8+8+8-1)) ;
1245 p[3] = (u_char)(time>>(8+8-1)) ;
1246 p[4] = (u_char)(time>>(8-1)) ;
1247 p[5] = (u_char)(time<<1) ;
1248 p[6] = (u_char)(smc->sm.uniq_ticks>>8) ;
1249 p[7] = (u_char)smc->sm.uniq_ticks ;
1250 /*
1251 * make sure we don't wrap: restart whenever the upper digits change
1252 */
1253 if (utime != smc->sm.uniq_time) {
1254 smc->sm.uniq_ticks = 0 ;
1255 }
1256 smc->sm.uniq_ticks++ ;
1257 smc->sm.uniq_time = utime ;
1258}
1259
1260/*
1261 * fill values in station policy parameter
1262 */
1263static void smt_fill_policy(struct s_smc *smc, struct smt_p_policy *policy)
1264{
1265 int i ;
1266 const u_char *map ;
1267 u_short in ;
1268 u_short out ;
1269
1270 /*
1271 * MIB para 101b (fddiSMTConnectionPolicy) coding
1272 * is different from 0005 coding
1273 */
1274 static const u_char ansi_weirdness[16] = {
1275 0,7,5,3,8,1,6,4,9,10,2,11,12,13,14,15
1276 } ;
1277 SMTSETPARA(policy,SMT_P_POLICY) ;
1278
1279 out = 0 ;
1280 in = smc->mib.fddiSMTConnectionPolicy ;
1281 for (i = 0, map = ansi_weirdness ; i < 16 ; i++) {
1282 if (in & 1)
1283 out |= (1<<*map) ;
1284 in >>= 1 ;
1285 map++ ;
1286 }
1287 policy->pl_config = smc->mib.fddiSMTConfigPolicy ;
1288 policy->pl_connect = out ;
1289}
1290
1291/*
1292 * fill values in latency equivalent parameter
1293 */
1294static void smt_fill_latency(struct s_smc *smc, struct smt_p_latency *latency)
1295{
1296 SMTSETPARA(latency,SMT_P_LATENCY) ;
1297
1298 latency->lt_phyout_idx1 = phy_index(smc,0) ;
1299 latency->lt_latency1 = 10 ; /* in octets (byte clock) */
1300 /*
1301 * note: latency has two phy entries by definition
1302 * for a SAS, the 2nd one is null
1303 */
1304 if (smc->s.sas == SMT_DAS) {
1305 latency->lt_phyout_idx2 = phy_index(smc,1) ;
1306 latency->lt_latency2 = 10 ; /* in octets (byte clock) */
1307 }
1308 else {
1309 latency->lt_phyout_idx2 = 0 ;
1310 latency->lt_latency2 = 0 ;
1311 }
1312}
1313
1314/*
1315 * fill values in MAC neighbors parameter
1316 */
1317static void smt_fill_neighbor(struct s_smc *smc, struct smt_p_neighbor *neighbor)
1318{
1319 SMTSETPARA(neighbor,SMT_P_NEIGHBORS) ;
1320
1321 neighbor->nb_mib_index = INDEX_MAC ;
1322 neighbor->nb_mac_index = mac_index(smc,1) ;
1323 neighbor->nb_una = smc->mib.m[MAC0].fddiMACUpstreamNbr ;
1324 neighbor->nb_dna = smc->mib.m[MAC0].fddiMACDownstreamNbr ;
1325}
1326
1327/*
1328 * fill values in path descriptor
1329 */
1330#ifdef CONCENTRATOR
1331#define ALLPHYS NUMPHYS
1332#else
1333#define ALLPHYS ((smc->s.sas == SMT_SAS) ? 1 : 2)
1334#endif
1335
1336static int smt_fill_path(struct s_smc *smc, struct smt_p_path *path)
1337{
1338 SK_LOC_DECL(int,type) ;
1339 SK_LOC_DECL(int,state) ;
1340 SK_LOC_DECL(int,remote) ;
1341 SK_LOC_DECL(int,mac) ;
1342 int len ;
1343 int p ;
1344 int physp ;
1345 struct smt_phy_rec *phy ;
1346 struct smt_mac_rec *pd_mac ;
1347
1348 len = PARA_LEN +
1349 sizeof(struct smt_mac_rec) * NUMMACS +
1350 sizeof(struct smt_phy_rec) * ALLPHYS ;
1351 path->para.p_type = SMT_P_PATH ;
1352 path->para.p_len = len - PARA_LEN ;
1353
1354 /* PHYs */
1355 for (p = 0,phy = path->pd_phy ; p < ALLPHYS ; p++, phy++) {
1356 physp = p ;
1357#ifndef CONCENTRATOR
1358 if (smc->s.sas == SMT_SAS)
1359 physp = PS ;
1360#endif
1361 pcm_status_state(smc,physp,&type,&state,&remote,&mac) ;
1362#ifdef LITTLE_ENDIAN
1363 phy->phy_mib_index = smt_swap_short((u_short)p+INDEX_PORT) ;
1364#else
1365 phy->phy_mib_index = p+INDEX_PORT ;
1366#endif
1367 phy->phy_type = type ;
1368 phy->phy_connect_state = state ;
1369 phy->phy_remote_type = remote ;
1370 phy->phy_remote_mac = mac ;
1371 phy->phy_resource_idx = phy_con_resource_index(smc,p) ;
1372 }
1373
1374 /* MAC */
1375 pd_mac = (struct smt_mac_rec *) phy ;
1376 pd_mac->mac_addr = smc->mib.m[MAC0].fddiMACSMTAddress ;
1377 pd_mac->mac_resource_idx = mac_con_resource_index(smc,1) ;
1378 return len;
1379}
1380
1381/*
1382 * fill values in mac status
1383 */
1384static void smt_fill_mac_status(struct s_smc *smc, struct smt_p_mac_status *st)
1385{
1386 SMTSETPARA(st,SMT_P_MAC_STATUS) ;
1387
1388 st->st_mib_index = INDEX_MAC ;
1389 st->st_mac_index = mac_index(smc,1) ;
1390
1391 mac_update_counter(smc) ;
1392 /*
1393 * timer values are represented in SMT as 2's complement numbers
1394 * units : internal : 2's complement BCLK
1395 */
1396 st->st_t_req = smc->mib.m[MAC0].fddiMACT_Req ;
1397 st->st_t_neg = smc->mib.m[MAC0].fddiMACT_Neg ;
1398 st->st_t_max = smc->mib.m[MAC0].fddiMACT_Max ;
1399 st->st_tvx_value = smc->mib.m[MAC0].fddiMACTvxValue ;
1400 st->st_t_min = smc->mib.m[MAC0].fddiMACT_Min ;
1401
1402 st->st_sba = smc->mib.a[PATH0].fddiPATHSbaPayload ;
1403 st->st_frame_ct = smc->mib.m[MAC0].fddiMACFrame_Ct ;
1404 st->st_error_ct = smc->mib.m[MAC0].fddiMACError_Ct ;
1405 st->st_lost_ct = smc->mib.m[MAC0].fddiMACLost_Ct ;
1406}
1407
1408/*
1409 * fill values in LEM status
1410 */
1411static void smt_fill_lem(struct s_smc *smc, struct smt_p_lem *lem, int phy)
1412{
1413 struct fddi_mib_p *mib ;
1414
1415 mib = smc->y[phy].mib ;
1416
1417 SMTSETPARA(lem,SMT_P_LEM) ;
1418 lem->lem_mib_index = phy+INDEX_PORT ;
1419 lem->lem_phy_index = phy_index(smc,phy) ;
1420 lem->lem_pad2 = 0 ;
1421 lem->lem_cutoff = mib->fddiPORTLer_Cutoff ;
1422 lem->lem_alarm = mib->fddiPORTLer_Alarm ;
1423 /* long term bit error rate */
1424 lem->lem_estimate = mib->fddiPORTLer_Estimate ;
1425 /* # of rejected connections */
1426 lem->lem_reject_ct = mib->fddiPORTLem_Reject_Ct ;
1427 lem->lem_ct = mib->fddiPORTLem_Ct ; /* total number of errors */
1428}
1429
1430/*
1431 * fill version parameter
1432 */
1433static void smt_fill_version(struct s_smc *smc, struct smt_p_version *vers)
1434{
1435 SK_UNUSED(smc) ;
1436 SMTSETPARA(vers,SMT_P_VERSION) ;
1437 vers->v_pad = 0 ;
1438 vers->v_n = 1 ; /* one version is enough .. */
1439 vers->v_index = 1 ;
1440 vers->v_version[0] = SMT_VID_2 ;
1441 vers->v_pad2 = 0 ;
1442}
1443
1444#ifdef SMT6_10
1445/*
1446 * fill frame status capabilities
1447 */
1448/*
1449 * note: this para 200B is NOT in swap table, because it's also set in
1450 * PMF add_para
1451 */
1452static void smt_fill_fsc(struct s_smc *smc, struct smt_p_fsc *fsc)
1453{
1454 SK_UNUSED(smc) ;
1455 SMTSETPARA(fsc,SMT_P_FSC) ;
1456 fsc->fsc_pad0 = 0 ;
1457 fsc->fsc_mac_index = INDEX_MAC ; /* this is MIB ; MIB is NOT
1458 * mac_index ()i !
1459 */
1460 fsc->fsc_pad1 = 0 ;
1461 fsc->fsc_value = FSC_TYPE0 ; /* "normal" node */
1462#ifdef LITTLE_ENDIAN
1463 fsc->fsc_mac_index = smt_swap_short(INDEX_MAC) ;
1464 fsc->fsc_value = smt_swap_short(FSC_TYPE0) ;
1465#endif
1466}
1467#endif
1468
1469/*
1470 * fill mac counter field
1471 */
1472static void smt_fill_mac_counter(struct s_smc *smc, struct smt_p_mac_counter *mc)
1473{
1474 SMTSETPARA(mc,SMT_P_MAC_COUNTER) ;
1475 mc->mc_mib_index = INDEX_MAC ;
1476 mc->mc_index = mac_index(smc,1) ;
1477 mc->mc_receive_ct = smc->mib.m[MAC0].fddiMACCopied_Ct ;
1478 mc->mc_transmit_ct = smc->mib.m[MAC0].fddiMACTransmit_Ct ;
1479}
1480
1481/*
1482 * fill mac frame not copied counter
1483 */
1484static void smt_fill_mac_fnc(struct s_smc *smc, struct smt_p_mac_fnc *fnc)
1485{
1486 SMTSETPARA(fnc,SMT_P_MAC_FNC) ;
1487 fnc->nc_mib_index = INDEX_MAC ;
1488 fnc->nc_index = mac_index(smc,1) ;
1489 fnc->nc_counter = smc->mib.m[MAC0].fddiMACNotCopied_Ct ;
1490}
1491
1492
1493/*
1494 * fill manufacturer field
1495 */
1496static void smt_fill_manufacturer(struct s_smc *smc,
1497 struct smp_p_manufacturer *man)
1498{
1499 SMTSETPARA(man,SMT_P_MANUFACTURER) ;
1500 memcpy((char *) man->mf_data,
1501 (char *) smc->mib.fddiSMTManufacturerData,
1502 sizeof(man->mf_data)) ;
1503}
1504
1505/*
1506 * fill user field
1507 */
1508static void smt_fill_user(struct s_smc *smc, struct smp_p_user *user)
1509{
1510 SMTSETPARA(user,SMT_P_USER) ;
1511 memcpy((char *) user->us_data,
1512 (char *) smc->mib.fddiSMTUserData,
1513 sizeof(user->us_data)) ;
1514}
1515
1516/*
1517 * fill set count
1518 */
1519static void smt_fill_setcount(struct s_smc *smc, struct smt_p_setcount *setcount)
1520{
1521 SK_UNUSED(smc) ;
1522 SMTSETPARA(setcount,SMT_P_SETCOUNT) ;
1523 setcount->count = smc->mib.fddiSMTSetCount.count ;
1524 memcpy((char *)setcount->timestamp,
1525 (char *)smc->mib.fddiSMTSetCount.timestamp,8) ;
1526}
1527
1528/*
1529 * fill echo data
1530 */
1531static void smt_fill_echo(struct s_smc *smc, struct smt_p_echo *echo, u_long seed,
1532 int len)
1533{
1534 u_char *p ;
1535
1536 SK_UNUSED(smc) ;
1537 SMTSETPARA(echo,SMT_P_ECHODATA) ;
1538 echo->para.p_len = len ;
1539 for (p = echo->ec_data ; len ; len--) {
1540 *p++ = (u_char) seed ;
1541 seed += 13 ;
1542 }
1543}
1544
1545/*
1546 * clear DNA and UNA
1547 * called from CFM if configuration changes
1548 */
1549static void smt_clear_una_dna(struct s_smc *smc)
1550{
1551 smc->mib.m[MAC0].fddiMACUpstreamNbr = SMT_Unknown ;
1552 smc->mib.m[MAC0].fddiMACDownstreamNbr = SMT_Unknown ;
1553}
1554
1555static void smt_clear_old_una_dna(struct s_smc *smc)
1556{
1557 smc->mib.m[MAC0].fddiMACOldUpstreamNbr = SMT_Unknown ;
1558 smc->mib.m[MAC0].fddiMACOldDownstreamNbr = SMT_Unknown ;
1559}
1560
1561u_long smt_get_tid(struct s_smc *smc)
1562{
1563 u_long tid ;
1564 while ((tid = ++(smc->sm.smt_tid) ^ SMT_TID_MAGIC) == 0)
1565 ;
1566 return tid & 0x3fffffffL;
1567}
1568
1569
1570/*
1571 * table of parameter lengths
1572 */
1573static const struct smt_pdef {
1574 int ptype ;
1575 int plen ;
1576 const char *pswap ;
1577} smt_pdef[] = {
1578 { SMT_P_UNA, sizeof(struct smt_p_una) ,
1579 SWAP_SMT_P_UNA } ,
1580 { SMT_P_SDE, sizeof(struct smt_p_sde) ,
1581 SWAP_SMT_P_SDE } ,
1582 { SMT_P_STATE, sizeof(struct smt_p_state) ,
1583 SWAP_SMT_P_STATE } ,
1584 { SMT_P_TIMESTAMP,sizeof(struct smt_p_timestamp) ,
1585 SWAP_SMT_P_TIMESTAMP } ,
1586 { SMT_P_POLICY, sizeof(struct smt_p_policy) ,
1587 SWAP_SMT_P_POLICY } ,
1588 { SMT_P_LATENCY, sizeof(struct smt_p_latency) ,
1589 SWAP_SMT_P_LATENCY } ,
1590 { SMT_P_NEIGHBORS,sizeof(struct smt_p_neighbor) ,
1591 SWAP_SMT_P_NEIGHBORS } ,
1592 { SMT_P_PATH, sizeof(struct smt_p_path) ,
1593 SWAP_SMT_P_PATH } ,
1594 { SMT_P_MAC_STATUS,sizeof(struct smt_p_mac_status) ,
1595 SWAP_SMT_P_MAC_STATUS } ,
1596 { SMT_P_LEM, sizeof(struct smt_p_lem) ,
1597 SWAP_SMT_P_LEM } ,
1598 { SMT_P_MAC_COUNTER,sizeof(struct smt_p_mac_counter) ,
1599 SWAP_SMT_P_MAC_COUNTER } ,
1600 { SMT_P_MAC_FNC,sizeof(struct smt_p_mac_fnc) ,
1601 SWAP_SMT_P_MAC_FNC } ,
1602 { SMT_P_PRIORITY,sizeof(struct smt_p_priority) ,
1603 SWAP_SMT_P_PRIORITY } ,
1604 { SMT_P_EB,sizeof(struct smt_p_eb) ,
1605 SWAP_SMT_P_EB } ,
1606 { SMT_P_MANUFACTURER,sizeof(struct smp_p_manufacturer) ,
1607 SWAP_SMT_P_MANUFACTURER } ,
1608 { SMT_P_REASON, sizeof(struct smt_p_reason) ,
1609 SWAP_SMT_P_REASON } ,
1610 { SMT_P_REFUSED, sizeof(struct smt_p_refused) ,
1611 SWAP_SMT_P_REFUSED } ,
1612 { SMT_P_VERSION, sizeof(struct smt_p_version) ,
1613 SWAP_SMT_P_VERSION } ,
1614#ifdef ESS
1615 { SMT_P0015, sizeof(struct smt_p_0015) , SWAP_SMT_P0015 } ,
1616 { SMT_P0016, sizeof(struct smt_p_0016) , SWAP_SMT_P0016 } ,
1617 { SMT_P0017, sizeof(struct smt_p_0017) , SWAP_SMT_P0017 } ,
1618 { SMT_P0018, sizeof(struct smt_p_0018) , SWAP_SMT_P0018 } ,
1619 { SMT_P0019, sizeof(struct smt_p_0019) , SWAP_SMT_P0019 } ,
1620 { SMT_P001A, sizeof(struct smt_p_001a) , SWAP_SMT_P001A } ,
1621 { SMT_P001B, sizeof(struct smt_p_001b) , SWAP_SMT_P001B } ,
1622 { SMT_P001C, sizeof(struct smt_p_001c) , SWAP_SMT_P001C } ,
1623 { SMT_P001D, sizeof(struct smt_p_001d) , SWAP_SMT_P001D } ,
1624#endif
1625#if 0
1626 { SMT_P_FSC, sizeof(struct smt_p_fsc) ,
1627 SWAP_SMT_P_FSC } ,
1628#endif
1629
1630 { SMT_P_SETCOUNT,0, SWAP_SMT_P_SETCOUNT } ,
1631 { SMT_P1048, 0, SWAP_SMT_P1048 } ,
1632 { SMT_P208C, 0, SWAP_SMT_P208C } ,
1633 { SMT_P208D, 0, SWAP_SMT_P208D } ,
1634 { SMT_P208E, 0, SWAP_SMT_P208E } ,
1635 { SMT_P208F, 0, SWAP_SMT_P208F } ,
1636 { SMT_P2090, 0, SWAP_SMT_P2090 } ,
1637#ifdef ESS
1638 { SMT_P320B, sizeof(struct smt_p_320b) , SWAP_SMT_P320B } ,
1639 { SMT_P320F, sizeof(struct smt_p_320f) , SWAP_SMT_P320F } ,
1640 { SMT_P3210, sizeof(struct smt_p_3210) , SWAP_SMT_P3210 } ,
1641#endif
1642 { SMT_P4050, 0, SWAP_SMT_P4050 } ,
1643 { SMT_P4051, 0, SWAP_SMT_P4051 } ,
1644 { SMT_P4052, 0, SWAP_SMT_P4052 } ,
1645 { SMT_P4053, 0, SWAP_SMT_P4053 } ,
1646} ;
1647
1648#define N_SMT_PLEN ARRAY_SIZE(smt_pdef)
1649
1650int smt_check_para(struct s_smc *smc, struct smt_header *sm,
1651 const u_short list[])
1652{
1653 const u_short *p = list ;
1654 while (*p) {
1655 if (!sm_to_para(smc,sm,(int) *p)) {
1656 DB_SMT("SMT: smt_check_para - missing para %x\n",*p,0);
1657 return -1;
1658 }
1659 p++ ;
1660 }
1661 return 0;
1662}
1663
1664void *sm_to_para(struct s_smc *smc, struct smt_header *sm, int para)
1665{
1666 char *p ;
1667 int len ;
1668 int plen ;
1669 void *found = NULL;
1670
1671 SK_UNUSED(smc) ;
1672
1673 len = sm->smt_len ;
1674 p = (char *)(sm+1) ; /* pointer to info */
1675 while (len > 0 ) {
1676 if (((struct smt_para *)p)->p_type == para)
1677 found = (void *) p ;
1678 plen = ((struct smt_para *)p)->p_len + PARA_LEN ;
1679 p += plen ;
1680 len -= plen ;
1681 if (len < 0) {
1682 DB_SMT("SMT : sm_to_para - length error %d\n",plen,0) ;
1683 return NULL;
1684 }
1685 if ((plen & 3) && (para != SMT_P_ECHODATA)) {
1686 DB_SMT("SMT : sm_to_para - odd length %d\n",plen,0) ;
1687 return NULL;
1688 }
1689 if (found)
1690 return found;
1691 }
1692 return NULL;
1693}
1694
1695#if 0
1696/*
1697 * send ANTC data test frame
1698 */
1699void fddi_send_antc(struct s_smc *smc, struct fddi_addr *dest)
1700{
1701 SK_UNUSED(smc) ;
1702 SK_UNUSED(dest) ;
1703#if 0
1704 SMbuf *mb ;
1705 struct smt_header *smt ;
1706 int i ;
1707 char *p ;
1708
1709 mb = smt_get_mbuf() ;
1710 mb->sm_len = 3000+12 ;
1711 p = smtod(mb, char *) + 12 ;
1712 for (i = 0 ; i < 3000 ; i++)
1713 *p++ = 1 << (i&7) ;
1714
1715 smt = smtod(mb, struct smt_header *) ;
1716 smt->smt_dest = *dest ;
1717 smt->smt_source = smc->mib.m[MAC0].fddiMACSMTAddress ;
1718 smt_send_mbuf(smc,mb,FC_ASYNC_LLC) ;
1719#endif
1720}
1721#endif
1722
1723#ifdef DEBUG
1724char *addr_to_string(struct fddi_addr *addr)
1725{
1726 int i ;
1727 static char string[6*3] = "****" ;
1728
1729 for (i = 0 ; i < 6 ; i++) {
1730 string[i * 3] = hex_asc_hi(addr->a[i]);
1731 string[i * 3 + 1] = hex_asc_lo(addr->a[i]);
1732 string[i * 3 + 2] = ':';
1733 }
1734 string[5 * 3 + 2] = 0;
1735 return string;
1736}
1737#endif
1738
1739#ifdef AM29K
1740int smt_ifconfig(int argc, char *argv[])
1741{
1742 if (argc >= 2 && !strcmp(argv[0],"opt_bypass") &&
1743 !strcmp(argv[1],"yes")) {
1744 smc->mib.fddiSMTBypassPresent = 1 ;
1745 return 0;
1746 }
1747 return amdfddi_config(0, argc, argv);
1748}
1749#endif
1750
1751/*
1752 * return static mac index
1753 */
1754static int mac_index(struct s_smc *smc, int mac)
1755{
1756 SK_UNUSED(mac) ;
1757#ifdef CONCENTRATOR
1758 SK_UNUSED(smc) ;
1759 return NUMPHYS + 1;
1760#else
1761 return (smc->s.sas == SMT_SAS) ? 2 : 3;
1762#endif
1763}
1764
1765/*
1766 * return static phy index
1767 */
1768static int phy_index(struct s_smc *smc, int phy)
1769{
1770 SK_UNUSED(smc) ;
1771 return phy + 1;
1772}
1773
1774/*
1775 * return dynamic mac connection resource index
1776 */
1777static int mac_con_resource_index(struct s_smc *smc, int mac)
1778{
1779#ifdef CONCENTRATOR
1780 SK_UNUSED(smc) ;
1781 SK_UNUSED(mac) ;
1782 return entity_to_index(smc, cem_get_downstream(smc, ENTITY_MAC));
1783#else
1784 SK_UNUSED(mac) ;
1785 switch (smc->mib.fddiSMTCF_State) {
1786 case SC9_C_WRAP_A :
1787 case SC5_THRU_B :
1788 case SC11_C_WRAP_S :
1789 return 1;
1790 case SC10_C_WRAP_B :
1791 case SC4_THRU_A :
1792 return 2;
1793 }
1794 return smc->s.sas == SMT_SAS ? 2 : 3;
1795#endif
1796}
1797
1798/*
1799 * return dynamic phy connection resource index
1800 */
1801static int phy_con_resource_index(struct s_smc *smc, int phy)
1802{
1803#ifdef CONCENTRATOR
1804 return entity_to_index(smc, cem_get_downstream(smc, ENTITY_PHY(phy))) ;
1805#else
1806 switch (smc->mib.fddiSMTCF_State) {
1807 case SC9_C_WRAP_A :
1808 return phy == PA ? 3 : 2;
1809 case SC10_C_WRAP_B :
1810 return phy == PA ? 1 : 3;
1811 case SC4_THRU_A :
1812 return phy == PA ? 3 : 1;
1813 case SC5_THRU_B :
1814 return phy == PA ? 2 : 3;
1815 case SC11_C_WRAP_S :
1816 return 2;
1817 }
1818 return phy;
1819#endif
1820}
1821
1822#ifdef CONCENTRATOR
1823static int entity_to_index(struct s_smc *smc, int e)
1824{
1825 if (e == ENTITY_MAC)
1826 return mac_index(smc, 1);
1827 else
1828 return phy_index(smc, e - ENTITY_PHY(0));
1829}
1830#endif
1831
1832#ifdef LITTLE_ENDIAN
1833static int smt_swap_short(u_short s)
1834{
1835 return ((s>>8)&0xff) | ((s&0xff)<<8);
1836}
1837
1838void smt_swap_para(struct smt_header *sm, int len, int direction)
1839/* int direction; 0 encode 1 decode */
1840{
1841 struct smt_para *pa ;
1842 const struct smt_pdef *pd ;
1843 char *p ;
1844 int plen ;
1845 int type ;
1846 int i ;
1847
1848/* printf("smt_swap_para sm %x len %d dir %d\n",
1849 sm,len,direction) ;
1850 */
1851 smt_string_swap((char *)sm,SWAP_SMTHEADER,len) ;
1852
1853 /* swap args */
1854 len -= sizeof(struct smt_header) ;
1855
1856 p = (char *) (sm + 1) ;
1857 while (len > 0) {
1858 pa = (struct smt_para *) p ;
1859 plen = pa->p_len ;
1860 type = pa->p_type ;
1861 pa->p_type = smt_swap_short(pa->p_type) ;
1862 pa->p_len = smt_swap_short(pa->p_len) ;
1863 if (direction) {
1864 plen = pa->p_len ;
1865 type = pa->p_type ;
1866 }
1867 /*
1868 * note: paras can have 0 length !
1869 */
1870 if (plen < 0)
1871 break ;
1872 plen += PARA_LEN ;
1873 for (i = N_SMT_PLEN, pd = smt_pdef; i ; i--,pd++) {
1874 if (pd->ptype == type)
1875 break ;
1876 }
1877 if (i && pd->pswap) {
1878 smt_string_swap(p+PARA_LEN,pd->pswap,len) ;
1879 }
1880 len -= plen ;
1881 p += plen ;
1882 }
1883}
1884
1885static void smt_string_swap(char *data, const char *format, int len)
1886{
1887 const char *open_paren = NULL ;
1888 int x ;
1889
1890 while (len > 0 && *format) {
1891 switch (*format) {
1892 case '[' :
1893 open_paren = format ;
1894 break ;
1895 case ']' :
1896 format = open_paren ;
1897 break ;
1898 case '1' :
1899 case '2' :
1900 case '3' :
1901 case '4' :
1902 case '5' :
1903 case '6' :
1904 case '7' :
1905 case '8' :
1906 case '9' :
1907 data += *format - '0' ;
1908 len -= *format - '0' ;
1909 break ;
1910 case 'c':
1911 data++ ;
1912 len-- ;
1913 break ;
1914 case 's' :
1915 x = data[0] ;
1916 data[0] = data[1] ;
1917 data[1] = x ;
1918 data += 2 ;
1919 len -= 2 ;
1920 break ;
1921 case 'l' :
1922 x = data[0] ;
1923 data[0] = data[3] ;
1924 data[3] = x ;
1925 x = data[1] ;
1926 data[1] = data[2] ;
1927 data[2] = x ;
1928 data += 4 ;
1929 len -= 4 ;
1930 break ;
1931 }
1932 format++ ;
1933 }
1934}
1935#else
1936void smt_swap_para(struct smt_header *sm, int len, int direction)
1937/* int direction; 0 encode 1 decode */
1938{
1939 SK_UNUSED(sm) ;
1940 SK_UNUSED(len) ;
1941 SK_UNUSED(direction) ;
1942}
1943#endif
1944
1945/*
1946 * PMF actions
1947 */
1948int smt_action(struct s_smc *smc, int class, int code, int index)
1949{
1950 int event ;
1951 int port ;
1952 DB_SMT("SMT: action %d code %d\n",class,code) ;
1953 switch(class) {
1954 case SMT_STATION_ACTION :
1955 switch(code) {
1956 case SMT_STATION_ACTION_CONNECT :
1957 smc->mib.fddiSMTRemoteDisconnectFlag = FALSE ;
1958 queue_event(smc,EVENT_ECM,EC_CONNECT) ;
1959 break ;
1960 case SMT_STATION_ACTION_DISCONNECT :
1961 queue_event(smc,EVENT_ECM,EC_DISCONNECT) ;
1962 smc->mib.fddiSMTRemoteDisconnectFlag = TRUE ;
1963 RS_SET(smc,RS_DISCONNECT) ;
1964 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
1965 FDDI_SMT_EVENT, (u_long) FDDI_REMOTE_DISCONNECT,
1966 smt_get_event_word(smc));
1967 break ;
1968 case SMT_STATION_ACTION_PATHTEST :
1969 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
1970 FDDI_SMT_EVENT, (u_long) FDDI_PATH_TEST,
1971 smt_get_event_word(smc));
1972 break ;
1973 case SMT_STATION_ACTION_SELFTEST :
1974 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
1975 FDDI_SMT_EVENT, (u_long) FDDI_REMOTE_SELF_TEST,
1976 smt_get_event_word(smc));
1977 break ;
1978 case SMT_STATION_ACTION_DISABLE_A :
1979 if (smc->y[PA].pc_mode == PM_PEER) {
1980 RS_SET(smc,RS_EVENT) ;
1981 queue_event(smc,EVENT_PCM+PA,PC_DISABLE) ;
1982 }
1983 break ;
1984 case SMT_STATION_ACTION_DISABLE_B :
1985 if (smc->y[PB].pc_mode == PM_PEER) {
1986 RS_SET(smc,RS_EVENT) ;
1987 queue_event(smc,EVENT_PCM+PB,PC_DISABLE) ;
1988 }
1989 break ;
1990 case SMT_STATION_ACTION_DISABLE_M :
1991 for (port = 0 ; port < NUMPHYS ; port++) {
1992 if (smc->mib.p[port].fddiPORTMy_Type != TM)
1993 continue ;
1994 RS_SET(smc,RS_EVENT) ;
1995 queue_event(smc,EVENT_PCM+port,PC_DISABLE) ;
1996 }
1997 break ;
1998 default :
1999 return 1;
2000 }
2001 break ;
2002 case SMT_PORT_ACTION :
2003 switch(code) {
2004 case SMT_PORT_ACTION_ENABLE :
2005 event = PC_ENABLE ;
2006 break ;
2007 case SMT_PORT_ACTION_DISABLE :
2008 event = PC_DISABLE ;
2009 break ;
2010 case SMT_PORT_ACTION_MAINT :
2011 event = PC_MAINT ;
2012 break ;
2013 case SMT_PORT_ACTION_START :
2014 event = PC_START ;
2015 break ;
2016 case SMT_PORT_ACTION_STOP :
2017 event = PC_STOP ;
2018 break ;
2019 default :
2020 return 1;
2021 }
2022 queue_event(smc,EVENT_PCM+index,event) ;
2023 break ;
2024 default :
2025 return 1;
2026 }
2027 return 0;
2028}
2029
2030/*
2031 * canonical conversion of <len> bytes beginning form *data
2032 */
2033#ifdef USE_CAN_ADDR
2034static void hwm_conv_can(struct s_smc *smc, char *data, int len)
2035{
2036 int i ;
2037
2038 SK_UNUSED(smc) ;
2039
2040 for (i = len; i ; i--, data++)
2041 *data = bitrev8(*data);
2042}
2043#endif
2044
2045#endif /* no SLIM_SMT */
2046
diff --git a/drivers/net/skfp/smtdef.c b/drivers/net/skfp/smtdef.c
deleted file mode 100644
index 1acab0b368e3..000000000000
--- a/drivers/net/skfp/smtdef.c
+++ /dev/null
@@ -1,355 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 SMT/CMT defaults
19*/
20
21#include "h/types.h"
22#include "h/fddi.h"
23#include "h/smc.h"
24
25#ifndef OEM_USER_DATA
26#define OEM_USER_DATA "SK-NET FDDI V2.0 Userdata"
27#endif
28
29#ifndef lint
30static const char ID_sccs[] = "@(#)smtdef.c 2.53 99/08/11 (C) SK " ;
31#endif
32
33/*
34 * defaults
35 */
36#define TTMS(x) ((u_long)(x)*1000L)
37#define TTS(x) ((u_long)(x)*1000000L)
38#define TTUS(x) ((u_long)(x))
39
40#define DEFAULT_TB_MIN TTMS(5)
41#define DEFAULT_TB_MAX TTMS(50)
42#define DEFAULT_C_MIN TTUS(1600)
43#define DEFAULT_T_OUT TTMS(100+5)
44#define DEFAULT_TL_MIN TTUS(30)
45#define DEFAULT_LC_SHORT TTMS(50+5)
46#define DEFAULT_LC_MEDIUM TTMS(500+20)
47#define DEFAULT_LC_LONG TTS(5)+TTMS(50)
48#define DEFAULT_LC_EXTENDED TTS(50)+TTMS(50)
49#define DEFAULT_T_NEXT_9 TTMS(200+10)
50#define DEFAULT_NS_MAX TTUS(1310)
51#define DEFAULT_I_MAX TTMS(25)
52#define DEFAULT_IN_MAX TTMS(40)
53#define DEFAULT_TD_MIN TTMS(5)
54#define DEFAULT_T_NON_OP TTS(1)
55#define DEFAULT_T_STUCK TTS(8)
56#define DEFAULT_T_DIRECT TTMS(370)
57#define DEFAULT_T_JAM TTMS(370)
58#define DEFAULT_T_ANNOUNCE TTMS(2500)
59#define DEFAULT_D_MAX TTUS(1617)
60#define DEFAULT_LEM_ALARM (8)
61#define DEFAULT_LEM_CUTOFF (7)
62#define DEFAULT_TEST_DONE TTS(1)
63#define DEFAULT_CHECK_POLL TTS(1)
64#define DEFAULT_POLL TTMS(50)
65
66/*
67 * LCT errors threshold
68 */
69#define DEFAULT_LCT_SHORT 1
70#define DEFAULT_LCT_MEDIUM 3
71#define DEFAULT_LCT_LONG 5
72#define DEFAULT_LCT_EXTEND 50
73
74/* Forward declarations */
75void smt_reset_defaults(struct s_smc *smc, int level);
76static void smt_init_mib(struct s_smc *smc, int level);
77static int set_min_max(int maxflag, u_long mib, u_long limit, u_long *oper);
78
79#define MS2BCLK(x) ((x)*12500L)
80#define US2BCLK(x) ((x)*1250L)
81
82void smt_reset_defaults(struct s_smc *smc, int level)
83{
84 struct smt_config *smt ;
85 int i ;
86 u_long smt_boot_time;
87
88
89 smt_init_mib(smc,level) ;
90
91 smc->os.smc_version = SMC_VERSION ;
92 smt_boot_time = smt_get_time();
93 for( i = 0; i < NUMMACS; i++ )
94 smc->sm.last_tok_time[i] = smt_boot_time ;
95 smt = &smc->s ;
96 smt->attach_s = 0 ;
97 smt->build_ring_map = 1 ;
98 smt->sas = SMT_DAS ;
99 smt->numphys = NUMPHYS ;
100 smt->pcm_tb_min = DEFAULT_TB_MIN ;
101 smt->pcm_tb_max = DEFAULT_TB_MAX ;
102 smt->pcm_c_min = DEFAULT_C_MIN ;
103 smt->pcm_t_out = DEFAULT_T_OUT ;
104 smt->pcm_tl_min = DEFAULT_TL_MIN ;
105 smt->pcm_lc_short = DEFAULT_LC_SHORT ;
106 smt->pcm_lc_medium = DEFAULT_LC_MEDIUM ;
107 smt->pcm_lc_long = DEFAULT_LC_LONG ;
108 smt->pcm_lc_extended = DEFAULT_LC_EXTENDED ;
109 smt->pcm_t_next_9 = DEFAULT_T_NEXT_9 ;
110 smt->pcm_ns_max = DEFAULT_NS_MAX ;
111 smt->ecm_i_max = DEFAULT_I_MAX ;
112 smt->ecm_in_max = DEFAULT_IN_MAX ;
113 smt->ecm_td_min = DEFAULT_TD_MIN ;
114 smt->ecm_test_done = DEFAULT_TEST_DONE ;
115 smt->ecm_check_poll = DEFAULT_CHECK_POLL ;
116 smt->rmt_t_non_op = DEFAULT_T_NON_OP ;
117 smt->rmt_t_stuck = DEFAULT_T_STUCK ;
118 smt->rmt_t_direct = DEFAULT_T_DIRECT ;
119 smt->rmt_t_jam = DEFAULT_T_JAM ;
120 smt->rmt_t_announce = DEFAULT_T_ANNOUNCE ;
121 smt->rmt_t_poll = DEFAULT_POLL ;
122 smt->rmt_dup_mac_behavior = FALSE ; /* See Struct smt_config */
123 smt->mac_d_max = DEFAULT_D_MAX ;
124
125 smt->lct_short = DEFAULT_LCT_SHORT ;
126 smt->lct_medium = DEFAULT_LCT_MEDIUM ;
127 smt->lct_long = DEFAULT_LCT_LONG ;
128 smt->lct_extended = DEFAULT_LCT_EXTEND ;
129
130#ifndef SLIM_SMT
131#ifdef ESS
132 if (level == 0) {
133 smc->ess.sync_bw_available = FALSE ;
134 smc->mib.fddiESSPayload = 0 ;
135 smc->mib.fddiESSOverhead = 0 ;
136 smc->mib.fddiESSMaxTNeg = (u_long)(- MS2BCLK(25)) ;
137 smc->mib.fddiESSMinSegmentSize = 1 ;
138 smc->mib.fddiESSCategory = SB_STATIC ;
139 smc->mib.fddiESSSynchTxMode = FALSE ;
140 smc->ess.raf_act_timer_poll = FALSE ;
141 smc->ess.timer_count = 7 ; /* first RAF alc req after 3s */
142 }
143 smc->ess.local_sba_active = FALSE ;
144 smc->ess.sba_reply_pend = NULL ;
145#endif
146#ifdef SBA
147 smt_init_sba(smc,level) ;
148#endif
149#endif /* no SLIM_SMT */
150#ifdef TAG_MODE
151 if (level == 0) {
152 smc->hw.pci_fix_value = 0 ;
153 }
154#endif
155}
156
157/*
158 * manufacturer data
159 */
160static const char man_data[32] =
161/* 01234567890123456789012345678901 */
162 "xxxSK-NET FDDI SMT 7.3 - V2.8.8" ;
163
164static void smt_init_mib(struct s_smc *smc, int level)
165{
166 struct fddi_mib *mib ;
167 struct fddi_mib_p *pm ;
168 int port ;
169 int path ;
170
171 mib = &smc->mib ;
172 if (level == 0) {
173 /*
174 * set EVERYTHING to ZERO
175 * EXCEPT hw and os
176 */
177 memset(((char *)smc)+
178 sizeof(struct s_smt_os)+sizeof(struct s_smt_hw), 0,
179 sizeof(struct s_smc) -
180 sizeof(struct s_smt_os) - sizeof(struct s_smt_hw)) ;
181 }
182 else {
183 mib->fddiSMTRemoteDisconnectFlag = 0 ;
184 mib->fddiSMTPeerWrapFlag = 0 ;
185 }
186
187 mib->fddiSMTOpVersionId = 2 ;
188 mib->fddiSMTHiVersionId = 2 ;
189 mib->fddiSMTLoVersionId = 2 ;
190 memcpy((char *) mib->fddiSMTManufacturerData,man_data,32) ;
191 if (level == 0) {
192 strcpy(mib->fddiSMTUserData,OEM_USER_DATA) ;
193 }
194 mib->fddiSMTMIBVersionId = 1 ;
195 mib->fddiSMTMac_Ct = NUMMACS ;
196 mib->fddiSMTConnectionPolicy = POLICY_MM | POLICY_AA | POLICY_BB ;
197
198 /*
199 * fddiSMTNonMaster_Ct and fddiSMTMaster_Ct are set in smt_fixup_mib
200 * s.sas is not set yet (is set in init driver)
201 */
202 mib->fddiSMTAvailablePaths = MIB_PATH_P | MIB_PATH_S ;
203
204 mib->fddiSMTConfigCapabilities = 0 ; /* no hold,no wrap_ab*/
205 mib->fddiSMTTT_Notify = 10 ;
206 mib->fddiSMTStatRptPolicy = TRUE ;
207 mib->fddiSMTTrace_MaxExpiration = SEC2MIB(7) ;
208 mib->fddiSMTMACIndexes = INDEX_MAC ;
209 mib->fddiSMTStationStatus = MIB_SMT_STASTA_SEPA ; /* separated */
210
211 mib->m[MAC0].fddiMACIndex = INDEX_MAC ;
212 mib->m[MAC0].fddiMACFrameStatusFunctions = FSC_TYPE0 ;
213 mib->m[MAC0].fddiMACRequestedPaths =
214 MIB_P_PATH_LOCAL |
215 MIB_P_PATH_SEC_ALTER |
216 MIB_P_PATH_PRIM_ALTER ;
217 mib->m[MAC0].fddiMACAvailablePaths = MIB_PATH_P ;
218 mib->m[MAC0].fddiMACCurrentPath = MIB_PATH_PRIMARY ;
219 mib->m[MAC0].fddiMACT_MaxCapabilitiy = (u_long)(- MS2BCLK(165)) ;
220 mib->m[MAC0].fddiMACTVXCapabilitiy = (u_long)(- US2BCLK(52)) ;
221 if (level == 0) {
222 mib->m[MAC0].fddiMACTvxValue = (u_long)(- US2BCLK(27)) ;
223 mib->m[MAC0].fddiMACTvxValueMIB = (u_long)(- US2BCLK(27)) ;
224 mib->m[MAC0].fddiMACT_Req = (u_long)(- MS2BCLK(165)) ;
225 mib->m[MAC0].fddiMACT_ReqMIB = (u_long)(- MS2BCLK(165)) ;
226 mib->m[MAC0].fddiMACT_Max = (u_long)(- MS2BCLK(165)) ;
227 mib->m[MAC0].fddiMACT_MaxMIB = (u_long)(- MS2BCLK(165)) ;
228 mib->m[MAC0].fddiMACT_Min = (u_long)(- MS2BCLK(4)) ;
229 }
230 mib->m[MAC0].fddiMACHardwarePresent = TRUE ;
231 mib->m[MAC0].fddiMACMA_UnitdataEnable = TRUE ;
232 mib->m[MAC0].fddiMACFrameErrorThreshold = 1 ;
233 mib->m[MAC0].fddiMACNotCopiedThreshold = 1 ;
234 /*
235 * Path attributes
236 */
237 for (path = 0 ; path < NUMPATHS ; path++) {
238 mib->a[path].fddiPATHIndex = INDEX_PATH + path ;
239 if (level == 0) {
240 mib->a[path].fddiPATHTVXLowerBound =
241 (u_long)(- US2BCLK(27)) ;
242 mib->a[path].fddiPATHT_MaxLowerBound =
243 (u_long)(- MS2BCLK(165)) ;
244 mib->a[path].fddiPATHMaxT_Req =
245 (u_long)(- MS2BCLK(165)) ;
246 }
247 }
248
249
250 /*
251 * Port attributes
252 */
253 pm = mib->p ;
254 for (port = 0 ; port < NUMPHYS ; port++) {
255 /*
256 * set MIB pointer in phy
257 */
258 /* Attention: don't initialize mib pointer here! */
259 /* It must be initialized during phase 2 */
260 smc->y[port].mib = NULL;
261 mib->fddiSMTPORTIndexes[port] = port+INDEX_PORT ;
262
263 pm->fddiPORTIndex = port+INDEX_PORT ;
264 pm->fddiPORTHardwarePresent = TRUE ;
265 if (level == 0) {
266 pm->fddiPORTLer_Alarm = DEFAULT_LEM_ALARM ;
267 pm->fddiPORTLer_Cutoff = DEFAULT_LEM_CUTOFF ;
268 }
269 /*
270 * fddiPORTRequestedPaths are set in pcmplc.c
271 * we don't know the port type yet !
272 */
273 pm->fddiPORTRequestedPaths[1] = 0 ;
274 pm->fddiPORTRequestedPaths[2] = 0 ;
275 pm->fddiPORTRequestedPaths[3] = 0 ;
276 pm->fddiPORTAvailablePaths = MIB_PATH_P ;
277 pm->fddiPORTPMDClass = MIB_PMDCLASS_MULTI ;
278 pm++ ;
279 }
280
281 (void) smt_set_mac_opvalues(smc) ;
282}
283
284int smt_set_mac_opvalues(struct s_smc *smc)
285{
286 int st ;
287 int st2 ;
288
289 st = set_min_max(1,smc->mib.m[MAC0].fddiMACTvxValueMIB,
290 smc->mib.a[PATH0].fddiPATHTVXLowerBound,
291 &smc->mib.m[MAC0].fddiMACTvxValue) ;
292 st |= set_min_max(0,smc->mib.m[MAC0].fddiMACT_MaxMIB,
293 smc->mib.a[PATH0].fddiPATHT_MaxLowerBound,
294 &smc->mib.m[MAC0].fddiMACT_Max) ;
295 st |= (st2 = set_min_max(0,smc->mib.m[MAC0].fddiMACT_ReqMIB,
296 smc->mib.a[PATH0].fddiPATHMaxT_Req,
297 &smc->mib.m[MAC0].fddiMACT_Req)) ;
298 if (st2) {
299 /* Treq attribute changed remotely. So send an AIX_EVENT to the
300 * user
301 */
302 AIX_EVENT(smc, (u_long) FDDI_RING_STATUS, (u_long)
303 FDDI_SMT_EVENT, (u_long) FDDI_REMOTE_T_REQ,
304 smt_get_event_word(smc));
305 }
306 return st;
307}
308
309void smt_fixup_mib(struct s_smc *smc)
310{
311#ifdef CONCENTRATOR
312 switch (smc->s.sas) {
313 case SMT_SAS :
314 smc->mib.fddiSMTNonMaster_Ct = 1 ;
315 break ;
316 case SMT_DAS :
317 smc->mib.fddiSMTNonMaster_Ct = 2 ;
318 break ;
319 case SMT_NAC :
320 smc->mib.fddiSMTNonMaster_Ct = 0 ;
321 break ;
322 }
323 smc->mib.fddiSMTMaster_Ct = NUMPHYS - smc->mib.fddiSMTNonMaster_Ct ;
324#else
325 switch (smc->s.sas) {
326 case SMT_SAS :
327 smc->mib.fddiSMTNonMaster_Ct = 1 ;
328 break ;
329 case SMT_DAS :
330 smc->mib.fddiSMTNonMaster_Ct = 2 ;
331 break ;
332 }
333 smc->mib.fddiSMTMaster_Ct = 0 ;
334#endif
335}
336
337/*
338 * determine new setting for operational value
339 * if limit is lower than mib
340 * use limit
341 * else
342 * use mib
343 * NOTE : numbers are negative, negate comparison !
344 */
345static int set_min_max(int maxflag, u_long mib, u_long limit, u_long *oper)
346{
347 u_long old ;
348 old = *oper ;
349 if ((limit > mib) ^ maxflag)
350 *oper = limit ;
351 else
352 *oper = mib ;
353 return old != *oper;
354}
355
diff --git a/drivers/net/skfp/smtinit.c b/drivers/net/skfp/smtinit.c
deleted file mode 100644
index e3a0c0bc2233..000000000000
--- a/drivers/net/skfp/smtinit.c
+++ /dev/null
@@ -1,125 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 Init SMT
19 call all module level initialization routines
20*/
21
22#include "h/types.h"
23#include "h/fddi.h"
24#include "h/smc.h"
25
26#ifndef lint
27static const char ID_sccs[] = "@(#)smtinit.c 1.15 97/05/06 (C) SK " ;
28#endif
29
30void init_fddi_driver(struct s_smc *smc, u_char *mac_addr);
31
32/* define global debug variable */
33#if defined(DEBUG) && !defined(DEBUG_BRD)
34struct smt_debug debug;
35#endif
36
37#ifndef MULT_OEM
38#define OEMID(smc,i) oem_id[i]
39 extern u_char oem_id[] ;
40#else /* MULT_OEM */
41#define OEMID(smc,i) smc->hw.oem_id->oi_mark[i]
42 extern struct s_oem_ids oem_ids[] ;
43#endif /* MULT_OEM */
44
45/*
46 * Set OEM specific values
47 *
48 * Can not be called in smt_reset_defaults, because it is not sure that
49 * the OEM ID is already defined.
50 */
51static void set_oem_spec_val(struct s_smc *smc)
52{
53 struct fddi_mib *mib ;
54
55 mib = &smc->mib ;
56
57 /*
58 * set IBM specific values
59 */
60 if (OEMID(smc,0) == 'I') {
61 mib->fddiSMTConnectionPolicy = POLICY_MM ;
62 }
63}
64
65/*
66 * Init SMT
67 */
68int init_smt(struct s_smc *smc, u_char *mac_addr)
69/* u_char *mac_addr; canonical address or NULL */
70{
71 int p ;
72
73#if defined(DEBUG) && !defined(DEBUG_BRD)
74 debug.d_smt = 0 ;
75 debug.d_smtf = 0 ;
76 debug.d_rmt = 0 ;
77 debug.d_ecm = 0 ;
78 debug.d_pcm = 0 ;
79 debug.d_cfm = 0 ;
80
81 debug.d_plc = 0 ;
82#ifdef ESS
83 debug.d_ess = 0 ;
84#endif
85#ifdef SBA
86 debug.d_sba = 0 ;
87#endif
88#endif /* DEBUG && !DEBUG_BRD */
89
90 /* First initialize the ports mib->pointers */
91 for ( p = 0; p < NUMPHYS; p ++ ) {
92 smc->y[p].mib = & smc->mib.p[p] ;
93 }
94
95 set_oem_spec_val(smc) ;
96 (void) smt_set_mac_opvalues(smc) ;
97 init_fddi_driver(smc,mac_addr) ; /* HW driver */
98 smt_fixup_mib(smc) ; /* update values that depend on s.sas */
99
100 ev_init(smc) ; /* event queue */
101#ifndef SLIM_SMT
102 smt_init_evc(smc) ; /* evcs in MIB */
103#endif /* no SLIM_SMT */
104 smt_timer_init(smc) ; /* timer package */
105 smt_agent_init(smc) ; /* SMT frame manager */
106
107 pcm_init(smc) ; /* PCM state machine */
108 ecm_init(smc) ; /* ECM state machine */
109 cfm_init(smc) ; /* CFM state machine */
110 rmt_init(smc) ; /* RMT state machine */
111
112 for (p = 0 ; p < NUMPHYS ; p++) {
113 pcm(smc,p,0) ; /* PCM A state machine */
114 }
115 ecm(smc,0) ; /* ECM state machine */
116 cfm(smc,0) ; /* CFM state machine */
117 rmt(smc,0) ; /* RMT state machine */
118
119 smt_agent_task(smc) ; /* NIF FSM etc */
120
121 PNMI_INIT(smc) ; /* PNMI initialization */
122
123 return 0;
124}
125
diff --git a/drivers/net/skfp/smttimer.c b/drivers/net/skfp/smttimer.c
deleted file mode 100644
index 531795e98c30..000000000000
--- a/drivers/net/skfp/smttimer.c
+++ /dev/null
@@ -1,156 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 SMT timer
19*/
20
21#include "h/types.h"
22#include "h/fddi.h"
23#include "h/smc.h"
24
25#ifndef lint
26static const char ID_sccs[] = "@(#)smttimer.c 2.4 97/08/04 (C) SK " ;
27#endif
28
29static void timer_done(struct s_smc *smc, int restart);
30
31void smt_timer_init(struct s_smc *smc)
32{
33 smc->t.st_queue = NULL;
34 smc->t.st_fast.tm_active = FALSE ;
35 smc->t.st_fast.tm_next = NULL;
36 hwt_init(smc) ;
37}
38
39void smt_timer_stop(struct s_smc *smc, struct smt_timer *timer)
40{
41 struct smt_timer **prev ;
42 struct smt_timer *tm ;
43
44 /*
45 * remove timer from queue
46 */
47 timer->tm_active = FALSE ;
48 if (smc->t.st_queue == timer && !timer->tm_next) {
49 hwt_stop(smc) ;
50 }
51 for (prev = &smc->t.st_queue ; (tm = *prev) ; prev = &tm->tm_next ) {
52 if (tm == timer) {
53 *prev = tm->tm_next ;
54 if (tm->tm_next) {
55 tm->tm_next->tm_delta += tm->tm_delta ;
56 }
57 return ;
58 }
59 }
60}
61
62void smt_timer_start(struct s_smc *smc, struct smt_timer *timer, u_long time,
63 u_long token)
64{
65 struct smt_timer **prev ;
66 struct smt_timer *tm ;
67 u_long delta = 0 ;
68
69 time /= 16 ; /* input is uS, clock ticks are 16uS */
70 if (!time)
71 time = 1 ;
72 smt_timer_stop(smc,timer) ;
73 timer->tm_smc = smc ;
74 timer->tm_token = token ;
75 timer->tm_active = TRUE ;
76 if (!smc->t.st_queue) {
77 smc->t.st_queue = timer ;
78 timer->tm_next = NULL;
79 timer->tm_delta = time ;
80 hwt_start(smc,time) ;
81 return ;
82 }
83 /*
84 * timer correction
85 */
86 timer_done(smc,0) ;
87
88 /*
89 * find position in queue
90 */
91 delta = 0 ;
92 for (prev = &smc->t.st_queue ; (tm = *prev) ; prev = &tm->tm_next ) {
93 if (delta + tm->tm_delta > time) {
94 break ;
95 }
96 delta += tm->tm_delta ;
97 }
98 /* insert in queue */
99 *prev = timer ;
100 timer->tm_next = tm ;
101 timer->tm_delta = time - delta ;
102 if (tm)
103 tm->tm_delta -= timer->tm_delta ;
104 /*
105 * start new with first
106 */
107 hwt_start(smc,smc->t.st_queue->tm_delta) ;
108}
109
110void smt_force_irq(struct s_smc *smc)
111{
112 smt_timer_start(smc,&smc->t.st_fast,32L, EV_TOKEN(EVENT_SMT,SM_FAST));
113}
114
115void smt_timer_done(struct s_smc *smc)
116{
117 timer_done(smc,1) ;
118}
119
120static void timer_done(struct s_smc *smc, int restart)
121{
122 u_long delta ;
123 struct smt_timer *tm ;
124 struct smt_timer *next ;
125 struct smt_timer **last ;
126 int done = 0 ;
127
128 delta = hwt_read(smc) ;
129 last = &smc->t.st_queue ;
130 tm = smc->t.st_queue ;
131 while (tm && !done) {
132 if (delta >= tm->tm_delta) {
133 tm->tm_active = FALSE ;
134 delta -= tm->tm_delta ;
135 last = &tm->tm_next ;
136 tm = tm->tm_next ;
137 }
138 else {
139 tm->tm_delta -= delta ;
140 delta = 0 ;
141 done = 1 ;
142 }
143 }
144 *last = NULL;
145 next = smc->t.st_queue ;
146 smc->t.st_queue = tm ;
147
148 for ( tm = next ; tm ; tm = next) {
149 next = tm->tm_next ;
150 timer_event(smc,tm->tm_token) ;
151 }
152
153 if (restart && smc->t.st_queue)
154 hwt_start(smc,smc->t.st_queue->tm_delta) ;
155}
156
diff --git a/drivers/net/skfp/srf.c b/drivers/net/skfp/srf.c
deleted file mode 100644
index f6f7baf9f27a..000000000000
--- a/drivers/net/skfp/srf.c
+++ /dev/null
@@ -1,429 +0,0 @@
1/******************************************************************************
2 *
3 * (C)Copyright 1998,1999 SysKonnect,
4 * a business unit of Schneider & Koch & Co. Datensysteme GmbH.
5 *
6 * See the file "skfddi.c" for further information.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * The information in this file is provided "AS IS" without warranty.
14 *
15 ******************************************************************************/
16
17/*
18 SMT 7.2 Status Response Frame Implementation
19 SRF state machine and frame generation
20*/
21
22#include "h/types.h"
23#include "h/fddi.h"
24#include "h/smc.h"
25#include "h/smt_p.h"
26
27#define KERNEL
28#include "h/smtstate.h"
29
30#ifndef SLIM_SMT
31#ifndef BOOT
32
33#ifndef lint
34static const char ID_sccs[] = "@(#)srf.c 1.18 97/08/04 (C) SK " ;
35#endif
36
37
38/*
39 * function declarations
40 */
41static void clear_all_rep(struct s_smc *smc);
42static void clear_reported(struct s_smc *smc);
43static void smt_send_srf(struct s_smc *smc);
44static struct s_srf_evc *smt_get_evc(struct s_smc *smc, int code, int index);
45
46#define MAX_EVCS ARRAY_SIZE(smc->evcs)
47
48struct evc_init {
49 u_char code ;
50 u_char index ;
51 u_char n ;
52 u_short para ;
53} ;
54
55static const struct evc_init evc_inits[] = {
56 { SMT_COND_SMT_PEER_WRAP, 0,1,SMT_P1048 } ,
57
58 { SMT_COND_MAC_DUP_ADDR, INDEX_MAC, NUMMACS,SMT_P208C } ,
59 { SMT_COND_MAC_FRAME_ERROR, INDEX_MAC, NUMMACS,SMT_P208D } ,
60 { SMT_COND_MAC_NOT_COPIED, INDEX_MAC, NUMMACS,SMT_P208E } ,
61 { SMT_EVENT_MAC_NEIGHBOR_CHANGE, INDEX_MAC, NUMMACS,SMT_P208F } ,
62 { SMT_EVENT_MAC_PATH_CHANGE, INDEX_MAC, NUMMACS,SMT_P2090 } ,
63
64 { SMT_COND_PORT_LER, INDEX_PORT,NUMPHYS,SMT_P4050 } ,
65 { SMT_COND_PORT_EB_ERROR, INDEX_PORT,NUMPHYS,SMT_P4052 } ,
66 { SMT_EVENT_PORT_CONNECTION, INDEX_PORT,NUMPHYS,SMT_P4051 } ,
67 { SMT_EVENT_PORT_PATH_CHANGE, INDEX_PORT,NUMPHYS,SMT_P4053 } ,
68} ;
69
70#define MAX_INIT_EVC ARRAY_SIZE(evc_inits)
71
72void smt_init_evc(struct s_smc *smc)
73{
74 struct s_srf_evc *evc ;
75 const struct evc_init *init ;
76 int i ;
77 int index ;
78 int offset ;
79
80 static u_char fail_safe = FALSE ;
81
82 memset((char *)smc->evcs,0,sizeof(smc->evcs)) ;
83
84 evc = smc->evcs ;
85 init = evc_inits ;
86
87 for (i = 0 ; (unsigned) i < MAX_INIT_EVC ; i++) {
88 for (index = 0 ; index < init->n ; index++) {
89 evc->evc_code = init->code ;
90 evc->evc_para = init->para ;
91 evc->evc_index = init->index + index ;
92#ifndef DEBUG
93 evc->evc_multiple = &fail_safe ;
94 evc->evc_cond_state = &fail_safe ;
95#endif
96 evc++ ;
97 }
98 init++ ;
99 }
100
101 if ((unsigned) (evc - smc->evcs) > MAX_EVCS) {
102 SMT_PANIC(smc,SMT_E0127, SMT_E0127_MSG) ;
103 }
104
105 /*
106 * conditions
107 */
108 smc->evcs[0].evc_cond_state = &smc->mib.fddiSMTPeerWrapFlag ;
109 smc->evcs[1].evc_cond_state =
110 &smc->mib.m[MAC0].fddiMACDuplicateAddressCond ;
111 smc->evcs[2].evc_cond_state =
112 &smc->mib.m[MAC0].fddiMACFrameErrorFlag ;
113 smc->evcs[3].evc_cond_state =
114 &smc->mib.m[MAC0].fddiMACNotCopiedFlag ;
115
116 /*
117 * events
118 */
119 smc->evcs[4].evc_multiple = &smc->mib.m[MAC0].fddiMACMultiple_N ;
120 smc->evcs[5].evc_multiple = &smc->mib.m[MAC0].fddiMACMultiple_P ;
121
122 offset = 6 ;
123 for (i = 0 ; i < NUMPHYS ; i++) {
124 /*
125 * conditions
126 */
127 smc->evcs[offset + 0*NUMPHYS].evc_cond_state =
128 &smc->mib.p[i].fddiPORTLerFlag ;
129 smc->evcs[offset + 1*NUMPHYS].evc_cond_state =
130 &smc->mib.p[i].fddiPORTEB_Condition ;
131
132 /*
133 * events
134 */
135 smc->evcs[offset + 2*NUMPHYS].evc_multiple =
136 &smc->mib.p[i].fddiPORTMultiple_U ;
137 smc->evcs[offset + 3*NUMPHYS].evc_multiple =
138 &smc->mib.p[i].fddiPORTMultiple_P ;
139 offset++ ;
140 }
141#ifdef DEBUG
142 for (i = 0, evc = smc->evcs ; (unsigned) i < MAX_EVCS ; i++, evc++) {
143 if (SMT_IS_CONDITION(evc->evc_code)) {
144 if (!evc->evc_cond_state) {
145 SMT_PANIC(smc,SMT_E0128, SMT_E0128_MSG) ;
146 }
147 evc->evc_multiple = &fail_safe ;
148 }
149 else {
150 if (!evc->evc_multiple) {
151 SMT_PANIC(smc,SMT_E0129, SMT_E0129_MSG) ;
152 }
153 evc->evc_cond_state = &fail_safe ;
154 }
155 }
156#endif
157 smc->srf.TSR = smt_get_time() ;
158 smc->srf.sr_state = SR0_WAIT ;
159}
160
161static struct s_srf_evc *smt_get_evc(struct s_smc *smc, int code, int index)
162{
163 int i ;
164 struct s_srf_evc *evc ;
165
166 for (i = 0, evc = smc->evcs ; (unsigned) i < MAX_EVCS ; i++, evc++) {
167 if (evc->evc_code == code && evc->evc_index == index)
168 return evc;
169 }
170 return NULL;
171}
172
173#define THRESHOLD_2 (2*TICKS_PER_SECOND)
174#define THRESHOLD_32 (32*TICKS_PER_SECOND)
175
176#ifdef DEBUG
177static const char * const srf_names[] = {
178 "None","MACPathChangeEvent", "MACNeighborChangeEvent",
179 "PORTPathChangeEvent", "PORTUndesiredConnectionAttemptEvent",
180 "SMTPeerWrapCondition", "SMTHoldCondition",
181 "MACFrameErrorCondition", "MACDuplicateAddressCondition",
182 "MACNotCopiedCondition", "PORTEBErrorCondition",
183 "PORTLerCondition"
184} ;
185#endif
186
187void smt_srf_event(struct s_smc *smc, int code, int index, int cond)
188{
189 struct s_srf_evc *evc ;
190 int cond_asserted = 0 ;
191 int cond_deasserted = 0 ;
192 int event_occurred = 0 ;
193 int tsr ;
194 int T_Limit = 2*TICKS_PER_SECOND ;
195
196 if (code == SMT_COND_MAC_DUP_ADDR && cond) {
197 RS_SET(smc,RS_DUPADDR) ;
198 }
199
200 if (code) {
201 DB_SMT("SRF: %s index %d\n",srf_names[code],index) ;
202
203 if (!(evc = smt_get_evc(smc,code,index))) {
204 DB_SMT("SRF : smt_get_evc() failed\n",0,0) ;
205 return ;
206 }
207 /*
208 * ignore condition if no change
209 */
210 if (SMT_IS_CONDITION(code)) {
211 if (*evc->evc_cond_state == cond)
212 return ;
213 }
214
215 /*
216 * set transition time stamp
217 */
218 smt_set_timestamp(smc,smc->mib.fddiSMTTransitionTimeStamp) ;
219 if (SMT_IS_CONDITION(code)) {
220 DB_SMT("SRF: condition is %s\n",cond ? "ON":"OFF",0) ;
221 if (cond) {
222 *evc->evc_cond_state = TRUE ;
223 evc->evc_rep_required = TRUE ;
224 smc->srf.any_report = TRUE ;
225 cond_asserted = TRUE ;
226 }
227 else {
228 *evc->evc_cond_state = FALSE ;
229 cond_deasserted = TRUE ;
230 }
231 }
232 else {
233 if (evc->evc_rep_required) {
234 *evc->evc_multiple = TRUE ;
235 }
236 else {
237 evc->evc_rep_required = TRUE ;
238 *evc->evc_multiple = FALSE ;
239 }
240 smc->srf.any_report = TRUE ;
241 event_occurred = TRUE ;
242 }
243#ifdef FDDI_MIB
244 snmp_srf_event(smc,evc) ;
245#endif /* FDDI_MIB */
246 }
247 tsr = smt_get_time() - smc->srf.TSR ;
248
249 switch (smc->srf.sr_state) {
250 case SR0_WAIT :
251 /* SR01a */
252 if (cond_asserted && tsr < T_Limit) {
253 smc->srf.SRThreshold = THRESHOLD_2 ;
254 smc->srf.sr_state = SR1_HOLDOFF ;
255 break ;
256 }
257 /* SR01b */
258 if (cond_deasserted && tsr < T_Limit) {
259 smc->srf.sr_state = SR1_HOLDOFF ;
260 break ;
261 }
262 /* SR01c */
263 if (event_occurred && tsr < T_Limit) {
264 smc->srf.sr_state = SR1_HOLDOFF ;
265 break ;
266 }
267 /* SR00b */
268 if (cond_asserted && tsr >= T_Limit) {
269 smc->srf.SRThreshold = THRESHOLD_2 ;
270 smc->srf.TSR = smt_get_time() ;
271 smt_send_srf(smc) ;
272 break ;
273 }
274 /* SR00c */
275 if (cond_deasserted && tsr >= T_Limit) {
276 smc->srf.TSR = smt_get_time() ;
277 smt_send_srf(smc) ;
278 break ;
279 }
280 /* SR00d */
281 if (event_occurred && tsr >= T_Limit) {
282 smc->srf.TSR = smt_get_time() ;
283 smt_send_srf(smc) ;
284 break ;
285 }
286 /* SR00e */
287 if (smc->srf.any_report && (u_long) tsr >=
288 smc->srf.SRThreshold) {
289 smc->srf.SRThreshold *= 2 ;
290 if (smc->srf.SRThreshold > THRESHOLD_32)
291 smc->srf.SRThreshold = THRESHOLD_32 ;
292 smc->srf.TSR = smt_get_time() ;
293 smt_send_srf(smc) ;
294 break ;
295 }
296 /* SR02 */
297 if (!smc->mib.fddiSMTStatRptPolicy) {
298 smc->srf.sr_state = SR2_DISABLED ;
299 break ;
300 }
301 break ;
302 case SR1_HOLDOFF :
303 /* SR10b */
304 if (tsr >= T_Limit) {
305 smc->srf.sr_state = SR0_WAIT ;
306 smc->srf.TSR = smt_get_time() ;
307 smt_send_srf(smc) ;
308 break ;
309 }
310 /* SR11a */
311 if (cond_asserted) {
312 smc->srf.SRThreshold = THRESHOLD_2 ;
313 }
314 /* SR11b */
315 /* SR11c */
316 /* handled above */
317 /* SR12 */
318 if (!smc->mib.fddiSMTStatRptPolicy) {
319 smc->srf.sr_state = SR2_DISABLED ;
320 break ;
321 }
322 break ;
323 case SR2_DISABLED :
324 if (smc->mib.fddiSMTStatRptPolicy) {
325 smc->srf.sr_state = SR0_WAIT ;
326 smc->srf.TSR = smt_get_time() ;
327 smc->srf.SRThreshold = THRESHOLD_2 ;
328 clear_all_rep(smc) ;
329 break ;
330 }
331 break ;
332 }
333}
334
335static void clear_all_rep(struct s_smc *smc)
336{
337 struct s_srf_evc *evc ;
338 int i ;
339
340 for (i = 0, evc = smc->evcs ; (unsigned) i < MAX_EVCS ; i++, evc++) {
341 evc->evc_rep_required = FALSE ;
342 if (SMT_IS_CONDITION(evc->evc_code))
343 *evc->evc_cond_state = FALSE ;
344 }
345 smc->srf.any_report = FALSE ;
346}
347
348static void clear_reported(struct s_smc *smc)
349{
350 struct s_srf_evc *evc ;
351 int i ;
352
353 smc->srf.any_report = FALSE ;
354 for (i = 0, evc = smc->evcs ; (unsigned) i < MAX_EVCS ; i++, evc++) {
355 if (SMT_IS_CONDITION(evc->evc_code)) {
356 if (*evc->evc_cond_state == FALSE)
357 evc->evc_rep_required = FALSE ;
358 else
359 smc->srf.any_report = TRUE ;
360 }
361 else {
362 evc->evc_rep_required = FALSE ;
363 *evc->evc_multiple = FALSE ;
364 }
365 }
366}
367
368/*
369 * build and send SMT SRF frame
370 */
371static void smt_send_srf(struct s_smc *smc)
372{
373
374 struct smt_header *smt ;
375 struct s_srf_evc *evc ;
376 SK_LOC_DECL(struct s_pcon,pcon) ;
377 SMbuf *mb ;
378 int i ;
379
380 static const struct fddi_addr SMT_SRF_DA = {
381 { 0x80, 0x01, 0x43, 0x00, 0x80, 0x08 }
382 } ;
383
384 /*
385 * build SMT header
386 */
387 if (!smc->r.sm_ma_avail)
388 return ;
389 if (!(mb = smt_build_frame(smc,SMT_SRF,SMT_ANNOUNCE,0)))
390 return ;
391
392 RS_SET(smc,RS_SOFTERROR) ;
393
394 smt = smtod(mb, struct smt_header *) ;
395 smt->smt_dest = SMT_SRF_DA ; /* DA == SRF multicast */
396
397 /*
398 * setup parameter status
399 */
400 pcon.pc_len = SMT_MAX_INFO_LEN ; /* max para length */
401 pcon.pc_err = 0 ; /* no error */
402 pcon.pc_badset = 0 ; /* no bad set count */
403 pcon.pc_p = (void *) (smt + 1) ; /* paras start here */
404
405 smt_add_para(smc,&pcon,(u_short) SMT_P1033,0,0) ;
406 smt_add_para(smc,&pcon,(u_short) SMT_P1034,0,0) ;
407
408 for (i = 0, evc = smc->evcs ; (unsigned) i < MAX_EVCS ; i++, evc++) {
409 if (evc->evc_rep_required) {
410 smt_add_para(smc,&pcon,evc->evc_para,
411 (int)evc->evc_index,0) ;
412 }
413 }
414 smt->smt_len = SMT_MAX_INFO_LEN - pcon.pc_len ;
415 mb->sm_len = smt->smt_len + sizeof(struct smt_header) ;
416
417 DB_SMT("SRF: sending SRF at %x, len %d\n",smt,mb->sm_len) ;
418 DB_SMT("SRF: state SR%d Threshold %d\n",
419 smc->srf.sr_state,smc->srf.SRThreshold/TICKS_PER_SECOND) ;
420#ifdef DEBUG
421 dump_smt(smc,smt,"SRF Send") ;
422#endif
423 smt_send_frame(smc,mb,FC_SMT_INFO,0) ;
424 clear_reported(smc) ;
425}
426
427#endif /* no BOOT */
428#endif /* no SLIM_SMT */
429
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 02:06:33 -0500