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authorJeff Garzik <jeff@garzik.org>2007-07-24 01:30:36 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:50:18 -0400
commitaf096046f63a065b692018cd4b8f5e7525c3e56a (patch)
tree79a45fa1ed1e88e1ea1c9cf826f73ae3ca5d24dc /drivers/net/skfp/hwt.c
parent7856a541ad83e84d260abb652c39299972ba310c (diff)
[netdrvr] skfp: remove a bunch of dead code
The driver has not compiled in anything except PCI support for many years (see drivers/net/skfp/Makefile). This driver is also unmaintained for many years, so arguments for keeping the cross-OS, cross-bus (ISA, EISA, MCA) code do not exist. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/skfp/hwt.c')
-rw-r--r--drivers/net/skfp/hwt.c42
1 files changed, 3 insertions, 39 deletions
diff --git a/drivers/net/skfp/hwt.c b/drivers/net/skfp/hwt.c
index e01f8a0f35c6..053151468f93 100644
--- a/drivers/net/skfp/hwt.c
+++ b/drivers/net/skfp/hwt.c
@@ -77,25 +77,10 @@ void hwt_start(struct s_smc *smc, u_long time)
77 */ 77 */
78 if (!cnt) 78 if (!cnt)
79 cnt++ ; 79 cnt++ ;
80#ifndef PCI 80
81 /*
82 * 6.25MHz -> CLK0 : T0 (cnt0 = 16us) -> OUT0
83 * OUT0 -> CLK1 : T1 (cnt1) OUT1 -> ISRA(IS_TIMINT)
84 */
85 OUT_82c54_TIMER(3,1<<6 | 3<<4 | 0<<1) ; /* counter 1, mode 0 */
86 OUT_82c54_TIMER(1,cnt & 0xff) ; /* LSB */
87 OUT_82c54_TIMER(1,(cnt>>8) & 0xff) ; /* MSB */
88 /*
89 * start timer by switching counter 0 to mode 3
90 * T0 resolution 16 us (CLK0=0.16us)
91 */
92 OUT_82c54_TIMER(3,0<<6 | 3<<4 | 3<<1) ; /* counter 0, mode 3 */
93 OUT_82c54_TIMER(0,100) ; /* LSB */
94 OUT_82c54_TIMER(0,0) ; /* MSB */
95#else /* PCI */
96 outpd(ADDR(B2_TI_INI), (u_long) cnt * 200) ; /* Load timer value. */ 81 outpd(ADDR(B2_TI_INI), (u_long) cnt * 200) ; /* Load timer value. */
97 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */ 82 outpw(ADDR(B2_TI_CRTL), TIM_START) ; /* Start timer. */
98#endif /* PCI */ 83
99 smc->hw.timer_activ = TRUE ; 84 smc->hw.timer_activ = TRUE ;
100} 85}
101 86
@@ -115,15 +100,8 @@ void hwt_start(struct s_smc *smc, u_long time)
115 ************************/ 100 ************************/
116void hwt_stop(struct s_smc *smc) 101void hwt_stop(struct s_smc *smc)
117{ 102{
118#ifndef PCI
119 /* stop counter 0 by switching to mode 0 */
120 OUT_82c54_TIMER(3,0<<6 | 3<<4 | 0<<1) ; /* counter 0, mode 0 */
121 OUT_82c54_TIMER(0,0) ; /* LSB */
122 OUT_82c54_TIMER(0,0) ; /* MSB */
123#else /* PCI */
124 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ; 103 outpw(ADDR(B2_TI_CRTL), TIM_STOP) ;
125 outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ; 104 outpw(ADDR(B2_TI_CRTL), TIM_CL_IRQ) ;
126#endif /* PCI */
127 105
128 smc->hw.timer_activ = FALSE ; 106 smc->hw.timer_activ = FALSE ;
129} 107}
@@ -168,11 +146,6 @@ void hwt_init(struct s_smc *smc)
168void hwt_restart(struct s_smc *smc) 146void hwt_restart(struct s_smc *smc)
169{ 147{
170 hwt_stop(smc) ; 148 hwt_stop(smc) ;
171#ifndef PCI
172 OUT_82c54_TIMER(3,1<<6 | 3<<4 | 0<<1) ; /* counter 1, mode 0 */
173 OUT_82c54_TIMER(1,1 ) ; /* LSB */
174 OUT_82c54_TIMER(1,0 ) ; /* MSB */
175#endif
176} 149}
177 150
178/************************ 151/************************
@@ -191,21 +164,12 @@ void hwt_restart(struct s_smc *smc)
191u_long hwt_read(struct s_smc *smc) 164u_long hwt_read(struct s_smc *smc)
192{ 165{
193 u_short tr ; 166 u_short tr ;
194#ifndef PCI
195 u_short is ;
196#else
197 u_long is ; 167 u_long is ;
198#endif
199 168
200 if (smc->hw.timer_activ) { 169 if (smc->hw.timer_activ) {
201 hwt_stop(smc) ; 170 hwt_stop(smc) ;
202#ifndef PCI
203 OUT_82c54_TIMER(3,1<<6) ; /* latch command */
204 tr = IN_82c54_TIMER(1) & 0xff ;
205 tr += (IN_82c54_TIMER(1) & 0xff)<<8 ;
206#else /* PCI */
207 tr = (u_short)((inpd(ADDR(B2_TI_VAL))/200) & 0xffff) ; 171 tr = (u_short)((inpd(ADDR(B2_TI_VAL))/200) & 0xffff) ;
208#endif /* PCI */ 172
209 is = GET_ISR() ; 173 is = GET_ISR() ;
210 /* Check if timer expired (or wraparound). */ 174 /* Check if timer expired (or wraparound). */
211 if ((tr > smc->hw.t_start) || (is & IS_TIMINT)) { 175 if ((tr > smc->hw.t_start) || (is & IS_TIMINT)) {