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authorJeff Garzik <jeff@garzik.org>2007-07-24 01:30:36 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:50:18 -0400
commitaf096046f63a065b692018cd4b8f5e7525c3e56a (patch)
tree79a45fa1ed1e88e1ea1c9cf826f73ae3ca5d24dc /drivers/net/skfp/h
parent7856a541ad83e84d260abb652c39299972ba310c (diff)
[netdrvr] skfp: remove a bunch of dead code
The driver has not compiled in anything except PCI support for many years (see drivers/net/skfp/Makefile). This driver is also unmaintained for many years, so arguments for keeping the cross-OS, cross-bus (ISA, EISA, MCA) code do not exist. Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/skfp/h')
-rw-r--r--drivers/net/skfp/h/mbuf.h4
-rw-r--r--drivers/net/skfp/h/skfbi.h783
-rw-r--r--drivers/net/skfp/h/skfbiinc.h26
-rw-r--r--drivers/net/skfp/h/targethw.h33
4 files changed, 2 insertions, 844 deletions
diff --git a/drivers/net/skfp/h/mbuf.h b/drivers/net/skfp/h/mbuf.h
index b339d1f2e0e5..f2aadcda9e7f 100644
--- a/drivers/net/skfp/h/mbuf.h
+++ b/drivers/net/skfp/h/mbuf.h
@@ -15,11 +15,7 @@
15#ifndef _MBUF_ 15#ifndef _MBUF_
16#define _MBUF_ 16#define _MBUF_
17 17
18#ifndef PCI
19#define M_SIZE 4550
20#else
21#define M_SIZE 4504 18#define M_SIZE 4504
22#endif
23 19
24#ifndef MAX_MBUF 20#ifndef MAX_MBUF
25#define MAX_MBUF 4 21#define MAX_MBUF 4
diff --git a/drivers/net/skfp/h/skfbi.h b/drivers/net/skfp/h/skfbi.h
index ba347d6910f1..d25c9f849842 100644
--- a/drivers/net/skfp/h/skfbi.h
+++ b/drivers/net/skfp/h/skfbi.h
@@ -21,791 +21,10 @@
21#endif 21#endif
22 22
23/* 23/*
24 * physical address offset + IO-Port base address 24 * FDDI-Fx (x := {I(SA), P(CI)})
25 */
26#ifndef PCI
27#define ADDR(a) ((a)+smc->hw.iop)
28#define ADDRS(smc,a) ((a)+(smc)->hw.iop)
29#endif
30
31/*
32 * FDDI-Fx (x := {I(SA), E(ISA), M(CA), P(CI)})
33 * address calculation & function defines 25 * address calculation & function defines
34 */ 26 */
35 27
36#ifdef EISA
37
38/*
39 * Configuration PROM: !! all 8-Bit IO's !!
40 * |<- MAC-Address ->|
41 * /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
42 * val: |PROD_ID0..3| | free | |00|00|5A|40| |nn|mm|00|00|
43 * /-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-//-+--+--+--+--+-/
44 * IO- ^ ^ ^ ^ ^
45 * port 0C80 0C83 0C88 0C90 0C98
46 * | \
47 * | \
48 * | \______________________________________________
49 * EISA Expansion Board Product ID: \
50 * BIT: |7 6 5 4 3 2 1 0| \
51 * | PROD_ID0 | PROD_ID1 | PROD_ID2 | PROD_ID3 |
52 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
53 * |0| MAN_C0 | MAN_C1 | MAN_C2 | PROD1 | PROD0 | REV1 | REV0 |
54 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
55 * ^=reserved | product numb. | revision numb |
56 * MAN_Cx = compressed manufacterer code (x:=0..2)
57 * ASCII : 'A'..'Z' : 0x41..0x5A -> compr.(c-0x40) : 0x01..0x1A (5Bits!)
58 */
59
60#ifndef MULT_OEM
61#ifndef OEM_CONCEPT
62#define MAN_C0 ('S'-0x40)
63#define MAN_C1 ('K'-0x40)
64#define MAN_C2 ('D'-0x40)
65#define PROD_ID0 (u_char)((MAN_C0<<2) | (MAN_C1>>3))
66#define PROD_ID1 (u_char)(((MAN_C1<<5) & 0xff) | MAN_C2)
67#define PROD_ID2 (u_char)(1) /* prod. nr. */
68#define PROD_ID3 (u_char)(0) /* rev. nr. */
69
70#ifndef OEM_USER_DATA
71#define OEM_USER_DATA "SK-NET FDDI V2.0 Userdata"
72#endif
73#else /* OEM_CONCEPT */
74
75/* MAN_C(0|1|2) no longer present (ra). */
76#define PROD_ID0 (u_char)OEM_PROD_ID0
77#define PROD_ID1 (u_char)OEM_PROD_ID1
78#define PROD_ID2 (u_char)OEM_PROD_ID2
79#define PROD_ID3 (u_char)OEM_PROD_ID3
80#endif /* OEM_CONCEPT */
81
82#define SKLOGO PROD_ID0, PROD_ID1, PROD_ID2, PROD_ID3
83#endif /* MULT_OEM */
84
85#define SADDRL (0) /* start address SKLOGO */
86#define SA_MAC (0x10) /* start addr. MAC_AD within the PROM */
87#define PRA_OFF (4)
88#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
89
90#define SKFDDI_PSZ 32 /* address PROM size */
91
92/*
93 * address transmission from logical to physical offset address on board
94 */
95#define FMA(a) (0x0400|((a)<<1)) /* FORMAC+ (r/w) */
96#define P1A(a) (0x0800|((a)<<1)) /* PLC1 (r/w) */
97#define P2A(a) (0x0840|((a)<<1)) /* PLC2 (r/w) */
98#define TIA(a) (0x0880|((a)<<1)) /* Timer (r/w) */
99#define PRA(a) (0x0c80| (a)) /* configuration PROM */
100#define C0A(a) (0x0c84| (a)) /* config. RAM */
101#define C1A(a) (0x0ca0| (a)) /* IRQ-, DMA-nr., EPROM type */
102#define C2A(a) (0x0ca4| (a)) /* EPROM and PAGE selector */
103
104#define CONF C0A(0) /* config RAM (card enable bit port) */
105#define PGRA C2A(0) /* Flash page register */
106#define CDID PRA(0) /* Card ID I/O port addr. offset */
107
108
109/*
110 * physical address offset + slot specific IO-Port base address
111 */
112#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
113#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
114#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
115#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
116#define PR_A(a) (PRA(a)+smc->hw.iop) /* config. PROM */
117#define C0_A(a) (C0A(a)+smc->hw.iop) /* config. RAM */
118#define C1_A(a) (C1A(a)+smc->hw.iop) /* config. RAM */
119#define C2_A(a) (C2A(a)+smc->hw.iop) /* config. RAM */
120
121
122#define CSRA 0x0008 /* control/status register address (r/w) */
123#define ISRA 0x0008 /* int. source register address (upper 8Bits) */
124#define PLC1I 0x001a /* clear PLC1 interrupt (write only) */
125#define PLC2I 0x0020 /* clear PLC2 interrupt (write only) */
126#define CSFA 0x001c /* control/status FIFO BUSY flags (read only) */
127#define RQAA 0x001c /* Request reg. (write only) */
128#define WCTA 0x001e /* word counter (r/w) */
129#define FFLAG 0x005e /* FLAG/V_FULL (FIFO almost full, write only)*/
130
131#define CSR_A (CSRA+smc->hw.iop) /* control/status register address (r/w) */
132#ifdef UNIX
133#define CSR_AS(smc) (CSRA+(smc)->hw.iop) /* control/status register address (r/w) */
134#endif
135#define ISR_A (ISRA+smc->hw.iop) /* int. source register address (upper 8Bits) */
136#define PLC1_I (PLC1I+smc->hw.iop) /* clear PLC1 internupt (write only) */
137#define PLC2_I (PLC2I+smc->hw.iop) /* clear PLC2 interrupt (write only) */
138#define CSF_A (CSFA+smc->hw.iop) /* control/status FIFO BUSY flags (r/w) */
139#define RQA_A (RQAA+smc->hw.iop) /* Request reg. (write only) */
140#define WCT_A (WCTA+smc->hw.iop) /* word counter (r/w) */
141#define FFLAG_A (FFLAG+smc->hw.iop) /* FLAG/V_FULL (FIFO almost full, write only)*/
142
143/*
144 * control/status register CSRA bits
145 */
146/* write */
147#define CS_CRESET 0x01 /* Card reset (0=reset) */
148#define CS_RESET_FIFO 0x02 /* FIFO reset (0=reset) */
149#define CS_IMSK 0x04 /* enable IRQ (1=enable, 0=disable) */
150#define CS_EN_IRQ_TC 0x08 /* enable IRQ from transfer counter */
151#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/
152#define CS_LED_0 0x40 /* switch LED 0 */
153#define CS_LED_1 0x80 /* switch LED 1 */
154/* read */
155#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */
156#define CS_SAS 0x80 /* single attachement station (=1) */
157
158/*
159 * control/status register CSFA bits (FIFO)
160 */
161#define CSF_MUX0 0x01
162#define CSF_MUX1 0x02
163#define CSF_HSREQ0 0x04
164#define CSF_HSREQ1 0x08
165#define CSF_HSREQ2 0x10
166#define CSF_BUSY_DMA 0x40
167#define CSF_BUSY_FIFO 0x80
168
169/*
170 * Interrupt source register ISRA (upper 8 data bits) read only & low activ.
171 */
172#define IS_MINTR1 0x0100 /* FORMAC ST1U/L & ~IMSK1U/L*/
173#define IS_MINTR2 0x0200 /* FORMAC ST2U/L & ~IMSK2U/L*/
174#define IS_PLINT1 0x0400 /* PLC1 */
175#define IS_PLINT2 0x0800 /* PLC2 */
176#define IS_TIMINT 0x1000 /* Timer 82C54-2 */
177#define IS_TC 0x2000 /* transf. counter */
178
179#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT|IS_TC)
180
181/*
182 * CONFIG<0> RAM (C0_A())
183 */
184#define CFG_CARD_EN 0x01 /* card enable */
185
186/*
187 * CONFIG<1> RAM (C1_A())
188 */
189#define CFG_IRQ_SEL 0x03 /* IRQ select (4 nr.) */
190#define CFG_IRQ_TT 0x04 /* IRQ trigger type (LEVEL/EDGE) */
191#define CFG_DRQ_SEL 0x18 /* DMA requ. (4 nr.) */
192#define CFG_BOOT_EN 0x20 /* 0=BOOT-, 1=Application Software */
193#define CFG_PROG_EN 0x40 /* V_Prog for FLASH_PROM (1=on) */
194
195/*
196 * CONFIG<2> RAM (C2_A())
197 */
198#define CFG_EPROM_SEL 0x0f /* FPROM start address selection */
199#define CFG_PAGE 0xf0 /* FPROM page selection */
200
201
202#define READ_PROM(a) ((u_char)inp(a))
203#define GET_PAGE(i) outp(C2_A(0),((int)(i)<<4) | (inp(C2_A(0)) & ~CFG_PAGE))
204#define FPROM_SW() (inp(C1_A(0)) & CFG_BOOT_EN)
205
206#define MAX_PAGES 16 /* 16 pages */
207#define MAX_FADDR 0x2000 /* 8K per page */
208#define VPP_ON() outp(C1_A(0),inp(C1_A(0)) | CFG_PROG_EN)
209#define VPP_OFF() outp(C1_A(0),inp(C1_A(0)) & ~CFG_PROG_EN)
210
211#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA)
212#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO)
213#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
214#define BUS_CHECK()
215
216#ifdef UNISYS
217/* For UNISYS use another macro with drv_usecewait function */
218#define CHECK_DMA() {u_long k = 1000000; \
219 while (k && (DMA_BUSY())) { k--; drv_usecwait(20); } \
220 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
221#else
222#define CHECK_DMA() {u_long k = 1000000 ;\
223 while (k && (DMA_BUSY())) k-- ;\
224 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
225#endif
226
227#define CHECK_FIFO() {u_long k = 1000000 ;\
228 while (k && (FIFO_BUSY())) k-- ;\
229 if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
230
231#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\
232 while (k && (DMA_FIFO_BUSY())) k-- ;\
233 if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
234
235#define GET_ISR() ~inpw(ISR_A)
236#define CHECK_ISR() ~inpw(ISR_A)
237
238#ifndef UNIX
239#ifndef WINNT
240#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&\
241 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
242#else /* WINNT */
243#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A)&\
244 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|smc->hw.led)
245#endif /* WINNT */
246#else /* UNIX */
247#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
248 (CS_CRESET|CS_BYPASS))|CS_RESET_FIFO|(smc)->hw.led)
249#endif
250
251#ifndef UNIX
252#define STI_FBI() outpw(CSR_A,(inpw(CSR_A)&\
253 (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|smc->hw.led)
254#else
255#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))&\
256 (CS_CRESET|CS_BYPASS|CS_RESET_FIFO))|CS_IMSK|(smc)->hw.led)
257#endif
258
259/* EISA DMA Controller */
260#define DMA_WRITE_SINGLE_MASK_BIT_M 0x0a /* Master DMA Controller */
261#define DMA_WRITE_SINGLE_MASK_BIT_S 0xd4 /* Slave DMA Controller */
262#define DMA_CLEAR_BYTE_POINTER_M 0x0c
263#define DMA_CLEAR_BYTE_POINTER_S 0xd8
264
265#endif /* EISA */
266
267#ifdef MCA
268
269/*
270 * POS Register: !! all I/O's are 8-Bit !!
271 */
272#define POS_SYS_SETUP 0x94 /* system setup register */
273#define POS_SYSTEM 0xff /* system mode */
274
275#define POS_CHANNEL_POS 0x96 /* register slot ID */
276#define POS_CHANNEL_BIT 0x08 /* mask for -"- */
277
278#define POS_BASE 0x100 /* POS base address */
279#define POS_ID_LOW POS_BASE /* card ID low */
280#define POS_ID_HIGH (POS_BASE+1) /* card ID high */
281#define POS_102 (POS_BASE+2) /* card en., arbitration level .. */
282#define POS_103 (POS_BASE+3) /* FPROM addr, page */
283#define POS_104 (POS_BASE+4) /* I/O, IRQ */
284#define POS_105 (POS_BASE+5) /* POS_CHCK */
285#define POS_106 (POS_BASE+6) /* to read VPD */
286#define POS_107 (POS_BASE+7) /* added without function */
287
288/* FM1 card IDs */
289#define FM1_CARD_ID0 0x83
290#define FM1_CARD_ID1 0
291
292#define FM1_IBM_ID0 0x9c
293#define FM1_IBM_ID1 0x8f
294
295
296/* FM2 card IDs */
297#define FM2_CARD_ID0 0xab
298#define FM2_CARD_ID1 0
299
300#define FM2_IBM_ID0 0x7e
301#define FM2_IBM_ID1 0x8f
302
303/* Board revision. */
304#define FM1_REV 0
305#define FM2_REV 1
306
307#define MAX_SLOT 8
308
309/*
310 * POS_102
311 */
312#define POS_CARD_EN 0x01 /* card enable =1 */
313#define POS_SDAT_EN 0x02 /* enable 32-bit streaming data mode */
314#define POS_EN_CHKINT 0x04 /* enable int. from check line asserted */
315#define POS_EN_BUS_ERR 0x08 /* enable int. on invalid busmaster transf. */
316#define POS_FAIRNESS 0x10 /* fairnes on =1 */
317/* attention: arbitration level used with bit 0 POS 105 */
318#define POS_LARBIT 0xe0 /* arbitration level (0,0,0)->level = 0x8
319 (1,1,1)->level = 0xf */
320/*
321 * POS_103
322 */
323#define POS_PAGE 0x07 /* FPROM page selection */
324#define POS_BOOT_EN 0x08 /* boot PROM enable =1 */
325#define POS_MSEL 0x70 /* memory start address for FPROM mapping */
326#define PROG_EN 0x80 /* FM1: Vpp prog on/off */
327#define POS_SDR 0x80 /* FM2: Streaming data bit */
328
329/*
330 * POS_104
331 */
332#define POS_IOSEL 0x3f /* selected I/O base address */
333#define POS_IRQSEL 0xc0 /* selected interrupt */
334
335/*
336 * POS_105
337 */
338#define POS_CHCK 0x80
339#define POS_SYNC_ERR 0x20 /* FM2: synchronous error reporting */
340#define POS_PAR_DATA 0x10 /* FM2: data parity enable bit */
341#define POS_PAR_ADDR 0x08 /* FM2: address parity enable bit */
342#define POS_IRQHSEL 0x02 /* FM2: Highest bit for IRQ_selection */
343#define POS_HARBIT 0x01 /* Highest bit in Bus arbitration selection */
344
345#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
346#define PRA_OFF (0)
347#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
348
349/*
350 * address transmission from logical to physical offset address on board
351 */
352#define FMA(a) (0x0100|((a)<<1)) /* FORMAC+ (r/w) */
353#define P2(a) (0x00c0|((a)<<1)) /* PLC2 (r/w) (DAS) */
354#define P1(a) (0x0080|((a)<<1)) /* PLC1 (r/w) */
355#define TI(a) (0x0060|((a)<<1)) /* Timer (r/w) */
356#define PR(a) (0x0040|((a)<<1)) /* configuration PROM */
357#define CS(a) (0x0020| (a)) /* control/status */
358#define FF(a) (0x0010|((a)<<1)) /* FIFO ASIC */
359#define CT(a) (0x0000|((a)<<1)) /* counter */
360
361/*
362 * counter
363 */
364#define ACLA CT(0) /* address counter low */
365#define ACHA CT(1) /* address counter high */
366#define BCN CT(2) /* byte counter */
367#define MUX CT(3) /* MUX-register */
368#define WCN CT(0x08) /* word counter */
369#define FFLG CT(0x09) /* FIFO Flags */
370
371/*
372 * test/control register (FM2 only)
373 */
374#define CNT_TST 0x018 /* Counter test control register */
375#define CNT_STP 0x01a /* Counter test step reg. (8 Bit) */
376
377/*
378 * CS register (read only)
379 */
380#define CSRA CS(0) /* control/status register address */
381#define CSFA CS(2) /* control/status FIFO BUSY ... */
382#define ISRA CS(4) /* first int. source register address */
383#define ISR2 CS(6) /* second int. source register address */
384#define LEDR CS(0x0c) /* LED register r/w */
385#define CSIL CS(0x10) /* I/O mapped POS_ID_low (100) */
386#define CSIH CS(0x12) /* - " - POS_ID_HIGH (101) */
387#define CSA CS(0x14) /* - " - POS_102 */
388#define CSM CS(0x0e) /* - " - POS_103 */
389#define CSM_FM1 CS(0x16) /* - " - POS_103 (copy in FM1) */
390#define CSI CS(0x18) /* - " - POS_104 */
391#define CSS CS(0x1a) /* - " - POS_105 */
392#define CSP_06 CS(0x1c) /* - " - POS_106 */
393#define WDOG_ST 0x1c /* Watchdog status (FM2 only) */
394#define WDOG_EN 0x1c /* Watchdog enabling (FM2 only, 8Bit) */
395#define WDOG_DIS 0x1e /* Watchdog disabling (FM2 only, 8Bit) */
396
397#define PGRA CSM /* Flash page register */
398
399
400#define WCTA FF(0) /* word counter */
401#define FFLAG FF(1) /* FLAG/V_FULL (FIFO almost full, write only)*/
402
403/*
404 * Timer register (FM2 only)
405 */
406#define RTM_CNT 0x28 /* RTM Counter */
407#define TI_DIV 0x60 /* Timer Prescaler */
408#define TI_CH1 0x62 /* Timer channel 1 counter */
409#define TI_STOP 0x64 /* Stop timer on channel 1 */
410#define TI_STRT 0x66 /* Start timer on channel 1 */
411#define TI_INI2 0x68 /* Timer: Bus master preemption */
412#define TI_CNT2 0x6a /* Timer */
413#define TI_INI3 0x6c /* Timer: Streaming data */
414#define TI_CNT3 0x6e /* Timer */
415#define WDOG_LO 0x70 /* Watchdog counter low */
416#define WDOG_HI 0x72 /* Watchdog counter high */
417#define RTM_PRE 0x74 /* restr. token prescaler */
418#define RTM_TIM 0x76 /* restr. token timer */
419
420/*
421 * Recommended Timeout values (for FM2 timer only)
422 */
423#define TOUT_BM_PRE 188 /* 3.76 usec */
424#define TOUT_S_DAT 374 /* 7.48 usec */
425
426/*
427 * CS register (write only)
428 */
429#define HSR(p) CS(0x18|(p)) /* Host request register */
430
431#define RTM_PUT 0x36 /* restr. token counter write */
432#define RTM_GET 0x28 /* - " - clear */
433#define RTM_CLEAR 0x34 /* - " - read */
434
435/*
436 * BCN Bit definitions
437 */
438#define BCN_BUSY 0x8000 /* DMA Busy flag */
439#define BCN_AZERO 0x4000 /* Almost zero flag (BCN < 4) */
440#define BCN_STREAM 0x2000 /* Allow streaming data (BCN >= 8) */
441
442/*
443 * WCN Bit definitions
444 */
445#define WCN_ZERO 0x2000 /* Zero flag (counted to zero) */
446#define WCN_AZERO 0x1000 /* Almost zero flag (BCN < 4) */
447
448/*
449 * CNT_TST Bit definitions
450 */
451#define CNT_MODE 0x01 /* Go into test mode */
452#define CNT_D32 0x02 /* 16/32 BIT test mode */
453
454/*
455 * FIFO Flag FIFO Flags/Vfull register
456 */
457#define FF_VFULL 0x003f /* V_full value mask */
458#define FFLG_FULL 0x2000 /* FULL flag */
459#define FFLG_A_FULL 0x1000 /* Almost full flag */
460#define FFLG_VFULL 0x0800 /* V_full Flag */
461#define FFLG_A_EMP 0x0400 /* almost empty flag */
462#define FFLG_EMP 0x0200 /* empty flag */
463#define FFLG_T_EMP 0x0100 /* totally empty flag */
464
465/*
466 * WDOG Watchdog status register
467 */
468#define WDOG_ALM 0x01 /* Watchdog alarm Bit */
469#define WDOG_ACT 0x02 /* Watchdog active Bit */
470
471/*
472 * CS(0) CONTROLS
473 */
474#define CS_CRESET 0x0001
475#define FIFO_RST 0x0002
476#define CS_IMSK 0x0004
477#define EN_IRQ_CHCK 0x0008
478#define EN_IRQ_TOKEN 0x0010
479#define EN_IRQ_TC 0x0020
480#define TOKEN_STATUS 0x0040
481#define RTM_CHANGE 0x0080
482
483#define CS_SAS 0x0100
484#define CS_BYSTAT 0x0200 /* bypass connected (0=conn.) */
485#define CS_BYPASS 0x0400 /* bypass on/off indication */
486
487/*
488 * CS(2) FIFOSTAT
489 */
490#define HSREQ 0x0007
491#define BIGDIR 0x0008
492#define CSF_BUSY_FIFO 0x0010
493#define CSF_BUSY_DMA 0x0020
494#define SLOT_32 0x0040
495
496#define LED_0 0x0001
497#define LED_1 0x0002
498#define LED_2 0x0100
499
500#define MAX_PAGES 8 /* pages */
501#define MAX_FADDR 0x4000 /* 16K per page */
502
503/*
504 * IRQ = ISRA || ISR2 ;
505 *
506 * ISRA = IRQ_OTH_EN && (IS_LAN | IS_BUS) ;
507 * ISR2 = IRQ_TC_EN && IS_TC ;
508 *
509 * IS_LAN = (IS_MINTR1 | IS_MINTR2 | IS_PLINT1 | IS_PLINT2 | IS_TIMINT) ||
510 * (IRQ_EN_TOKEN && IS_TOKEN) ;
511 * IS_BUS = IRQ_CHCK_EN && (IS_BUSERR | IS_CHCK_L) ;
512 */
513/*
514 * ISRA !!! activ high !!!
515 */
516#define IS_MINTR1 0x0001 /* FORMAC ST1U/L & ~IMSK1U/L*/
517#define IS_MINTR2 0x0002 /* FORMAC ST2U/L & ~IMSK2U/L*/
518#define IS_PLINT1 0x0004 /* PLC1 */
519#define IS_PLINT2 0x0008 /* PLC2 */
520#define IS_TIMINT 0x0010 /* Timer 82C54-2 */
521#define IS_TOKEN 0x0020 /* restrictet token monitoring */
522#define IS_CHCK_L 0x0040 /* check line asserted */
523#define IS_BUSERR 0x0080 /* bus error */
524/*
525 * ISR2
526 */
527#define IS_TC 0x0001 /* terminal count irq */
528#define IS_SFDBKRTN 0x0002 /* selected feedback return */
529#define IS_D16 0x0004 /* DS16 */
530#define IS_D32 0x0008 /* DS32 */
531#define IS_DPEI 0x0010 /* Data Parity Indication */
532
533#define ALL_IRSR 0x00ff
534
535#define FM_A(a) ADDR(FMA(a)) /* FORMAC Plus physical addr */
536#define P1_A(a) ADDR(P1(a)) /* PLC1 (r/w) */
537#define P2_A(a) ADDR(P2(a)) /* PLC2 (r/w) (DAS) */
538#define TI_A(a) ADDR(TI(a)) /* Timer (r/w) FM1 only! */
539#define PR_A(a) ADDR(PR(a)) /* config. PROM */
540#define CS_A(a) ADDR(CS(a)) /* control/status */
541
542#define ISR1_A ADDR(ISRA) /* first int. source register address */
543#define ISR2_A ADDR(ISR2) /* second -"- */
544#define CSR_A ADDR(CSRA) /* control/status register address */
545#define CSF_A ADDR(CSFA) /* control/status FIFO BUSY flags (r/w) */
546
547#define CSIL_A ADDR(CSIL) /* I/O mapped POS_ID_low (102) */
548#define CSIH_A ADDR(CSIH) /* - " - POS_ID_HIGH (101) */
549#define CSA_A ADDR(CSA) /* - " - POS_102 */
550#define CSI_A ADDR(CSI) /* - " - POS_104 */
551#define CSM_A ADDR(CSM) /* - " - POS_103 */
552#define CSM_FM1_A ADDR(CSM_FM1) /* - " - POS_103 (2nd copy, FM1) */
553#define CSP_06_A ADDR(CSP_06) /* - " - POS_106 */
554
555#define WCT_A ADDR(WCTA) /* word counter (r/w) */
556#define FFLAG_A ADDR(FFLAG) /* FLAG/V_FULL (FIFO almost full, write only)*/
557
558#define ACL_A ADDR(ACLA) /* address counter low */
559#define ACH_A ADDR(ACHA) /* address counter high */
560#define BCN_A ADDR(BCN) /* byte counter */
561#define MUX_A ADDR(MUX) /* MUX-register */
562
563#define ISR_A ADDR(ISRA) /* Interrupt Source Register */
564#define FIFO_RESET_A ADDR(FIFO_RESET) /* reset the FIFO */
565#define FIFO_EN_A ADDR(FIFO_EN) /* enable the FIFO */
566
567#define WDOG_EN_A ADDR(WDOG_EN) /* reset and start the WDOG */
568#define WDOG_DIS_A ADDR(WDOG_DIS) /* disable the WDOG */
569/*
570 * all control reg. (read!) are 8 bit (except PAGE_RG_A and LEDR_A)
571 */
572#define HSR_A(p) ADDR(HSR(p)) /* Host request register */
573
574#define STAT_BYP 0 /* bypass station */
575#define STAT_INS 2 /* insert station */
576#define BYPASS(o) CS(0x10|(o)) /* o=STAT_BYP || STAT_INS */
577
578#define IRQ_TC_EN CS(0x0b) /* enable/disable IRQ on TC */
579#define IRQ_TC_DIS CS(0x0a)
580#define IRQ_TOKEN_EN CS(9) /* enable/disable IRQ on restr. Token */
581#define IRQ_TOKEN_DIS CS(8)
582#define IRQ_CHCK_EN CS(7) /* -"- IRQ after CHCK line */
583#define IRQ_CHCK_DIS CS(6)
584#define IRQ_OTH_EN CS(5) /* -"- other IRQ's */
585#define IRQ_OTH_DIS CS(4)
586#define FIFO_EN CS(3) /* disable (reset), enable FIFO */
587#define FIFO_RESET CS(2)
588#define CARD_EN CS(1) /* disable (reset), enable card */
589#define CARD_DIS CS(0)
590
591#define LEDR_A ADDR(LEDR) /* D0=green, D1=yellow, D8=L2 */
592#define PAGE_RG_A ADDR(CSM) /* D<2..0> */
593#define IRQ_CHCK_EN_A ADDR(IRQ_CHCK_EN)
594#define IRQ_CHCK_DIS_A ADDR(IRQ_CHCK_DIS)
595
596#define GET_PAGE(bank) outpw(PAGE_RG_A,(inpw(PAGE_RG_A) &\
597 (~POS_PAGE)) |(int) (bank))
598#define VPP_ON() if (smc->hw.rev == FM1_REV) { \
599 outpw(PAGE_RG_A, \
600 (inpw(PAGE_RG_A) & POS_PAGE) | PROG_EN); \
601 }
602#define VPP_OFF() if (smc->hw.rev == FM1_REV) { \
603 outpw(PAGE_RG_A,(inpw(PAGE_RG_A) & POS_PAGE)); \
604 }
605
606#define SKFDDI_PSZ 16 /* address PROM size */
607
608#define READ_PROM(a) ((u_char)inp(a))
609
610#define GET_ISR() ~inpw(ISR1_A)
611#ifndef TCI
612#define CHECK_ISR() ~inpw(ISR1_A)
613#define CHECK_ISR_SMP(iop) ~inpw((iop)+ISRA)
614#else
615#define CHECK_ISR() (~inpw(ISR1_A) | ~inpw(ISR2_A))
616#define CHECK_ISR_SMP(iop) (~inpw((iop)+ISRA) | ~inpw((iop)+ISR2))
617#endif
618
619#define DMA_BUSY() (inpw(CSF_A) & CSF_BUSY_DMA)
620#define FIFO_BUSY() (inpw(CSF_A) & CSF_BUSY_FIFO)
621#define DMA_FIFO_BUSY() (inpw(CSF_A) & (CSF_BUSY_DMA | CSF_BUSY_FIFO))
622#define BUS_CHECK() { int i ; \
623 if ((i = GET_ISR()) & IS_BUSERR) \
624 SMT_PANIC(smc,HWM_E0020,HWM_E0020_MSG) ; \
625 if (i & IS_CHCK_L) \
626 SMT_PANIC(smc,HWM_E0014,HWM_E0014_MSG) ; \
627 }
628
629#define CHECK_DMA() { u_long k = 10000 ; \
630 while (k && (DMA_BUSY())) { \
631 k-- ; \
632 BUS_CHECK() ; \
633 } \
634 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
635
636#define CHECK_FIFO() {u_long k = 1000000 ;\
637 while (k && (FIFO_BUSY())) k-- ;\
638 if (!k) SMT_PANIC(smc,HWM_E0019,HWM_E0019_MSG) ; }
639
640#define CHECK_DMA_FIFO() {u_long k = 1000000 ;\
641 while (k && (DMA_FIFO_BUSY())) { \
642 k-- ;\
643 BUS_CHECK() ; \
644 } \
645 if (!k) SMT_PANIC(smc,HWM_E0004,HWM_E0004_MSG) ; }
646
647#ifndef UNIX
648#define CLI_FBI() outp(ADDR(IRQ_OTH_DIS),0)
649#else
650#define CLI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_DIS),0)
651#endif
652
653#ifndef TCI
654#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0)
655#else
656#define CLI_FBI_SMP(iop) outp((iop)+IRQ_OTH_DIS,0) ;\
657 outp((iop)+IRQ_TC_DIS,0)
658#endif
659
660#ifndef UNIX
661#define STI_FBI() outp(ADDR(IRQ_OTH_EN),0)
662#else
663#define STI_FBI(smc) outp(ADDRS((smc),IRQ_OTH_EN),0)
664#endif
665
666/*
667 * Terminal count primitives
668 */
669#define CLI_TCI(smc) outp(ADDRS((smc),IRQ_TC_DIS),0)
670#define STI_TCI(smc) outp(ADDRS((smc),IRQ_TC_EN),0)
671#define CHECK_TC(smc,k) {(k) = 10000 ;\
672 while ((k) && (~inpw(ISR2_A) & IS_TC)) (k)-- ;\
673 if (!k) SMT_PANIC(smc,HWM_E0018,HWM_E0018_MSG) ; }
674
675#endif /* MCA */
676
677#ifdef ISA
678
679/*
680 * address transmission from logic NPADDR6-0 to physical offset address on board
681 */
682#define FMA(a) (0x8000|(((a)&0x07)<<1)|(((a)&0x78)<<7)) /* FORMAC+ (r/w) */
683#define PRA(a) (0x1000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PROM (read only)*/
684#define P1A(a) (0x4000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC1 (r/w) */
685#define P2A(a) (0x5000|(((a)&0x07)<<1)|(((a)&0x18)<<7)) /* PLC2 (r/w) */
686#define TIA(a) (0x6000|(((a)&0x03)<<1)) /* Timer (r/w) */
687
688#define ISRA 0x0000 /* int. source register address (read only) */
689#define ACLA 0x0000 /* address counter low address (write only) */
690#define ACHA 0x0002 /* address counter high address (write only) */
691#define TRCA 0x0004 /* transfer counter address (write only) */
692#define PGRA 0x0006 /* page register address (write only) */
693#define RQAA 0x2000 /* Request reg. (write only) */
694#define CSRA 0x3000 /* control/status register address (r/w) */
695
696/*
697 * physical address offset + IO-Port base address
698 */
699#define FM_A(a) (FMA(a)+smc->hw.iop) /* FORMAC Plus physical addr */
700#define PR_A(a) (PRA(a)+smc->hw.iop) /* PROM (read only)*/
701#define P1_A(a) (P1A(a)+smc->hw.iop) /* PLC1 (r/w) */
702#define P2_A(a) (P2A(a)+smc->hw.iop) /* PLC2 (r/w) */
703#define TI_A(a) (TIA(a)+smc->hw.iop) /* Timer (r/w) */
704
705#define ISR_A (0x0000+smc->hw.iop) /* int. source register address (read only) */
706#define ACL_A (0x0000+smc->hw.iop) /* address counter low address (write only) */
707#define ACH_A (0x0002+smc->hw.iop) /* address counter high address (write only)*/
708#define TRC_A (0x0004+smc->hw.iop) /* transfer counter address (write only) */
709#define PGR_A (0x0006+smc->hw.iop) /* page register address (write only) */
710#define RQA_A (0x2000+smc->hw.iop) /* Request reg. (write only) */
711#define CSR_A (0x3000+smc->hw.iop) /* control/status register address (r/w) */
712#ifdef UNIX
713#define CSR_AS(smc) (0x3000+(smc)->hw.iop) /* control/status register address */
714#endif
715#define PLC1_I (0x3400+smc->hw.iop) /* clear PLC1 interrupt bit */
716#define PLC2_I (0x3800+smc->hw.iop) /* clear PLC2 interrupt bit */
717
718#ifndef MULT_OEM
719#ifndef OEM_CONCEPT
720#define SKLOGO_STR "SKFDDI"
721#else /* OEM_CONCEPT */
722#define SKLOGO_STR OEM_FDDI_LOGO
723#endif /* OEM_CONCEPT */
724#endif /* MULT_OEM */
725#define SADDRL (24) /* start address SKLOGO */
726#define SA_MAC (0) /* start addr. MAC_AD within the PROM */
727#define PRA_OFF (0)
728#define SA_PMD_TYPE (8) /* start addr. PMD-Type */
729
730#define CDID (PRA(SADDRL)) /* Card ID int/O port addr. offset */
731#define NEXT_CDID ((PRA(SADDRL+1)) - CDID)
732
733#define SKFDDI_PSZ 32 /* address PROM size */
734
735#define READ_PROM(a) ((u_char)inpw(a))
736#define GET_PAGE(i) outpw(PGR_A,(int)(i))
737
738#define MAX_PAGES 16 /* 16 pages */
739#define MAX_FADDR 0x2000 /* 8K per page */
740#define VPP_OFF() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)))
741#define VPP_ON() outpw(CSR_A,(inpw(CSR_A) & (CS_CRESET|CS_BYPASS)) | \
742 CS_VPPSW)
743
744/*
745 * control/status register CSRA bits (log. addr: 0x3000)
746 */
747/* write */
748#define CS_CRESET 0x01 /* Card reset (0=reset) */
749#define CS_IMSK 0x02 /* enable IRQ (1=enable, 0=disable) */
750#define CS_RESINT1 0x04 /* PLINT1 reset */
751#define CS_VPPSW 0x10 /* 12V power switch (0=off, 1=on) */
752#define CS_BYPASS 0x20 /* bypass switch (0=remove, 1=insert)*/
753#define CS_RESINT2 0x40 /* PLINT2 reset */
754/* read */
755#define CS_BUSY 0x04 /* master transfer activ (=1) */
756#define CS_SW_EPROM 0x08 /* 0=Application Soft. 1=BOOT-EPROM */
757#define CS_BYSTAT 0x40 /* 0=Bypass exist, 1= ..not */
758#define CS_SAS 0x80 /* single attachement station (=1) */
759
760/*
761 * Interrupt source register ISRA (log. addr: 0x0000) read only & low activ.
762 */
763#define IS_MINTR1 0x01 /* FORMAC ST1U/L && ~IMSK1U/L*/
764#define IS_MINTR2 0x02 /* FORMAC ST2U/L && ~IMSK2U/L*/
765#define IS_PLINT1 0x04 /* PLC1 */
766#define IS_PLINT2 0x08 /* PLC2 */
767#define IS_TIMINT 0x10 /* Timer 82C54-2 */
768
769#define ALL_IRSR (IS_MINTR1|IS_MINTR2|IS_PLINT1|IS_PLINT2|IS_TIMINT)
770
771#define FPROM_SW() (inpw(CSR_A)&CS_SW_EPROM)
772#define DMA_BUSY() (inpw(CSR_A)&CS_BUSY)
773#define CHECK_FIFO()
774#define BUS_CHECK()
775
776/*
777 * set Host Request register (wr.)
778 */
779#define SET_HRQ(qup) outpw(RQA_A+((qup)<<1),0)
780
781#ifndef UNIX
782#ifndef WINNT
783#define CLI_FBI() outpw(CSR_A,(inpw(CSR_A)&(CS_CRESET|CS_BYPASS|CS_VPPSW)))
784#else
785#define CLI_FBI() outpw(CSR_A,(l_inpw(CSR_A) & \
786 (CS_CRESET|CS_BYPASS|CS_VPPSW)))
787#endif
788#else
789#define CLI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc))& \
790 (CS_CRESET|CS_BYPASS|CS_VPPSW)))
791#endif
792
793#ifndef UNIX
794#define STI_FBI() outpw(CSR_A,(inpw(CSR_A) & \
795 (CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
796#else
797#define STI_FBI(smc) outpw(CSR_AS(smc),(inpw(CSR_AS(smc)) & \
798 (CS_CRESET|CS_BYPASS|CS_VPPSW)) | CS_IMSK)
799#endif
800
801#define CHECK_DMA() {unsigned k = 10000 ;\
802 while (k && (DMA_BUSY())) k-- ;\
803 if (!k) SMT_PANIC(smc,HWM_E0003,HWM_E0003_MSG) ; }
804
805#define GET_ISR() ~inpw(ISR_A)
806
807#endif /* ISA */
808
809/*--------------------------------------------------------------------------*/ 28/*--------------------------------------------------------------------------*/
810#ifdef PCI 29#ifdef PCI
811 30
diff --git a/drivers/net/skfp/h/skfbiinc.h b/drivers/net/skfp/h/skfbiinc.h
index 79d55ad2cd2a..ac2d7192f1ca 100644
--- a/drivers/net/skfp/h/skfbiinc.h
+++ b/drivers/net/skfp/h/skfbiinc.h
@@ -22,32 +22,6 @@
22 */ 22 */
23#define ERR_FLAGS (FS_MSRABT | FS_SEAC2 | FS_SFRMERR | FS_SFRMTY1) 23#define ERR_FLAGS (FS_MSRABT | FS_SEAC2 | FS_SFRMERR | FS_SFRMTY1)
24 24
25#ifdef ISA
26#define DMA_BUSY_CHECK CSRA
27#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT)
28#define HRQR (RQAA+(RQ_RRQ<<1))
29#define HRQW (RQAA+(RQ_WA2<<1))
30#define HRQA0 (RQAA+(RQ_WA0<<1))
31#define HRQSQ (RQAA+(RQ_WSQ<<1))
32#endif
33
34#ifdef EISA
35#define DMA_BUSY_CHECK CSRA
36#define DMA_HIGH_WORD 0x0400
37#define DMA_MASK_M 0x0a
38#define DMA_MODE_M 0x0b
39#define DMA_BYTE_PTR_M 0x0c
40#define DMA_MASK_S 0x0d4
41#define DMA_MODE_S 0x0d6
42#define DMA_BYTE_PTR_S 0x0d8
43#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TC)
44#endif /* EISA */
45
46#ifdef MCA
47#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
48 IS_CHCK_L | IS_BUSERR)
49#endif
50
51#ifdef PCI 25#ifdef PCI
52#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \ 26#define IMASK_FAST (IS_PLINT1 | IS_PLINT2 | IS_TIMINT | IS_TOKEN | \
53 IS_MINTR2 | IS_MINTR3 | IS_R1_P | \ 27 IS_MINTR2 | IS_MINTR3 | IS_R1_P | \
diff --git a/drivers/net/skfp/h/targethw.h b/drivers/net/skfp/h/targethw.h
index 22c4923241d3..626dc7263591 100644
--- a/drivers/net/skfp/h/targethw.h
+++ b/drivers/net/skfp/h/targethw.h
@@ -53,11 +53,6 @@ struct s_oem_ids {
53 u_char oi_sub_id[4] ; /* sub id bytes, representation as */ 53 u_char oi_sub_id[4] ; /* sub id bytes, representation as */
54 /* defined by hardware, */ 54 /* defined by hardware, */
55#endif 55#endif
56#ifdef ISA
57 u_char oi_logo_len ; /* the length of the adapter logo */
58 u_char oi_logo[6] ; /* the adapter logo */
59 u_char oi_reserved1 ;
60#endif /* ISA */
61} ; 56} ;
62#endif /* MULT_OEM */ 57#endif /* MULT_OEM */
63 58
@@ -70,43 +65,17 @@ struct s_smt_hw {
70 short dma ; /* DMA channel */ 65 short dma ; /* DMA channel */
71 short irq ; /* IRQ level */ 66 short irq ; /* IRQ level */
72 short eprom ; /* FLASH prom */ 67 short eprom ; /* FLASH prom */
73#ifndef PCI
74 short DmaWriteExtraBytes ; /* add bytes for DMA write */
75#endif
76 68
77#ifndef SYNC 69#ifndef SYNC
78 u_short n_a_send ; /* pending send requests */ 70 u_short n_a_send ; /* pending send requests */
79#endif 71#endif
80 72
81#if (defined(EISA) || defined(MCA) || defined(PCI)) 73#if defined(PCI)
82 short slot ; /* slot number */ 74 short slot ; /* slot number */
83 short max_slots ; /* maximum number of slots */ 75 short max_slots ; /* maximum number of slots */
84#endif
85
86#if (defined(PCI) || defined(MCA))
87 short wdog_used ; /* TRUE if the watch dog is used */ 76 short wdog_used ; /* TRUE if the watch dog is used */
88#endif 77#endif
89 78
90#ifdef MCA
91 short slot_32 ; /* 32bit slot (1) or 16bit slot (0) */
92 short rev ; /* Board revision (FMx_REV). */
93 short VFullRead ; /* V_full value for DMA read */
94 short VFullWrite ; /* V_full value for DMA write */
95#endif
96
97#ifdef EISA
98 short led ; /* LED for FE card */
99
100 short dma_rmode ; /* read mode */
101 short dma_wmode ; /* write mode */
102 short dma_emode ; /* extend mode */
103
104 /* DMA controller channel dependent io addresses */
105 u_short dma_base_word_count ;
106 u_short dma_base_address ;
107 u_short dma_base_address_page ;
108#endif
109
110#ifdef PCI 79#ifdef PCI
111 u_short pci_handle ; /* handle to access the BIOS func */ 80 u_short pci_handle ; /* handle to access the BIOS func */
112 u_long is_imask ; /* int maske for the int source reg */ 81 u_long is_imask ; /* int maske for the int source reg */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 12:25:39 -0500