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authorDaniele Venzano <venza@brownhat.org>2005-10-11 03:44:30 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-28 16:48:19 -0400
commitea37ccea66e6bdd9f3571418b6461850088c114e (patch)
tree93e543532a6c2959602d3d01384544c398b4f551 /drivers/net/sis900.h
parent7380a78a973a8109c13cb0e47617c456b6f6e1f5 (diff)
[PATCH] Add Wake on LAN support to sis900 (2)
Sorry, but that day I had smoked somthing too heavy for me, the patch didn't apply. Here's a new one. The patch availble below adds support for Wake on LAN to the sis900 driver. Some register addresses were added to sis900.h and two new functions were implemented in sis900.c. WoL status is controlled by ethtool. Patch is against 2.6.13. Comments are welcome, but also consider for inclusion in the -mm series. Signed-off-by: Daniele Venzano <venza@brownhat.org> -- Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/sis900.h')
-rw-r--r--drivers/net/sis900.h45
1 files changed, 45 insertions, 0 deletions
diff --git a/drivers/net/sis900.h b/drivers/net/sis900.h
index de3c06735d15..4233ea55670f 100644
--- a/drivers/net/sis900.h
+++ b/drivers/net/sis900.h
@@ -33,6 +33,7 @@ enum sis900_registers {
33 rxcfg=0x34, //Receive Configuration Register 33 rxcfg=0x34, //Receive Configuration Register
34 flctrl=0x38, //Flow Control Register 34 flctrl=0x38, //Flow Control Register
35 rxlen=0x3c, //Receive Packet Length Register 35 rxlen=0x3c, //Receive Packet Length Register
36 cfgpmcsr=0x44, //Configuration Power Management Control/Status Register
36 rfcr=0x48, //Receive Filter Control Register 37 rfcr=0x48, //Receive Filter Control Register
37 rfdr=0x4C, //Receive Filter Data Register 38 rfdr=0x4C, //Receive Filter Data Register
38 pmctrl=0xB0, //Power Management Control Register 39 pmctrl=0xB0, //Power Management Control Register
@@ -140,6 +141,50 @@ enum sis96x_eeprom_command {
140 EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100 141 EEREQ = 0x00000400, EEDONE = 0x00000200, EEGNT = 0x00000100
141}; 142};
142 143
144/* PCI Registers */
145enum sis900_pci_registers {
146 CFGPMC = 0x40,
147 CFGPMCSR = 0x44
148};
149
150/* Power management capabilities bits */
151enum sis900_cfgpmc_register_bits {
152 PMVER = 0x00070000,
153 DSI = 0x00100000,
154 PMESP = 0xf8000000
155};
156
157enum sis900_pmesp_bits {
158 PME_D0 = 0x1,
159 PME_D1 = 0x2,
160 PME_D2 = 0x4,
161 PME_D3H = 0x8,
162 PME_D3C = 0x10
163};
164
165/* Power management control/status bits */
166enum sis900_cfgpmcsr_register_bits {
167 PMESTS = 0x00004000,
168 PME_EN = 0x00000100, // Power management enable
169 PWR_STA = 0x00000003 // Current power state
170};
171
172/* Wake-on-LAN support. */
173enum sis900_power_management_control_register_bits {
174 LINKLOSS = 0x00000001,
175 LINKON = 0x00000002,
176 MAGICPKT = 0x00000400,
177 ALGORITHM = 0x00000800,
178 FRM1EN = 0x00100000,
179 FRM2EN = 0x00200000,
180 FRM3EN = 0x00400000,
181 FRM1ACS = 0x01000000,
182 FRM2ACS = 0x02000000,
183 FRM3ACS = 0x04000000,
184 WAKEALL = 0x40000000,
185 GATECLK = 0x80000000
186};
187
143/* Management Data I/O (mdio) frame */ 188/* Management Data I/O (mdio) frame */
144#define MIIread 0x6000 189#define MIIread 0x6000
145#define MIIwrite 0x5002 190#define MIIwrite 0x5002