net: sh_eth: modify the definitions of register

The previous code cannot handle the ETHER and GETHER both as same time
because the definitions of register was hardcoded.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 364 insertions, 259 deletions

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index efa64221eede..1510a7ca956a 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -2,7 +2,7 @@
  *  SuperH Ethernet device driver
  *
  *  Copyright (C) 2006-2008 Nobuhiro Iwamatsu
- *  Copyright (C) 2008-2009 Renesas Solutions Corp.
+ *  Copyright (C) 2008-2011 Renesas Solutions Corp.
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms and conditions of the GNU General Public License,
@@ -38,162 +38,345 @@
 #define ETHERSMALL              60
 #define PKT_BUF_SZ              1538
 
+enum {
+        /* E-DMAC registers */
+        EDSR = 0,
+        EDMR,
+        EDTRR,
+        EDRRR,
+        EESR,
+        EESIPR,
+        TDLAR,
+        TDFAR,
+        TDFXR,
+        TDFFR,
+        RDLAR,
+        RDFAR,
+        RDFXR,
+        RDFFR,
+        TRSCER,
+        RMFCR,
+        TFTR,
+        FDR,
+        RMCR,
+        EDOCR,
+        TFUCR,
+        RFOCR,
+        FCFTR,
+        RPADIR,
+        TRIMD,
+        RBWAR,
+        TBRAR,
+
+        /* Ether registers */
+        ECMR,
+        ECSR,
+        ECSIPR,
+        PIR,
+        PSR,
+        RDMLR,
+        PIPR,
+        RFLR,
+        IPGR,
+        APR,
+        MPR,
+        PFTCR,
+        PFRCR,
+        RFCR,
+        RFCF,
+        TPAUSER,
+        TPAUSECR,
+        BCFR,
+        BCFRR,
+        GECMR,
+        BCULR,
+        MAHR,
+        MALR,
+        TROCR,
+        CDCR,
+        LCCR,
+        CNDCR,
+        CEFCR,
+        FRECR,
+        TSFRCR,
+        TLFRCR,
+        CERCR,
+        CEECR,
+        MAFCR,
+        RTRATE,
+
+        /* TSU Absolute address */
+        ARSTR,
+        TSU_CTRST,
+        TSU_FWEN0,
+        TSU_FWEN1,
+        TSU_FCM,
+        TSU_BSYSL0,
+        TSU_BSYSL1,
+        TSU_PRISL0,
+        TSU_PRISL1,
+        TSU_FWSL0,
+        TSU_FWSL1,
+        TSU_FWSLC,
+        TSU_QTAG0,
+        TSU_QTAG1,
+        TSU_QTAGM0,
+        TSU_QTAGM1,
+        TSU_FWSR,
+        TSU_FWINMK,
+        TSU_ADQT0,
+        TSU_ADQT1,
+        TSU_VTAG0,
+        TSU_VTAG1,
+        TSU_ADSBSY,
+        TSU_TEN,
+        TSU_POST1,
+        TSU_POST2,
+        TSU_POST3,
+        TSU_POST4,
+        TSU_ADRH0,
+        TSU_ADRL0,
+        TSU_ADRH31,
+        TSU_ADRL31,
+
+        TXNLCR0,
+        TXALCR0,
+        RXNLCR0,
+        RXALCR0,
+        FWNLCR0,
+        FWALCR0,
+        TXNLCR1,
+        TXALCR1,
+        RXNLCR1,
+        RXALCR1,
+        FWNLCR1,
+        FWALCR1,
+
+        /* This value must be written at last. */
+        SH_ETH_MAX_REGISTER_OFFSET,
+};
+
+static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
+        [EDSR]  = 0x0000,
+        [EDMR]  = 0x0400,
+        [EDTRR] = 0x0408,
+        [EDRRR] = 0x0410,
+        [EESR]  = 0x0428,
+        [EESIPR]        = 0x0430,
+        [TDLAR] = 0x0010,
+        [TDFAR] = 0x0014,
+        [TDFXR] = 0x0018,
+        [TDFFR] = 0x001c,
+        [RDLAR] = 0x0030,
+        [RDFAR] = 0x0034,
+        [RDFXR] = 0x0038,
+        [RDFFR] = 0x003c,
+        [TRSCER]        = 0x0438,
+        [RMFCR] = 0x0440,
+        [TFTR]  = 0x0448,
+        [FDR]   = 0x0450,
+        [RMCR]  = 0x0458,
+        [RPADIR]        = 0x0460,
+        [FCFTR] = 0x0468,
+
+        [ECMR]  = 0x0500,
+        [ECSR]  = 0x0510,
+        [ECSIPR]        = 0x0518,
+        [PIR]   = 0x0520,
+        [PSR]   = 0x0528,
+        [PIPR]  = 0x052c,
+        [RFLR]  = 0x0508,
+        [APR]   = 0x0554,
+        [MPR]   = 0x0558,
+        [PFTCR] = 0x055c,
+        [PFRCR] = 0x0560,
+        [TPAUSER]       = 0x0564,
+        [GECMR] = 0x05b0,
+        [BCULR] = 0x05b4,
+        [MAHR]  = 0x05c0,
+        [MALR]  = 0x05c8,
+        [TROCR] = 0x0700,
+        [CDCR]  = 0x0708,
+        [LCCR]  = 0x0710,
+        [CEFCR] = 0x0740,
+        [FRECR] = 0x0748,
+        [TSFRCR]        = 0x0750,
+        [TLFRCR]        = 0x0758,
+        [RFCR]  = 0x0760,
+        [CERCR] = 0x0768,
+        [CEECR] = 0x0770,
+        [MAFCR] = 0x0778,
+
+        [TSU_CTRST]     = 0x0004,
+        [TSU_FWEN0]     = 0x0010,
+        [TSU_FWEN1]     = 0x0014,
+        [TSU_FCM]       = 0x0018,
+        [TSU_BSYSL0]    = 0x0020,
+        [TSU_BSYSL1]    = 0x0024,
+        [TSU_PRISL0]    = 0x0028,
+        [TSU_PRISL1]    = 0x002c,
+        [TSU_FWSL0]     = 0x0030,
+        [TSU_FWSL1]     = 0x0034,
+        [TSU_FWSLC]     = 0x0038,
+        [TSU_QTAG0]     = 0x0040,
+        [TSU_QTAG1]     = 0x0044,
+        [TSU_FWSR]      = 0x0050,
+        [TSU_FWINMK]    = 0x0054,
+        [TSU_ADQT0]     = 0x0048,
+        [TSU_ADQT1]     = 0x004c,
+        [TSU_VTAG0]     = 0x0058,
+        [TSU_VTAG1]     = 0x005c,
+        [TSU_ADSBSY]    = 0x0060,
+        [TSU_TEN]       = 0x0064,
+        [TSU_POST1]     = 0x0070,
+        [TSU_POST2]     = 0x0074,
+        [TSU_POST3]     = 0x0078,
+        [TSU_POST4]     = 0x007c,
+        [TSU_ADRH0]     = 0x0100,
+        [TSU_ADRL0]     = 0x0104,
+        [TSU_ADRH31]    = 0x01f8,
+        [TSU_ADRL31]    = 0x01fc,
+
+        [TXNLCR0]       = 0x0080,
+        [TXALCR0]       = 0x0084,
+        [RXNLCR0]       = 0x0088,
+        [RXALCR0]       = 0x008c,
+        [FWNLCR0]       = 0x0090,
+        [FWALCR0]       = 0x0094,
+        [TXNLCR1]       = 0x00a0,
+        [TXALCR1]       = 0x00a0,
+        [RXNLCR1]       = 0x00a8,
+        [RXALCR1]       = 0x00ac,
+        [FWNLCR1]       = 0x00b0,
+        [FWALCR1]       = 0x00b4,
+};
+
+static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
+        [ECMR]  = 0x0100,
+        [RFLR]  = 0x0108,
+        [ECSR]  = 0x0110,
+        [ECSIPR]        = 0x0118,
+        [PIR]   = 0x0120,
+        [PSR]   = 0x0128,
+        [RDMLR] = 0x0140,
+        [IPGR]  = 0x0150,
+        [APR]   = 0x0154,
+        [MPR]   = 0x0158,
+        [TPAUSER]       = 0x0164,
+        [RFCF]  = 0x0160,
+        [TPAUSECR]      = 0x0168,
+        [BCFRR] = 0x016c,
+        [MAHR]  = 0x01c0,
+        [MALR]  = 0x01c8,
+        [TROCR] = 0x01d0,
+        [CDCR]  = 0x01d4,
+        [LCCR]  = 0x01d8,
+        [CNDCR] = 0x01dc,
+        [CEFCR] = 0x01e4,
+        [FRECR] = 0x01e8,
+        [TSFRCR]        = 0x01ec,
+        [TLFRCR]        = 0x01f0,
+        [RFCR]  = 0x01f4,
+        [MAFCR] = 0x01f8,
+        [RTRATE]        = 0x01fc,
+
+        [EDMR]  = 0x0000,
+        [EDTRR] = 0x0008,
+        [EDRRR] = 0x0010,
+        [TDLAR] = 0x0018,
+        [RDLAR] = 0x0020,
+        [EESR]  = 0x0028,
+        [EESIPR]        = 0x0030,
+        [TRSCER]        = 0x0038,
+        [RMFCR] = 0x0040,
+        [TFTR]  = 0x0048,
+        [FDR]   = 0x0050,
+        [RMCR]  = 0x0058,
+        [TFUCR] = 0x0064,
+        [RFOCR] = 0x0068,
+        [FCFTR] = 0x0070,
+        [RPADIR]        = 0x0078,
+        [TRIMD] = 0x007c,
+        [RBWAR] = 0x00c8,
+        [RDFAR] = 0x00cc,
+        [TBRAR] = 0x00d4,
+        [TDFAR] = 0x00d8,
+};
+
+static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
+        [ECMR]  = 0x0160,
+        [ECSR]  = 0x0164,
+        [ECSIPR]        = 0x0168,
+        [PIR]   = 0x016c,
+        [MAHR]  = 0x0170,
+        [MALR]  = 0x0174,
+        [RFLR]  = 0x0178,
+        [PSR]   = 0x017c,
+        [TROCR] = 0x0180,
+        [CDCR]  = 0x0184,
+        [LCCR]  = 0x0188,
+        [CNDCR] = 0x018c,
+        [CEFCR] = 0x0194,
+        [FRECR] = 0x0198,
+        [TSFRCR]        = 0x019c,
+        [TLFRCR]        = 0x01a0,
+        [RFCR]  = 0x01a4,
+        [MAFCR] = 0x01a8,
+        [IPGR]  = 0x01b4,
+        [APR]   = 0x01b8,
+        [MPR]   = 0x01bc,
+        [TPAUSER]       = 0x01c4,
+        [BCFR]  = 0x01cc,
+
+        [TSU_CTRST]     = 0x0004,
+        [TSU_FWEN0]     = 0x0010,
+        [TSU_FWEN1]     = 0x0014,
+        [TSU_FCM]       = 0x0018,
+        [TSU_BSYSL0]    = 0x0020,
+        [TSU_BSYSL1]    = 0x0024,
+        [TSU_PRISL0]    = 0x0028,
+        [TSU_PRISL1]    = 0x002c,
+        [TSU_FWSL0]     = 0x0030,
+        [TSU_FWSL1]     = 0x0034,
+        [TSU_FWSLC]     = 0x0038,
+        [TSU_QTAGM0]    = 0x0040,
+        [TSU_QTAGM1]    = 0x0044,
+        [TSU_ADQT0]     = 0x0048,
+        [TSU_ADQT1]     = 0x004c,
+        [TSU_FWSR]      = 0x0050,
+        [TSU_FWINMK]    = 0x0054,
+        [TSU_ADSBSY]    = 0x0060,
+        [TSU_TEN]       = 0x0064,
+        [TSU_POST1]     = 0x0070,
+        [TSU_POST2]     = 0x0074,
+        [TSU_POST3]     = 0x0078,
+        [TSU_POST4]     = 0x007c,
+
+        [TXNLCR0]       = 0x0080,
+        [TXALCR0]       = 0x0084,
+        [RXNLCR0]       = 0x0088,
+        [RXALCR0]       = 0x008c,
+        [FWNLCR0]       = 0x0090,
+        [FWALCR0]       = 0x0094,
+        [TXNLCR1]       = 0x00a0,
+        [TXALCR1]       = 0x00a0,
+        [RXNLCR1]       = 0x00a8,
+        [RXALCR1]       = 0x00ac,
+        [FWNLCR1]       = 0x00b0,
+        [FWALCR1]       = 0x00b4,
+
+        [TSU_ADRH0]     = 0x0100,
+        [TSU_ADRL0]     = 0x0104,
+        [TSU_ADRL31]    = 0x01fc,
+
+};
+
 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
 /* This CPU register maps is very difference by other SH4 CPU */
-
 /* Chip Base Address */
 # define SH_TSU_ADDR    0xFEE01800
 # define ARSTR          SH_TSU_ADDR
-
-/* Chip Registers */
-/* E-DMAC */
-# define EDSR    0x000
-# define EDMR    0x400
-# define EDTRR   0x408
-# define EDRRR   0x410
-# define EESR    0x428
-# define EESIPR  0x430
-# define TDLAR   0x010
-# define TDFAR   0x014
-# define TDFXR   0x018
-# define TDFFR   0x01C
-# define RDLAR   0x030
-# define RDFAR   0x034
-# define RDFXR   0x038
-# define RDFFR   0x03C
-# define TRSCER  0x438
-# define RMFCR   0x440
-# define TFTR    0x448
-# define FDR     0x450
-# define RMCR    0x458
-# define RPADIR  0x460
-# define FCFTR   0x468
-
-/* Ether Register */
-# define ECMR    0x500
-# define ECSR    0x510
-# define ECSIPR  0x518
-# define PIR     0x520
-# define PSR     0x528
-# define PIPR    0x52C
-# define RFLR    0x508
-# define APR     0x554
-# define MPR     0x558
-# define PFTCR   0x55C
-# define PFRCR   0x560
-# define TPAUSER 0x564
-# define GECMR   0x5B0
-# define BCULR   0x5B4
-# define MAHR    0x5C0
-# define MALR    0x5C8
-# define TROCR   0x700
-# define CDCR    0x708
-# define LCCR    0x710
-# define CEFCR   0x740
-# define FRECR   0x748
-# define TSFRCR  0x750
-# define TLFRCR  0x758
-# define RFCR    0x760
-# define CERCR   0x768
-# define CEECR   0x770
-# define MAFCR   0x778
-
-/* TSU Absolute Address */
-# define TSU_CTRST       0x004
-# define TSU_FWEN0       0x010
-# define TSU_FWEN1       0x014
-# define TSU_FCM         0x18
-# define TSU_BSYSL0      0x20
-# define TSU_BSYSL1      0x24
-# define TSU_PRISL0      0x28
-# define TSU_PRISL1      0x2C
-# define TSU_FWSL0       0x30
-# define TSU_FWSL1       0x34
-# define TSU_FWSLC       0x38
-# define TSU_QTAG0       0x40
-# define TSU_QTAG1       0x44
-# define TSU_FWSR        0x50
-# define TSU_FWINMK      0x54
-# define TSU_ADQT0       0x48
-# define TSU_ADQT1       0x4C
-# define TSU_VTAG0       0x58
-# define TSU_VTAG1       0x5C
-# define TSU_ADSBSY      0x60
-# define TSU_TEN         0x64
-# define TSU_POST1       0x70
-# define TSU_POST2       0x74
-# define TSU_POST3       0x78
-# define TSU_POST4       0x7C
-# define TSU_ADRH0       0x100
-# define TSU_ADRL0       0x104
-# define TSU_ADRH31      0x1F8
-# define TSU_ADRL31      0x1FC
-
-# define TXNLCR0         0x80
-# define TXALCR0         0x84
-# define RXNLCR0         0x88
-# define RXALCR0         0x8C
-# define FWNLCR0         0x90
-# define FWALCR0         0x94
-# define TXNLCR1         0xA0
-# define TXALCR1         0xA4
-# define RXNLCR1         0xA8
-# define RXALCR1         0xAC
-# define FWNLCR1         0xB0
-# define FWALCR1         0x40
-
 #elif defined(CONFIG_CPU_SH4)   /* #if defined(CONFIG_CPU_SUBTYPE_SH7763) */
-/* EtherC */
-#define ECMR            0x100
-#define RFLR            0x108
-#define ECSR            0x110
-#define ECSIPR          0x118
-#define PIR             0x120
-#define PSR             0x128
-#define RDMLR           0x140
-#define IPGR            0x150
-#define APR             0x154
-#define MPR             0x158
-#define TPAUSER         0x164
-#define RFCF            0x160
-#define TPAUSECR        0x168
-#define BCFRR           0x16c
-#define MAHR            0x1c0
-#define MALR            0x1c8
-#define TROCR           0x1d0
-#define CDCR            0x1d4
-#define LCCR            0x1d8
-#define CNDCR           0x1dc
-#define CEFCR           0x1e4
-#define FRECR           0x1e8
-#define TSFRCR          0x1ec
-#define TLFRCR          0x1f0
-#define RFCR            0x1f4
-#define MAFCR           0x1f8
-#define RTRATE          0x1fc
-
-/* E-DMAC */
-#define EDMR            0x000
-#define EDTRR           0x008
-#define EDRRR           0x010
-#define TDLAR           0x018
-#define RDLAR           0x020
-#define EESR            0x028
-#define EESIPR          0x030
-#define TRSCER          0x038
-#define RMFCR           0x040
-#define TFTR            0x048
-#define FDR             0x050
-#define RMCR            0x058
-#define TFUCR           0x064
-#define RFOCR           0x068
-#define FCFTR           0x070
-#define RPADIR          0x078
-#define TRIMD           0x07c
-#define RBWAR           0x0c8
-#define RDFAR           0x0cc
-#define TBRAR           0x0d4
-#define TDFAR           0x0d8
 #else /* #elif defined(CONFIG_CPU_SH4) */
 /* This section is SH3 or SH2 */
 #ifndef CONFIG_CPU_SUBTYPE_SH7619
@@ -201,116 +384,8 @@
 # define SH_TSU_ADDR  0xA7000804
 # define ARSTR            0xA7000800
 #endif
-/* Chip Registers */
-/* E-DMAC */
-# define EDMR   0x0000
-# define EDTRR  0x0004
-# define EDRRR  0x0008
-# define TDLAR  0x000C
-# define RDLAR  0x0010
-# define EESR   0x0014
-# define EESIPR 0x0018
-# define TRSCER 0x001C
-# define RMFCR  0x0020
-# define TFTR   0x0024
-# define FDR    0x0028
-# define RMCR   0x002C
-# define EDOCR  0x0030
-# define FCFTR  0x0034
-# define RPADIR 0x0038
-# define TRIMD  0x003C
-# define RBWAR  0x0040
-# define RDFAR  0x0044
-# define TBRAR  0x004C
-# define TDFAR  0x0050
-
-/* Ether Register */
-# define ECMR   0x0160
-# define ECSR   0x0164
-# define ECSIPR 0x0168
-# define PIR    0x016C
-# define MAHR   0x0170
-# define MALR   0x0174
-# define RFLR   0x0178
-# define PSR    0x017C
-# define TROCR  0x0180
-# define CDCR   0x0184
-# define LCCR   0x0188
-# define CNDCR  0x018C
-# define CEFCR  0x0194
-# define FRECR  0x0198
-# define TSFRCR 0x019C
-# define TLFRCR 0x01A0
-# define RFCR   0x01A4
-# define MAFCR  0x01A8
-# define IPGR   0x01B4
-# if defined(CONFIG_CPU_SUBTYPE_SH7710)
-# define APR    0x01B8
-# define MPR    0x01BC
-# define TPAUSER 0x1C4
-# define BCFR   0x1CC
-# endif /* CONFIG_CPU_SH7710 */
-
-/* TSU */
-# define TSU_CTRST      0x004
-# define TSU_FWEN0      0x010
-# define TSU_FWEN1      0x014
-# define TSU_FCM        0x018
-# define TSU_BSYSL0     0x020
-# define TSU_BSYSL1     0x024
-# define TSU_PRISL0     0x028
-# define TSU_PRISL1     0x02C
-# define TSU_FWSL0      0x030
-# define TSU_FWSL1      0x034
-# define TSU_FWSLC      0x038
-# define TSU_QTAGM0     0x040
-# define TSU_QTAGM1     0x044
-# define TSU_ADQT0      0x048
-# define TSU_ADQT1      0x04C
-# define TSU_FWSR       0x050
-# define TSU_FWINMK     0x054
-# define TSU_ADSBSY     0x060
-# define TSU_TEN        0x064
-# define TSU_POST1      0x070
-# define TSU_POST2      0x074
-# define TSU_POST3      0x078
-# define TSU_POST4      0x07C
-# define TXNLCR0        0x080
-# define TXALCR0        0x084
-# define RXNLCR0        0x088
-# define RXALCR0        0x08C
-# define FWNLCR0        0x090
-# define FWALCR0        0x094
-# define TXNLCR1        0x0A0
-# define TXALCR1        0x0A4
-# define RXNLCR1        0x0A8
-# define RXALCR1        0x0AC
-# define FWNLCR1        0x0B0
-# define FWALCR1        0x0B4
-
-#define TSU_ADRH0       0x0100
-#define TSU_ADRL0       0x0104
-#define TSU_ADRL31      0x01FC
-
 #endif /* CONFIG_CPU_SUBTYPE_SH7763 */
 
-/* There are avoid compile error... */
-#if !defined(BCULR)
-#define BCULR   0x0fc
-#endif
-#if !defined(TRIMD)
-#define TRIMD   0x0fc
-#endif
-#if !defined(APR)
-#define APR     0x0fc
-#endif
-#if !defined(MPR)
-#define MPR     0x0fc
-#endif
-#if !defined(TPAUSER)
-#define TPAUSER 0x0fc
-#endif
-
 /* Driver's parameters */
 #if defined(CONFIG_CPU_SH4)
 #define SH4_SKB_RX_ALIGN        32
@@ -704,6 +779,8 @@ struct sh_eth_cpu_data {
 struct sh_eth_private {
         struct platform_device *pdev;
         struct sh_eth_cpu_data *cd;
+        const u16 *reg_offset;
+        void __iomem *tsu_addr;
         dma_addr_t rx_desc_dma;
         dma_addr_t tx_desc_dma;
         struct sh_eth_rxdesc *rx_ring;
@@ -746,4 +823,32 @@ static inline void sh_eth_soft_swap(char *src, int len)
 #endif
 }
 
+static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
+                                int enum_index)
+{
+        struct sh_eth_private *mdp = netdev_priv(ndev);
+
+        writel(data, ndev->base_addr + mdp->reg_offset[enum_index]);
+}
+
+static inline unsigned long sh_eth_read(struct net_device *ndev,
+                                        int enum_index)
+{
+        struct sh_eth_private *mdp = netdev_priv(ndev);
+
+        return readl(ndev->base_addr + mdp->reg_offset[enum_index]);
+}
+
+static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
+                                unsigned long data, int enum_index)
+{
+        writel(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
+}
+
+static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
+                                        int enum_index)
+{
+        return readl(mdp->tsu_addr + mdp->reg_offset[enum_index]);
+}
+
 #endif  /* #ifndef __SH_ETH_H__ */