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authorYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>2009-05-24 19:54:21 -0400
committerDavid S. Miller <davem@davemloft.net>2009-05-26 01:49:55 -0400
commit380af9e390ec81e74a2fd7fad948a8b12eeec7da (patch)
tree28123090740fe01bfcae1787993b40c9e588756a /drivers/net/sh_eth.c
parent862df49750e7ca9369c04d8d8105b3cc5d976e0d (diff)
net: sh_eth: CPU dependency code collect to "struct sh_eth_cpu_data"
This improves readability by collecting CPU dependency code. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sh_eth.c')
-rw-r--r--drivers/net/sh_eth.c411
1 files changed, 267 insertions, 144 deletions
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 728c4196830a..19571f759610 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -2,7 +2,7 @@
2 * SuperH Ethernet device driver 2 * SuperH Ethernet device driver
3 * 3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify it 7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License, 8 * under the terms and conditions of the GNU General Public License,
@@ -33,6 +33,176 @@
33 33
34#include "sh_eth.h" 34#include "sh_eth.h"
35 35
36/* There is CPU dependent code */
37#if defined(CONFIG_CPU_SUBTYPE_SH7763)
38#define SH_ETH_HAS_TSU 1
39static void sh_eth_chip_reset(struct net_device *ndev)
40{
41 /* reset device */
42 ctrl_outl(ARSTR_ARSTR, ARSTR);
43 mdelay(1);
44}
45
46static void sh_eth_reset(struct net_device *ndev)
47{
48 u32 ioaddr = ndev->base_addr;
49 int cnt = 100;
50
51 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
52 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
53 while (cnt > 0) {
54 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
55 break;
56 mdelay(1);
57 cnt--;
58 }
59 if (cnt < 0)
60 printk(KERN_ERR "Device reset fail\n");
61
62 /* Table Init */
63 ctrl_outl(0x0, ioaddr + TDLAR);
64 ctrl_outl(0x0, ioaddr + TDFAR);
65 ctrl_outl(0x0, ioaddr + TDFXR);
66 ctrl_outl(0x0, ioaddr + TDFFR);
67 ctrl_outl(0x0, ioaddr + RDLAR);
68 ctrl_outl(0x0, ioaddr + RDFAR);
69 ctrl_outl(0x0, ioaddr + RDFXR);
70 ctrl_outl(0x0, ioaddr + RDFFR);
71}
72
73static void sh_eth_set_duplex(struct net_device *ndev)
74{
75 struct sh_eth_private *mdp = netdev_priv(ndev);
76 u32 ioaddr = ndev->base_addr;
77
78 if (mdp->duplex) /* Full */
79 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
80 else /* Half */
81 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
82}
83
84static void sh_eth_set_rate(struct net_device *ndev)
85{
86 struct sh_eth_private *mdp = netdev_priv(ndev);
87 u32 ioaddr = ndev->base_addr;
88
89 switch (mdp->speed) {
90 case 10: /* 10BASE */
91 ctrl_outl(GECMR_10, ioaddr + GECMR);
92 break;
93 case 100:/* 100BASE */
94 ctrl_outl(GECMR_100, ioaddr + GECMR);
95 break;
96 case 1000: /* 1000BASE */
97 ctrl_outl(GECMR_1000, ioaddr + GECMR);
98 break;
99 default:
100 break;
101 }
102}
103
104/* sh7763 */
105static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
106 .chip_reset = sh_eth_chip_reset,
107 .set_duplex = sh_eth_set_duplex,
108 .set_rate = sh_eth_set_rate,
109
110 .ecsr_value = ECSR_ICD | ECSR_MPD,
111 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
112 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
113
114 .tx_check = EESR_TC1 | EESR_FTC,
115 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
116 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
117 EESR_ECI,
118 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
119 EESR_TFE,
120
121 .apr = 1,
122 .mpr = 1,
123 .tpauser = 1,
124 .bculr = 1,
125 .hw_swap = 1,
126 .rpadir = 1,
127 .no_trimd = 1,
128 .no_ade = 1,
129};
130
131#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
132#define SH_ETH_RESET_DEFAULT 1
133static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
134 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
135
136 .apr = 1,
137 .mpr = 1,
138 .tpauser = 1,
139 .hw_swap = 1,
140};
141#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
142#define SH_ETH_RESET_DEFAULT 1
143#define SH_ETH_HAS_TSU 1
144static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
145 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
146};
147#endif
148
149static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
150{
151 if (!cd->ecsr_value)
152 cd->ecsr_value = DEFAULT_ECSR_INIT;
153
154 if (!cd->ecsipr_value)
155 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
156
157 if (!cd->fcftr_value)
158 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
159 DEFAULT_FIFO_F_D_RFD;
160
161 if (!cd->fdr_value)
162 cd->fdr_value = DEFAULT_FDR_INIT;
163
164 if (!cd->rmcr_value)
165 cd->rmcr_value = DEFAULT_RMCR_VALUE;
166
167 if (!cd->tx_check)
168 cd->tx_check = DEFAULT_TX_CHECK;
169
170 if (!cd->eesr_err_check)
171 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
172
173 if (!cd->tx_error_check)
174 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
175}
176
177#if defined(SH_ETH_RESET_DEFAULT)
178/* Chip Reset */
179static void sh_eth_reset(struct net_device *ndev)
180{
181 u32 ioaddr = ndev->base_addr;
182
183 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
184 mdelay(3);
185 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
186}
187#endif
188
189#if defined(CONFIG_CPU_SH4)
190static void sh_eth_set_receive_align(struct sk_buff *skb)
191{
192 int reserve;
193
194 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
195 if (reserve)
196 skb_reserve(skb, reserve);
197}
198#else
199static void sh_eth_set_receive_align(struct sk_buff *skb)
200{
201 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
202}
203#endif
204
205
36/* CPU <-> EDMAC endian convert */ 206/* CPU <-> EDMAC endian convert */
37static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 207static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
38{ 208{
@@ -165,41 +335,6 @@ static struct mdiobb_ops bb_ops = {
165 .get_mdio_data = sh_get_mdio, 335 .get_mdio_data = sh_get_mdio,
166}; 336};
167 337
168/* Chip Reset */
169static void sh_eth_reset(struct net_device *ndev)
170{
171 u32 ioaddr = ndev->base_addr;
172
173#if defined(CONFIG_CPU_SUBTYPE_SH7763)
174 int cnt = 100;
175
176 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
177 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
178 while (cnt > 0) {
179 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
180 break;
181 mdelay(1);
182 cnt--;
183 }
184 if (cnt < 0)
185 printk(KERN_ERR "Device reset fail\n");
186
187 /* Table Init */
188 ctrl_outl(0x0, ioaddr + TDLAR);
189 ctrl_outl(0x0, ioaddr + TDFAR);
190 ctrl_outl(0x0, ioaddr + TDFXR);
191 ctrl_outl(0x0, ioaddr + TDFFR);
192 ctrl_outl(0x0, ioaddr + RDLAR);
193 ctrl_outl(0x0, ioaddr + RDFAR);
194 ctrl_outl(0x0, ioaddr + RDFXR);
195 ctrl_outl(0x0, ioaddr + RDFFR);
196#else
197 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
198 mdelay(3);
199 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
200#endif
201}
202
203/* free skb and descriptor buffer */ 338/* free skb and descriptor buffer */
204static void sh_eth_ring_free(struct net_device *ndev) 339static void sh_eth_ring_free(struct net_device *ndev)
205{ 340{
@@ -228,7 +363,7 @@ static void sh_eth_ring_free(struct net_device *ndev)
228/* format skb and descriptor buffer */ 363/* format skb and descriptor buffer */
229static void sh_eth_ring_format(struct net_device *ndev) 364static void sh_eth_ring_format(struct net_device *ndev)
230{ 365{
231 u32 ioaddr = ndev->base_addr, reserve = 0; 366 u32 ioaddr = ndev->base_addr;
232 struct sh_eth_private *mdp = netdev_priv(ndev); 367 struct sh_eth_private *mdp = netdev_priv(ndev);
233 int i; 368 int i;
234 struct sk_buff *skb; 369 struct sk_buff *skb;
@@ -253,14 +388,8 @@ static void sh_eth_ring_format(struct net_device *ndev)
253 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz, 388 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
254 DMA_FROM_DEVICE); 389 DMA_FROM_DEVICE);
255 skb->dev = ndev; /* Mark as being used by this device. */ 390 skb->dev = ndev; /* Mark as being used by this device. */
256#if defined(CONFIG_CPU_SUBTYPE_SH7763) 391 sh_eth_set_receive_align(skb);
257 reserve = SH7763_SKB_ALIGN 392
258 - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1));
259 if (reserve)
260 skb_reserve(skb, reserve);
261#else
262 skb_reserve(skb, RX_OFFSET);
263#endif
264 /* RX descriptor */ 393 /* RX descriptor */
265 rxdesc = &mdp->rx_ring[i]; 394 rxdesc = &mdp->rx_ring[i];
266 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 395 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
@@ -321,7 +450,7 @@ static int sh_eth_ring_init(struct net_device *ndev)
321 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE, 450 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
322 GFP_KERNEL); 451 GFP_KERNEL);
323 if (!mdp->rx_skbuff) { 452 if (!mdp->rx_skbuff) {
324 printk(KERN_ERR "%s: Cannot allocate Rx skb\n", ndev->name); 453 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
325 ret = -ENOMEM; 454 ret = -ENOMEM;
326 return ret; 455 return ret;
327 } 456 }
@@ -329,7 +458,7 @@ static int sh_eth_ring_init(struct net_device *ndev)
329 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE, 458 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
330 GFP_KERNEL); 459 GFP_KERNEL);
331 if (!mdp->tx_skbuff) { 460 if (!mdp->tx_skbuff) {
332 printk(KERN_ERR "%s: Cannot allocate Tx skb\n", ndev->name); 461 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
333 ret = -ENOMEM; 462 ret = -ENOMEM;
334 goto skb_ring_free; 463 goto skb_ring_free;
335 } 464 }
@@ -340,8 +469,8 @@ static int sh_eth_ring_init(struct net_device *ndev)
340 GFP_KERNEL); 469 GFP_KERNEL);
341 470
342 if (!mdp->rx_ring) { 471 if (!mdp->rx_ring) {
343 printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n", 472 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
344 ndev->name, rx_ringsize); 473 rx_ringsize);
345 ret = -ENOMEM; 474 ret = -ENOMEM;
346 goto desc_ring_free; 475 goto desc_ring_free;
347 } 476 }
@@ -353,8 +482,8 @@ static int sh_eth_ring_init(struct net_device *ndev)
353 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 482 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
354 GFP_KERNEL); 483 GFP_KERNEL);
355 if (!mdp->tx_ring) { 484 if (!mdp->tx_ring) {
356 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n", 485 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
357 ndev->name, tx_ringsize); 486 tx_ringsize);
358 ret = -ENOMEM; 487 ret = -ENOMEM;
359 goto desc_ring_free; 488 goto desc_ring_free;
360 } 489 }
@@ -384,44 +513,43 @@ static int sh_eth_dev_init(struct net_device *ndev)
384 513
385 /* Descriptor format */ 514 /* Descriptor format */
386 sh_eth_ring_format(ndev); 515 sh_eth_ring_format(ndev);
387 ctrl_outl(RPADIR_INIT, ioaddr + RPADIR); 516 if (mdp->cd->rpadir)
517 ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
388 518
389 /* all sh_eth int mask */ 519 /* all sh_eth int mask */
390 ctrl_outl(0, ioaddr + EESIPR); 520 ctrl_outl(0, ioaddr + EESIPR);
391 521
392#if defined(CONFIG_CPU_SUBTYPE_SH7763) 522#if defined(__LITTLE_ENDIAN__)
393 ctrl_outl(EDMR_EL, ioaddr + EDMR); 523 if (mdp->cd->hw_swap)
394#else 524 ctrl_outl(EDMR_EL, ioaddr + EDMR);
395 ctrl_outl(0, ioaddr + EDMR); /* Endian change */ 525 else
396#endif 526#endif
527 ctrl_outl(0, ioaddr + EDMR);
397 528
398 /* FIFO size set */ 529 /* FIFO size set */
399 ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR); 530 ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
400 ctrl_outl(0, ioaddr + TFTR); 531 ctrl_outl(0, ioaddr + TFTR);
401 532
402 /* Frame recv control */ 533 /* Frame recv control */
403 ctrl_outl(0, ioaddr + RMCR); 534 ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
404 535
405 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; 536 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
406 tx_int_var = mdp->tx_int_var = DESC_I_TINT2; 537 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
407 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER); 538 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
408 539
409#if defined(CONFIG_CPU_SUBTYPE_SH7763) 540 if (mdp->cd->bculr)
410 /* Burst sycle set */ 541 ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
411 ctrl_outl(0x800, ioaddr + BCULR);
412#endif
413 542
414 ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR); 543 ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
415 544
416#if !defined(CONFIG_CPU_SUBTYPE_SH7763) 545 if (!mdp->cd->no_trimd)
417 ctrl_outl(0, ioaddr + TRIMD); 546 ctrl_outl(0, ioaddr + TRIMD);
418#endif
419 547
420 /* Recv frame limit set register */ 548 /* Recv frame limit set register */
421 ctrl_outl(RFLR_VALUE, ioaddr + RFLR); 549 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
422 550
423 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR); 551 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
424 ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR); 552 ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
425 553
426 /* PAUSE Prohibition */ 554 /* PAUSE Prohibition */
427 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) | 555 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
@@ -429,24 +557,25 @@ static int sh_eth_dev_init(struct net_device *ndev)
429 557
430 ctrl_outl(val, ioaddr + ECMR); 558 ctrl_outl(val, ioaddr + ECMR);
431 559
560 if (mdp->cd->set_rate)
561 mdp->cd->set_rate(ndev);
562
432 /* E-MAC Status Register clear */ 563 /* E-MAC Status Register clear */
433 ctrl_outl(ECSR_INIT, ioaddr + ECSR); 564 ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
434 565
435 /* E-MAC Interrupt Enable register */ 566 /* E-MAC Interrupt Enable register */
436 ctrl_outl(ECSIPR_INIT, ioaddr + ECSIPR); 567 ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
437 568
438 /* Set MAC address */ 569 /* Set MAC address */
439 update_mac_address(ndev); 570 update_mac_address(ndev);
440 571
441 /* mask reset */ 572 /* mask reset */
442#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7763) 573 if (mdp->cd->apr)
443 ctrl_outl(APR_AP, ioaddr + APR); 574 ctrl_outl(APR_AP, ioaddr + APR);
444 ctrl_outl(MPR_MP, ioaddr + MPR); 575 if (mdp->cd->mpr)
445 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER); 576 ctrl_outl(MPR_MP, ioaddr + MPR);
446#endif 577 if (mdp->cd->tpauser)
447#if defined(CONFIG_CPU_SUBTYPE_SH7710) 578 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
448 ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR);
449#endif
450 579
451 /* Setting the Rx mode will start the Rx process. */ 580 /* Setting the Rx mode will start the Rx process. */
452 ctrl_outl(EDRRR_R, ioaddr + EDRRR); 581 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
@@ -495,7 +624,7 @@ static int sh_eth_rx(struct net_device *ndev)
495 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx; 624 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
496 struct sk_buff *skb; 625 struct sk_buff *skb;
497 u16 pkt_len = 0; 626 u16 pkt_len = 0;
498 u32 desc_status, reserve = 0; 627 u32 desc_status;
499 628
500 rxdesc = &mdp->rx_ring[entry]; 629 rxdesc = &mdp->rx_ring[entry];
501 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 630 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
@@ -524,8 +653,10 @@ static int sh_eth_rx(struct net_device *ndev)
524 if (desc_status & RD_RFS10) 653 if (desc_status & RD_RFS10)
525 mdp->stats.rx_over_errors++; 654 mdp->stats.rx_over_errors++;
526 } else { 655 } else {
527 swaps(phys_to_virt(ALIGN(rxdesc->addr, 4)), 656 if (!mdp->cd->hw_swap)
528 pkt_len + 2); 657 sh_eth_soft_swap(
658 phys_to_virt(ALIGN(rxdesc->addr, 4)),
659 pkt_len + 2);
529 skb = mdp->rx_skbuff[entry]; 660 skb = mdp->rx_skbuff[entry];
530 mdp->rx_skbuff[entry] = NULL; 661 mdp->rx_skbuff[entry] = NULL;
531 skb_put(skb, pkt_len); 662 skb_put(skb, pkt_len);
@@ -554,14 +685,8 @@ static int sh_eth_rx(struct net_device *ndev)
554 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz, 685 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
555 DMA_FROM_DEVICE); 686 DMA_FROM_DEVICE);
556 skb->dev = ndev; 687 skb->dev = ndev;
557#if defined(CONFIG_CPU_SUBTYPE_SH7763) 688 sh_eth_set_receive_align(skb);
558 reserve = SH7763_SKB_ALIGN 689
559 - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1));
560 if (reserve)
561 skb_reserve(skb, reserve);
562#else
563 skb_reserve(skb, RX_OFFSET);
564#endif
565 skb->ip_summed = CHECKSUM_NONE; 690 skb->ip_summed = CHECKSUM_NONE;
566 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 691 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
567 } 692 }
@@ -587,6 +712,8 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
587 struct sh_eth_private *mdp = netdev_priv(ndev); 712 struct sh_eth_private *mdp = netdev_priv(ndev);
588 u32 ioaddr = ndev->base_addr; 713 u32 ioaddr = ndev->base_addr;
589 u32 felic_stat; 714 u32 felic_stat;
715 u32 link_stat;
716 u32 mask;
590 717
591 if (intr_status & EESR_ECI) { 718 if (intr_status & EESR_ECI) {
592 felic_stat = ctrl_inl(ioaddr + ECSR); 719 felic_stat = ctrl_inl(ioaddr + ECSR);
@@ -595,7 +722,14 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
595 mdp->stats.tx_carrier_errors++; 722 mdp->stats.tx_carrier_errors++;
596 if (felic_stat & ECSR_LCHNG) { 723 if (felic_stat & ECSR_LCHNG) {
597 /* Link Changed */ 724 /* Link Changed */
598 u32 link_stat = (ctrl_inl(ioaddr + PSR)); 725 if (mdp->cd->no_psr) {
726 if (mdp->link == PHY_DOWN)
727 link_stat = 0;
728 else
729 link_stat = PHY_ST_LINK;
730 } else {
731 link_stat = (ctrl_inl(ioaddr + PSR));
732 }
599 if (!(link_stat & PHY_ST_LINK)) { 733 if (!(link_stat & PHY_ST_LINK)) {
600 /* Link Down : disable tx and rx */ 734 /* Link Down : disable tx and rx */
601 ctrl_outl(ctrl_inl(ioaddr + ECMR) & 735 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
@@ -627,17 +761,15 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
627 if (intr_status & EESR_RFRMER) { 761 if (intr_status & EESR_RFRMER) {
628 /* Receive Frame Overflow int */ 762 /* Receive Frame Overflow int */
629 mdp->stats.rx_frame_errors++; 763 mdp->stats.rx_frame_errors++;
630 printk(KERN_ERR "Receive Frame Overflow\n"); 764 dev_err(&ndev->dev, "Receive Frame Overflow\n");
631 } 765 }
632 } 766 }
633#if !defined(CONFIG_CPU_SUBTYPE_SH7763) 767
634 if (intr_status & EESR_ADE) { 768 if (!mdp->cd->no_ade) {
635 if (intr_status & EESR_TDE) { 769 if (intr_status & EESR_ADE && intr_status & EESR_TDE &&
636 if (intr_status & EESR_TFE) 770 intr_status & EESR_TFE)
637 mdp->stats.tx_fifo_errors++; 771 mdp->stats.tx_fifo_errors++;
638 }
639 } 772 }
640#endif
641 773
642 if (intr_status & EESR_RDE) { 774 if (intr_status & EESR_RDE) {
643 /* Receive Descriptor Empty int */ 775 /* Receive Descriptor Empty int */
@@ -645,24 +777,24 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
645 777
646 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R) 778 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
647 ctrl_outl(EDRRR_R, ioaddr + EDRRR); 779 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
648 printk(KERN_ERR "Receive Descriptor Empty\n"); 780 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
649 } 781 }
650 if (intr_status & EESR_RFE) { 782 if (intr_status & EESR_RFE) {
651 /* Receive FIFO Overflow int */ 783 /* Receive FIFO Overflow int */
652 mdp->stats.rx_fifo_errors++; 784 mdp->stats.rx_fifo_errors++;
653 printk(KERN_ERR "Receive FIFO Overflow\n"); 785 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
654 } 786 }
655 if (intr_status & (EESR_TWB | EESR_TABT | 787
656#if !defined(CONFIG_CPU_SUBTYPE_SH7763) 788 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
657 EESR_ADE | 789 if (mdp->cd->no_ade)
658#endif 790 mask &= ~EESR_ADE;
659 EESR_TDE | EESR_TFE)) { 791 if (intr_status & mask) {
660 /* Tx error */ 792 /* Tx error */
661 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR); 793 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
662 /* dmesg */ 794 /* dmesg */
663 printk(KERN_ERR "%s:TX error. status=%8.8x cur_tx=%8.8x ", 795 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
664 ndev->name, intr_status, mdp->cur_tx); 796 intr_status, mdp->cur_tx);
665 printk(KERN_ERR "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 797 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
666 mdp->dirty_tx, (u32) ndev->state, edtrr); 798 mdp->dirty_tx, (u32) ndev->state, edtrr);
667 /* dirty buffer free */ 799 /* dirty buffer free */
668 sh_eth_txfree(ndev); 800 sh_eth_txfree(ndev);
@@ -681,6 +813,7 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
681{ 813{
682 struct net_device *ndev = netdev; 814 struct net_device *ndev = netdev;
683 struct sh_eth_private *mdp = netdev_priv(ndev); 815 struct sh_eth_private *mdp = netdev_priv(ndev);
816 struct sh_eth_cpu_data *cd = mdp->cd;
684 irqreturn_t ret = IRQ_NONE; 817 irqreturn_t ret = IRQ_NONE;
685 u32 ioaddr, boguscnt = RX_RING_SIZE; 818 u32 ioaddr, boguscnt = RX_RING_SIZE;
686 u32 intr_status = 0; 819 u32 intr_status = 0;
@@ -693,7 +826,7 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
693 /* Clear interrupt */ 826 /* Clear interrupt */
694 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | 827 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
695 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | 828 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
696 TX_CHECK | EESR_ERR_CHECK)) { 829 cd->tx_check | cd->eesr_err_check)) {
697 ctrl_outl(intr_status, ioaddr + EESR); 830 ctrl_outl(intr_status, ioaddr + EESR);
698 ret = IRQ_HANDLED; 831 ret = IRQ_HANDLED;
699 } else 832 } else
@@ -710,12 +843,12 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
710 } 843 }
711 844
712 /* Tx Check */ 845 /* Tx Check */
713 if (intr_status & TX_CHECK) { 846 if (intr_status & cd->tx_check) {
714 sh_eth_txfree(ndev); 847 sh_eth_txfree(ndev);
715 netif_wake_queue(ndev); 848 netif_wake_queue(ndev);
716 } 849 }
717 850
718 if (intr_status & EESR_ERR_CHECK) 851 if (intr_status & cd->eesr_err_check)
719 sh_eth_error(ndev, intr_status); 852 sh_eth_error(ndev, intr_status);
720 853
721 if (--boguscnt < 0) { 854 if (--boguscnt < 0) {
@@ -750,32 +883,15 @@ static void sh_eth_adjust_link(struct net_device *ndev)
750 if (phydev->duplex != mdp->duplex) { 883 if (phydev->duplex != mdp->duplex) {
751 new_state = 1; 884 new_state = 1;
752 mdp->duplex = phydev->duplex; 885 mdp->duplex = phydev->duplex;
753#if defined(CONFIG_CPU_SUBTYPE_SH7763) 886 if (mdp->cd->set_duplex)
754 if (mdp->duplex) { /* FULL */ 887 mdp->cd->set_duplex(ndev);
755 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM,
756 ioaddr + ECMR);
757 } else { /* Half */
758 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM,
759 ioaddr + ECMR);
760 }
761#endif
762 } 888 }
763 889
764 if (phydev->speed != mdp->speed) { 890 if (phydev->speed != mdp->speed) {
765 new_state = 1; 891 new_state = 1;
766 mdp->speed = phydev->speed; 892 mdp->speed = phydev->speed;
767#if defined(CONFIG_CPU_SUBTYPE_SH7763) 893 if (mdp->cd->set_rate)
768 switch (mdp->speed) { 894 mdp->cd->set_rate(ndev);
769 case 10: /* 10BASE */
770 ctrl_outl(GECMR_10, ioaddr + GECMR); break;
771 case 100:/* 100BASE */
772 ctrl_outl(GECMR_100, ioaddr + GECMR); break;
773 case 1000: /* 1000BASE */
774 ctrl_outl(GECMR_1000, ioaddr + GECMR); break;
775 default:
776 break;
777 }
778#endif
779 } 895 }
780 if (mdp->link == PHY_DOWN) { 896 if (mdp->link == PHY_DOWN) {
781 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF) 897 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
@@ -815,8 +931,9 @@ static int sh_eth_phy_init(struct net_device *ndev)
815 dev_err(&ndev->dev, "phy_connect failed\n"); 931 dev_err(&ndev->dev, "phy_connect failed\n");
816 return PTR_ERR(phydev); 932 return PTR_ERR(phydev);
817 } 933 }
934
818 dev_info(&ndev->dev, "attached phy %i to driver %s\n", 935 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
819 phydev->addr, phydev->drv->name); 936 phydev->addr, phydev->drv->name);
820 937
821 mdp->phydev = phydev; 938 mdp->phydev = phydev;
822 939
@@ -854,7 +971,7 @@ static int sh_eth_open(struct net_device *ndev)
854#endif 971#endif
855 ndev->name, ndev); 972 ndev->name, ndev);
856 if (ret) { 973 if (ret) {
857 printk(KERN_ERR "Can not assign IRQ number to %s\n", CARDNAME); 974 dev_err(&ndev->dev, "Can not assign IRQ number\n");
858 return ret; 975 return ret;
859 } 976 }
860 977
@@ -951,7 +1068,9 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
951 txdesc = &mdp->tx_ring[entry]; 1068 txdesc = &mdp->tx_ring[entry];
952 txdesc->addr = virt_to_phys(skb->data); 1069 txdesc->addr = virt_to_phys(skb->data);
953 /* soft swap. */ 1070 /* soft swap. */
954 swaps(phys_to_virt(ALIGN(txdesc->addr, 4)), skb->len + 2); 1071 if (!mdp->cd->hw_swap)
1072 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1073 skb->len + 2);
955 /* write back */ 1074 /* write back */
956 __flush_purge_region(skb->data, skb->len); 1075 __flush_purge_region(skb->data, skb->len);
957 if (skb->len < ETHERSMALL) 1076 if (skb->len < ETHERSMALL)
@@ -1053,7 +1172,7 @@ static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1053 return phy_mii_ioctl(phydev, if_mii(rq), cmd); 1172 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
1054} 1173}
1055 1174
1056 1175#if defined(SH_ETH_HAS_TSU)
1057/* Multicast reception directions set */ 1176/* Multicast reception directions set */
1058static void sh_eth_set_multicast_list(struct net_device *ndev) 1177static void sh_eth_set_multicast_list(struct net_device *ndev)
1059{ 1178{
@@ -1098,6 +1217,7 @@ static void sh_eth_tsu_init(u32 ioaddr)
1098 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */ 1217 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1099 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */ 1218 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1100} 1219}
1220#endif /* SH_ETH_HAS_TSU */
1101 1221
1102/* MDIO bus release function */ 1222/* MDIO bus release function */
1103static int sh_mdio_release(struct net_device *ndev) 1223static int sh_mdio_release(struct net_device *ndev)
@@ -1187,7 +1307,9 @@ static const struct net_device_ops sh_eth_netdev_ops = {
1187 .ndo_stop = sh_eth_close, 1307 .ndo_stop = sh_eth_close,
1188 .ndo_start_xmit = sh_eth_start_xmit, 1308 .ndo_start_xmit = sh_eth_start_xmit,
1189 .ndo_get_stats = sh_eth_get_stats, 1309 .ndo_get_stats = sh_eth_get_stats,
1310#if defined(SH_ETH_HAS_TSU)
1190 .ndo_set_multicast_list = sh_eth_set_multicast_list, 1311 .ndo_set_multicast_list = sh_eth_set_multicast_list,
1312#endif
1191 .ndo_tx_timeout = sh_eth_tx_timeout, 1313 .ndo_tx_timeout = sh_eth_tx_timeout,
1192 .ndo_do_ioctl = sh_eth_do_ioctl, 1314 .ndo_do_ioctl = sh_eth_do_ioctl,
1193 .ndo_validate_addr = eth_validate_addr, 1315 .ndo_validate_addr = eth_validate_addr,
@@ -1213,7 +1335,7 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1213 1335
1214 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 1336 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1215 if (!ndev) { 1337 if (!ndev) {
1216 printk(KERN_ERR "%s: could not allocate device.\n", CARDNAME); 1338 dev_err(&pdev->dev, "Could not allocate device.\n");
1217 ret = -ENOMEM; 1339 ret = -ENOMEM;
1218 goto out; 1340 goto out;
1219 } 1341 }
@@ -1246,6 +1368,10 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1246 /* EDMAC endian */ 1368 /* EDMAC endian */
1247 mdp->edmac_endian = pd->edmac_endian; 1369 mdp->edmac_endian = pd->edmac_endian;
1248 1370
1371 /* set cpu data */
1372 mdp->cd = &sh_eth_my_cpu_data;
1373 sh_eth_set_default_cpu_data(mdp->cd);
1374
1249 /* set function */ 1375 /* set function */
1250 ndev->netdev_ops = &sh_eth_netdev_ops; 1376 ndev->netdev_ops = &sh_eth_netdev_ops;
1251 ndev->watchdog_timeo = TX_TIMEOUT; 1377 ndev->watchdog_timeo = TX_TIMEOUT;
@@ -1258,13 +1384,10 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1258 1384
1259 /* First device only init */ 1385 /* First device only init */
1260 if (!devno) { 1386 if (!devno) {
1261#if defined(ARSTR) 1387 if (mdp->cd->chip_reset)
1262 /* reset device */ 1388 mdp->cd->chip_reset(ndev);
1263 ctrl_outl(ARSTR_ARSTR, ARSTR);
1264 mdelay(1);
1265#endif
1266 1389
1267#if defined(SH_TSU_ADDR) 1390#if defined(SH_ETH_HAS_TSU)
1268 /* TSU init (Init only)*/ 1391 /* TSU init (Init only)*/
1269 sh_eth_tsu_init(SH_TSU_ADDR); 1392 sh_eth_tsu_init(SH_TSU_ADDR);
1270#endif 1393#endif
@@ -1281,8 +1404,8 @@ static int sh_eth_drv_probe(struct platform_device *pdev)
1281 goto out_unregister; 1404 goto out_unregister;
1282 1405
1283 /* pritnt device infomation */ 1406 /* pritnt device infomation */
1284 printk(KERN_INFO "%s: %s at 0x%x, ", 1407 pr_info("Base address at 0x%x, ",
1285 ndev->name, CARDNAME, (u32) ndev->base_addr); 1408 (u32)ndev->base_addr);
1286 1409
1287 for (i = 0; i < 5; i++) 1410 for (i = 0; i < 5; i++)
1288 printk("%02X:", ndev->dev_addr[i]); 1411 printk("%02X:", ndev->dev_addr[i]);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 03:34:50 -0500