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authorYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>2010-07-05 14:32:50 -0400
committerDavid S. Miller <davem@davemloft.net>2010-07-07 18:45:00 -0400
commitf29a3d040727a80c3307a2bea057206be049c305 (patch)
treefeaedf1ea5e2c0cd17d5ed39aed1d91793f7eedb /drivers/net/sh_eth.c
parent6f3c72a2148f5f99c4dcc97cbcea06916136c862 (diff)
net: sh_eth: add support for SH7757's ETHER
The SH7757 has 2 Fast Ethernet controller (ETHER) and 2 Gigabit Ethernet Controller (GETHER). This patch supports 2 ETHER only. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sh_eth.c')
-rw-r--r--drivers/net/sh_eth.c53
1 files changed, 52 insertions, 1 deletions
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 501a55ffce57..7ac814d932b1 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -88,6 +88,55 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
88 .rpadir = 1, 88 .rpadir = 1,
89 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 89 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
90}; 90};
91#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
92#define SH_ETH_RESET_DEFAULT 1
93static void sh_eth_set_duplex(struct net_device *ndev)
94{
95 struct sh_eth_private *mdp = netdev_priv(ndev);
96 u32 ioaddr = ndev->base_addr;
97
98 if (mdp->duplex) /* Full */
99 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
100 else /* Half */
101 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
102}
103
104static void sh_eth_set_rate(struct net_device *ndev)
105{
106 struct sh_eth_private *mdp = netdev_priv(ndev);
107 u32 ioaddr = ndev->base_addr;
108
109 switch (mdp->speed) {
110 case 10: /* 10BASE */
111 ctrl_outl(0, ioaddr + RTRATE);
112 break;
113 case 100:/* 100BASE */
114 ctrl_outl(1, ioaddr + RTRATE);
115 break;
116 default:
117 break;
118 }
119}
120
121/* SH7757 */
122static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
123 .set_duplex = sh_eth_set_duplex,
124 .set_rate = sh_eth_set_rate,
125
126 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
127 .rmcr_value = 0x00000001,
128
129 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
130 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
131 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
132 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
133
134 .apr = 1,
135 .mpr = 1,
136 .tpauser = 1,
137 .hw_swap = 1,
138 .no_ade = 1,
139};
91 140
92#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 141#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
93#define SH_ETH_HAS_TSU 1 142#define SH_ETH_HAS_TSU 1
@@ -1023,7 +1072,9 @@ static int sh_eth_open(struct net_device *ndev)
1023 pm_runtime_get_sync(&mdp->pdev->dev); 1072 pm_runtime_get_sync(&mdp->pdev->dev);
1024 1073
1025 ret = request_irq(ndev->irq, sh_eth_interrupt, 1074 ret = request_irq(ndev->irq, sh_eth_interrupt,
1026#if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764) 1075#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1076 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1077 defined(CONFIG_CPU_SUBTYPE_SH7757)
1027 IRQF_SHARED, 1078 IRQF_SHARED,
1028#else 1079#else
1029 0, 1080 0,