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authorRalf Baechle <ralf@linux-mips.org>2005-10-10 09:50:56 -0400
committerJeff Garzik <jgarzik@pobox.com>2005-10-18 18:03:47 -0400
commit302a5c4b3d4d6aff7772a4b3431bb772586e6011 (patch)
tree0f08e4c1419dae13e86039b53db2271d57bde4e3 /drivers/net/sgiseeq.c
parent2891439e7378e35534d7eb32f77671dc4d61db4c (diff)
[PATCH] sgiseeq: Configure PIO and DMA timing requests.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> drivers/net/sgiseeq.c | 28 ++++++++++++++-------------- include/asm-mips/sgi/hpc3.h | 40 ++++++++++++++++++++-------------------- 2 files changed, 34 insertions(+), 34 deletions(-) Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/sgiseeq.c')
-rw-r--r--drivers/net/sgiseeq.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/net/sgiseeq.c b/drivers/net/sgiseeq.c
index a9d2e4fd0aec..a4614df38a90 100644
--- a/drivers/net/sgiseeq.c
+++ b/drivers/net/sgiseeq.c
@@ -32,8 +32,6 @@
32 32
33#include "sgiseeq.h" 33#include "sgiseeq.h"
34 34
35static char *version = "sgiseeq.c: David S. Miller (dm@engr.sgi.com)\n";
36
37static char *sgiseeqstr = "SGI Seeq8003"; 35static char *sgiseeqstr = "SGI Seeq8003";
38 36
39/* 37/*
@@ -113,9 +111,9 @@ static struct net_device *root_sgiseeq_dev;
113 111
114static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs) 112static inline void hpc3_eth_reset(struct hpc3_ethregs *hregs)
115{ 113{
116 hregs->rx_reset = HPC3_ERXRST_CRESET | HPC3_ERXRST_CLRIRQ; 114 hregs->reset = HPC3_ERST_CRESET | HPC3_ERST_CLRIRQ;
117 udelay(20); 115 udelay(20);
118 hregs->rx_reset = 0; 116 hregs->reset = 0;
119} 117}
120 118
121static inline void reset_hpc3_and_seeq(struct hpc3_ethregs *hregs, 119static inline void reset_hpc3_and_seeq(struct hpc3_ethregs *hregs,
@@ -252,7 +250,6 @@ void sgiseeq_dump_rings(void)
252 250
253#define TSTAT_INIT_SEEQ (SEEQ_TCMD_IPT|SEEQ_TCMD_I16|SEEQ_TCMD_IC|SEEQ_TCMD_IUF) 251#define TSTAT_INIT_SEEQ (SEEQ_TCMD_IPT|SEEQ_TCMD_I16|SEEQ_TCMD_IC|SEEQ_TCMD_IUF)
254#define TSTAT_INIT_EDLC ((TSTAT_INIT_SEEQ) | SEEQ_TCMD_RB2) 252#define TSTAT_INIT_EDLC ((TSTAT_INIT_SEEQ) | SEEQ_TCMD_RB2)
255#define RDMACFG_INIT (HPC3_ERXDCFG_FRXDC | HPC3_ERXDCFG_FEOP | HPC3_ERXDCFG_FIRQ)
256 253
257static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp, 254static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp,
258 struct sgiseeq_regs *sregs) 255 struct sgiseeq_regs *sregs)
@@ -274,8 +271,6 @@ static int init_seeq(struct net_device *dev, struct sgiseeq_private *sp,
274 sregs->tstat = TSTAT_INIT_SEEQ; 271 sregs->tstat = TSTAT_INIT_SEEQ;
275 } 272 }
276 273
277 hregs->rx_dconfig |= RDMACFG_INIT;
278
279 hregs->rx_ndptr = CPHYSADDR(sp->rx_desc); 274 hregs->rx_ndptr = CPHYSADDR(sp->rx_desc);
280 hregs->tx_ndptr = CPHYSADDR(sp->tx_desc); 275 hregs->tx_ndptr = CPHYSADDR(sp->tx_desc);
281 276
@@ -446,7 +441,7 @@ static irqreturn_t sgiseeq_interrupt(int irq, void *dev_id, struct pt_regs *regs
446 spin_lock(&sp->tx_lock); 441 spin_lock(&sp->tx_lock);
447 442
448 /* Ack the IRQ and set software state. */ 443 /* Ack the IRQ and set software state. */
449 hregs->rx_reset = HPC3_ERXRST_CLRIRQ; 444 hregs->reset = HPC3_ERST_CLRIRQ;
450 445
451 /* Always check for received packets. */ 446 /* Always check for received packets. */
452 sgiseeq_rx(dev, sp, hregs, sregs); 447 sgiseeq_rx(dev, sp, hregs, sregs);
@@ -646,7 +641,7 @@ static inline void setup_rx_ring(struct sgiseeq_rx_desc *buf, int nbufs)
646 641
647#define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf)) 642#define ALIGNED(x) ((((unsigned long)(x)) + 0xf) & ~(0xf))
648 643
649static int sgiseeq_init(struct hpc3_regs* regs, int irq) 644static int sgiseeq_init(struct hpc3_regs* hpcregs, int irq)
650{ 645{
651 struct sgiseeq_init_block *sr; 646 struct sgiseeq_init_block *sr;
652 struct sgiseeq_private *sp; 647 struct sgiseeq_private *sp;
@@ -682,8 +677,8 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq)
682 gpriv = sp; 677 gpriv = sp;
683 gdev = dev; 678 gdev = dev;
684#endif 679#endif
685 sp->sregs = (struct sgiseeq_regs *) &hpc3c0->eth_ext[0]; 680 sp->sregs = (struct sgiseeq_regs *) &hpcregs->eth_ext[0];
686 sp->hregs = &hpc3c0->ethregs; 681 sp->hregs = &hpcregs->ethregs;
687 sp->name = sgiseeqstr; 682 sp->name = sgiseeqstr;
688 sp->mode = SEEQ_RCMD_RBCAST; 683 sp->mode = SEEQ_RCMD_RBCAST;
689 684
@@ -700,6 +695,11 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq)
700 setup_rx_ring(sp->rx_desc, SEEQ_RX_BUFFERS); 695 setup_rx_ring(sp->rx_desc, SEEQ_RX_BUFFERS);
701 setup_tx_ring(sp->tx_desc, SEEQ_TX_BUFFERS); 696 setup_tx_ring(sp->tx_desc, SEEQ_TX_BUFFERS);
702 697
698 /* Setup PIO and DMA transfer timing */
699 sp->hregs->pconfig = 0x161;
700 sp->hregs->dconfig = HPC3_EDCFG_FIRQ | HPC3_EDCFG_FEOP |
701 HPC3_EDCFG_FRXDC | HPC3_EDCFG_PTO | 0x026;
702
703 /* Reset the chip. */ 703 /* Reset the chip. */
704 hpc3_eth_reset(sp->hregs); 704 hpc3_eth_reset(sp->hregs);
705 705
@@ -726,7 +726,7 @@ static int sgiseeq_init(struct hpc3_regs* regs, int irq)
726 goto err_out_free_page; 726 goto err_out_free_page;
727 } 727 }
728 728
729 printk(KERN_INFO "%s: SGI Seeq8003 ", dev->name); 729 printk(KERN_INFO "%s: %s ", dev->name, sgiseeqstr);
730 for (i = 0; i < 6; i++) 730 for (i = 0; i < 6; i++)
731 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? '\n' : ':'); 731 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? '\n' : ':');
732 732
@@ -746,8 +746,6 @@ err_out:
746 746
747static int __init sgiseeq_probe(void) 747static int __init sgiseeq_probe(void)
748{ 748{
749 printk(version);
750
751 /* On board adapter on 1st HPC is always present */ 749 /* On board adapter on 1st HPC is always present */
752 return sgiseeq_init(hpc3c0, SGI_ENET_IRQ); 750 return sgiseeq_init(hpc3c0, SGI_ENET_IRQ);
753} 751}
@@ -769,4 +767,6 @@ static void __exit sgiseeq_exit(void)
769module_init(sgiseeq_probe); 767module_init(sgiseeq_probe);
770module_exit(sgiseeq_exit); 768module_exit(sgiseeq_exit);
771 769
770MODULE_DESCRIPTION("SGI Seeq 8003 driver");
771MODULE_AUTHOR("Linux/MIPS Mailing List <linux-mips@linux-mips.org>");
772MODULE_LICENSE("GPL"); 772MODULE_LICENSE("GPL");