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authorBen Hutchings <bhutchings@solarflare.com>2011-02-24 14:30:41 -0500
committerBen Hutchings <bhutchings@solarflare.com>2011-02-28 18:57:24 -0500
commit5fb6b06d4eda2167eab662ad5e30058cecd67b8b (patch)
tree854a97a5c9db96a95fc23464677b087c93377b22 /drivers/net/sfc
parent119226c563be011c6396c6a2d268d1ca7e467bd3 (diff)
sfc: Remove configurable FIFO thresholds for pause frame generation
In Falcon we can configure the fill levels of the RX data FIFO which trigger the generation of pause frames (if enabled), and we have module parameters for this. Siena does not allow the levels to be configured (or, if it does, this is done by the MC firmware and is not configurable by drivers). So far as I can tell, the module parameters are not used by our internal scripts and have not been documented (with the exception of the short parameter descriptions). Therefore, remove them and always initialise Falcon with the default values. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat (limited to 'drivers/net/sfc')
-rw-r--r--drivers/net/sfc/falcon.c20
-rw-r--r--drivers/net/sfc/nic.c20
-rw-r--r--drivers/net/sfc/nic.h1
-rw-r--r--drivers/net/sfc/siena.c5
4 files changed, 5 insertions, 41 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 87481a6df42c..734fcfb52e85 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -1478,36 +1478,26 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
1478 /* RX control FIFO thresholds (32 entries) */ 1478 /* RX control FIFO thresholds (32 entries) */
1479 const unsigned ctrl_xon_thr = 20; 1479 const unsigned ctrl_xon_thr = 20;
1480 const unsigned ctrl_xoff_thr = 25; 1480 const unsigned ctrl_xoff_thr = 25;
1481 /* RX data FIFO thresholds (256-byte units; size varies) */
1482 int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1483 int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1484 efx_oword_t reg; 1481 efx_oword_t reg;
1485 1482
1486 efx_reado(efx, &reg, FR_AZ_RX_CFG); 1483 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1487 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { 1484 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1488 /* Data FIFO size is 5.5K */ 1485 /* Data FIFO size is 5.5K */
1489 if (data_xon_thr < 0)
1490 data_xon_thr = 512 >> 8;
1491 if (data_xoff_thr < 0)
1492 data_xoff_thr = 2048 >> 8;
1493 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); 1486 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1494 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, 1487 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1495 huge_buf_size); 1488 huge_buf_size);
1496 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); 1489 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, 512 >> 8);
1497 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); 1490 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, 2048 >> 8);
1498 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); 1491 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1499 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); 1492 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1500 } else { 1493 } else {
1501 /* Data FIFO size is 80K; register fields moved */ 1494 /* Data FIFO size is 80K; register fields moved */
1502 if (data_xon_thr < 0)
1503 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1504 if (data_xoff_thr < 0)
1505 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1506 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); 1495 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1507 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, 1496 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1508 huge_buf_size); 1497 huge_buf_size);
1509 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); 1498 /* Send XON and XOFF at ~3 * max MTU away from empty/full */
1510 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); 1499 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, 27648 >> 8);
1500 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, 54272 >> 8);
1511 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); 1501 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1512 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); 1502 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1513 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); 1503 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
diff --git a/drivers/net/sfc/nic.c b/drivers/net/sfc/nic.c
index fb25b87a1835..e8396614daf3 100644
--- a/drivers/net/sfc/nic.c
+++ b/drivers/net/sfc/nic.c
@@ -41,26 +41,6 @@
41#define RX_DC_ENTRIES 64 41#define RX_DC_ENTRIES 64
42#define RX_DC_ENTRIES_ORDER 3 42#define RX_DC_ENTRIES_ORDER 3
43 43
44/* RX FIFO XOFF watermark
45 *
46 * When the amount of the RX FIFO increases used increases past this
47 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
48 * This also has an effect on RX/TX arbitration
49 */
50int efx_nic_rx_xoff_thresh = -1;
51module_param_named(rx_xoff_thresh_bytes, efx_nic_rx_xoff_thresh, int, 0644);
52MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
53
54/* RX FIFO XON watermark
55 *
56 * When the amount of the RX FIFO used decreases below this
57 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
58 * This also has an effect on RX/TX arbitration
59 */
60int efx_nic_rx_xon_thresh = -1;
61module_param_named(rx_xon_thresh_bytes, efx_nic_rx_xon_thresh, int, 0644);
62MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
63
64/* If EFX_MAX_INT_ERRORS internal errors occur within 44/* If EFX_MAX_INT_ERRORS internal errors occur within
65 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and 45 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
66 * disable it. 46 * disable it.
diff --git a/drivers/net/sfc/nic.h b/drivers/net/sfc/nic.h
index 1daaee6c7f07..d9de1b647d41 100644
--- a/drivers/net/sfc/nic.h
+++ b/drivers/net/sfc/nic.h
@@ -188,7 +188,6 @@ extern void efx_nic_eventq_read_ack(struct efx_channel *channel);
188/* MAC/PHY */ 188/* MAC/PHY */
189extern void falcon_drain_tx_fifo(struct efx_nic *efx); 189extern void falcon_drain_tx_fifo(struct efx_nic *efx);
190extern void falcon_reconfigure_mac_wrapper(struct efx_nic *efx); 190extern void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
191extern int efx_nic_rx_xoff_thresh, efx_nic_rx_xon_thresh;
192 191
193/* Interrupts and test events */ 192/* Interrupts and test events */
194extern int efx_nic_init_interrupt(struct efx_nic *efx); 193extern int efx_nic_init_interrupt(struct efx_nic *efx);
diff --git a/drivers/net/sfc/siena.c b/drivers/net/sfc/siena.c
index 8bd537e1de7f..e4dd8986b1fe 100644
--- a/drivers/net/sfc/siena.c
+++ b/drivers/net/sfc/siena.c
@@ -341,11 +341,6 @@ static int siena_init_nic(struct efx_nic *efx)
341 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8); 341 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
342 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3); 342 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
343 343
344 if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
345 /* No MCDI operation has been defined to set thresholds */
346 netif_err(efx, hw, efx->net_dev,
347 "ignoring RX flow control thresholds\n");
348
349 /* Enable event logging */ 344 /* Enable event logging */
350 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 345 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
351 if (rc) 346 if (rc)