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authorBen Hutchings <bhutchings@solarflare.com>2010-12-06 17:55:18 -0500
committerBen Hutchings <bhutchings@solarflare.com>2010-12-06 17:55:18 -0500
commit494bdf1b0fd58688d055f1b66c34b0844dcfc1fa (patch)
treeb25bdaa90516813e19b5ee97de336da123f01bcd /drivers/net/sfc
parent9f2f6cd07a09bc0af1f2950189e426569561d1e6 (diff)
sfc: Remove redundant memory barriers between MMIOs
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat (limited to 'drivers/net/sfc')
-rw-r--r--drivers/net/sfc/io.h5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/net/sfc/io.h b/drivers/net/sfc/io.h
index 0764e84ecc41..896b31e8606d 100644
--- a/drivers/net/sfc/io.h
+++ b/drivers/net/sfc/io.h
@@ -96,13 +96,11 @@ static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
96 spin_lock_irqsave(&efx->biu_lock, flags); 96 spin_lock_irqsave(&efx->biu_lock, flags);
97#ifdef EFX_USE_QWORD_IO 97#ifdef EFX_USE_QWORD_IO
98 _efx_writeq(efx, value->u64[0], reg + 0); 98 _efx_writeq(efx, value->u64[0], reg + 0);
99 wmb();
100 _efx_writeq(efx, value->u64[1], reg + 8); 99 _efx_writeq(efx, value->u64[1], reg + 8);
101#else 100#else
102 _efx_writed(efx, value->u32[0], reg + 0); 101 _efx_writed(efx, value->u32[0], reg + 0);
103 _efx_writed(efx, value->u32[1], reg + 4); 102 _efx_writed(efx, value->u32[1], reg + 4);
104 _efx_writed(efx, value->u32[2], reg + 8); 103 _efx_writed(efx, value->u32[2], reg + 8);
105 wmb();
106 _efx_writed(efx, value->u32[3], reg + 12); 104 _efx_writed(efx, value->u32[3], reg + 12);
107#endif 105#endif
108 mmiowb(); 106 mmiowb();
@@ -125,7 +123,6 @@ static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
125 __raw_writeq((__force u64)value->u64[0], membase + addr); 123 __raw_writeq((__force u64)value->u64[0], membase + addr);
126#else 124#else
127 __raw_writel((__force u32)value->u32[0], membase + addr); 125 __raw_writel((__force u32)value->u32[0], membase + addr);
128 wmb();
129 __raw_writel((__force u32)value->u32[1], membase + addr + 4); 126 __raw_writel((__force u32)value->u32[1], membase + addr + 4);
130#endif 127#endif
131 mmiowb(); 128 mmiowb();
@@ -152,7 +149,6 @@ static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
152 149
153 spin_lock_irqsave(&efx->biu_lock, flags); 150 spin_lock_irqsave(&efx->biu_lock, flags);
154 value->u32[0] = _efx_readd(efx, reg + 0); 151 value->u32[0] = _efx_readd(efx, reg + 0);
155 rmb();
156 value->u32[1] = _efx_readd(efx, reg + 4); 152 value->u32[1] = _efx_readd(efx, reg + 4);
157 value->u32[2] = _efx_readd(efx, reg + 8); 153 value->u32[2] = _efx_readd(efx, reg + 8);
158 value->u32[3] = _efx_readd(efx, reg + 12); 154 value->u32[3] = _efx_readd(efx, reg + 12);
@@ -175,7 +171,6 @@ static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
175 value->u64[0] = (__force __le64)__raw_readq(membase + addr); 171 value->u64[0] = (__force __le64)__raw_readq(membase + addr);
176#else 172#else
177 value->u32[0] = (__force __le32)__raw_readl(membase + addr); 173 value->u32[0] = (__force __le32)__raw_readl(membase + addr);
178 rmb();
179 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); 174 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
180#endif 175#endif
181 spin_unlock_irqrestore(&efx->biu_lock, flags); 176 spin_unlock_irqrestore(&efx->biu_lock, flags);