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authorBen Hutchings <bhutchings@solarflare.com>2008-09-01 07:48:55 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-09-03 09:53:48 -0400
commita515089c963b045f65c495cee1d344d8cb75e1d1 (patch)
tree55bc6bbbe1d70b3cc2bbcbc1d778d4271efcf480 /drivers/net/sfc
parent2467ca46b6bb7672ed59fc74ac6780bf10bcd742 (diff)
sfc: Rework the bitfield header so that we can identify fields by bit number
This will support register self-tests. From: Steve Hodgson <shodgson@solarflare.com> Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/sfc')
-rw-r--r--drivers/net/sfc/bitfield.h159
-rw-r--r--drivers/net/sfc/falcon_hwdefs.h4
2 files changed, 95 insertions, 68 deletions
diff --git a/drivers/net/sfc/bitfield.h b/drivers/net/sfc/bitfield.h
index 2c79d27404e0..b757a39f078e 100644
--- a/drivers/net/sfc/bitfield.h
+++ b/drivers/net/sfc/bitfield.h
@@ -52,9 +52,9 @@
52 * 52 *
53 * The maximum width mask that can be generated is 64 bits. 53 * The maximum width mask that can be generated is 64 bits.
54 */ 54 */
55#define EFX_MASK64(field) \ 55#define EFX_MASK64(width) \
56 (EFX_WIDTH(field) == 64 ? ~((u64) 0) : \ 56 ((width) == 64 ? ~((u64) 0) : \
57 (((((u64) 1) << EFX_WIDTH(field))) - 1)) 57 (((((u64) 1) << (width))) - 1))
58 58
59/* Mask equal in width to the specified field. 59/* Mask equal in width to the specified field.
60 * 60 *
@@ -63,9 +63,9 @@
63 * The maximum width mask that can be generated is 32 bits. Use 63 * The maximum width mask that can be generated is 32 bits. Use
64 * EFX_MASK64 for higher width fields. 64 * EFX_MASK64 for higher width fields.
65 */ 65 */
66#define EFX_MASK32(field) \ 66#define EFX_MASK32(width) \
67 (EFX_WIDTH(field) == 32 ? ~((u32) 0) : \ 67 ((width) == 32 ? ~((u32) 0) : \
68 (((((u32) 1) << EFX_WIDTH(field))) - 1)) 68 (((((u32) 1) << (width))) - 1))
69 69
70/* A doubleword (i.e. 4 byte) datatype - little-endian in HW */ 70/* A doubleword (i.e. 4 byte) datatype - little-endian in HW */
71typedef union efx_dword { 71typedef union efx_dword {
@@ -138,44 +138,49 @@ typedef union efx_oword {
138 EFX_EXTRACT_NATIVE(le32_to_cpu(element), min, max, low, high) 138 EFX_EXTRACT_NATIVE(le32_to_cpu(element), min, max, low, high)
139 139
140#define EFX_EXTRACT_OWORD64(oword, low, high) \ 140#define EFX_EXTRACT_OWORD64(oword, low, high) \
141 (EFX_EXTRACT64((oword).u64[0], 0, 63, low, high) | \ 141 ((EFX_EXTRACT64((oword).u64[0], 0, 63, low, high) | \
142 EFX_EXTRACT64((oword).u64[1], 64, 127, low, high)) 142 EFX_EXTRACT64((oword).u64[1], 64, 127, low, high)) & \
143 EFX_MASK64(high + 1 - low))
143 144
144#define EFX_EXTRACT_QWORD64(qword, low, high) \ 145#define EFX_EXTRACT_QWORD64(qword, low, high) \
145 EFX_EXTRACT64((qword).u64[0], 0, 63, low, high) 146 (EFX_EXTRACT64((qword).u64[0], 0, 63, low, high) & \
147 EFX_MASK64(high + 1 - low))
146 148
147#define EFX_EXTRACT_OWORD32(oword, low, high) \ 149#define EFX_EXTRACT_OWORD32(oword, low, high) \
148 (EFX_EXTRACT32((oword).u32[0], 0, 31, low, high) | \ 150 ((EFX_EXTRACT32((oword).u32[0], 0, 31, low, high) | \
149 EFX_EXTRACT32((oword).u32[1], 32, 63, low, high) | \ 151 EFX_EXTRACT32((oword).u32[1], 32, 63, low, high) | \
150 EFX_EXTRACT32((oword).u32[2], 64, 95, low, high) | \ 152 EFX_EXTRACT32((oword).u32[2], 64, 95, low, high) | \
151 EFX_EXTRACT32((oword).u32[3], 96, 127, low, high)) 153 EFX_EXTRACT32((oword).u32[3], 96, 127, low, high)) & \
154 EFX_MASK32(high + 1 - low))
152 155
153#define EFX_EXTRACT_QWORD32(qword, low, high) \ 156#define EFX_EXTRACT_QWORD32(qword, low, high) \
154 (EFX_EXTRACT32((qword).u32[0], 0, 31, low, high) | \ 157 ((EFX_EXTRACT32((qword).u32[0], 0, 31, low, high) | \
155 EFX_EXTRACT32((qword).u32[1], 32, 63, low, high)) 158 EFX_EXTRACT32((qword).u32[1], 32, 63, low, high)) & \
159 EFX_MASK32(high + 1 - low))
156 160
157#define EFX_EXTRACT_DWORD(dword, low, high) \ 161#define EFX_EXTRACT_DWORD(dword, low, high) \
158 EFX_EXTRACT32((dword).u32[0], 0, 31, low, high) 162 (EFX_EXTRACT32((dword).u32[0], 0, 31, low, high) & \
163 EFX_MASK32(high + 1 - low))
159 164
160#define EFX_OWORD_FIELD64(oword, field) \ 165#define EFX_OWORD_FIELD64(oword, field) \
161 (EFX_EXTRACT_OWORD64(oword, EFX_LOW_BIT(field), EFX_HIGH_BIT(field)) \ 166 EFX_EXTRACT_OWORD64(oword, EFX_LOW_BIT(field), \
162 & EFX_MASK64(field)) 167 EFX_HIGH_BIT(field))
163 168
164#define EFX_QWORD_FIELD64(qword, field) \ 169#define EFX_QWORD_FIELD64(qword, field) \
165 (EFX_EXTRACT_QWORD64(qword, EFX_LOW_BIT(field), EFX_HIGH_BIT(field)) \ 170 EFX_EXTRACT_QWORD64(qword, EFX_LOW_BIT(field), \
166 & EFX_MASK64(field)) 171 EFX_HIGH_BIT(field))
167 172
168#define EFX_OWORD_FIELD32(oword, field) \ 173#define EFX_OWORD_FIELD32(oword, field) \
169 (EFX_EXTRACT_OWORD32(oword, EFX_LOW_BIT(field), EFX_HIGH_BIT(field)) \ 174 EFX_EXTRACT_OWORD32(oword, EFX_LOW_BIT(field), \
170 & EFX_MASK32(field)) 175 EFX_HIGH_BIT(field))
171 176
172#define EFX_QWORD_FIELD32(qword, field) \ 177#define EFX_QWORD_FIELD32(qword, field) \
173 (EFX_EXTRACT_QWORD32(qword, EFX_LOW_BIT(field), EFX_HIGH_BIT(field)) \ 178 EFX_EXTRACT_QWORD32(qword, EFX_LOW_BIT(field), \
174 & EFX_MASK32(field)) 179 EFX_HIGH_BIT(field))
175 180
176#define EFX_DWORD_FIELD(dword, field) \ 181#define EFX_DWORD_FIELD(dword, field) \
177 (EFX_EXTRACT_DWORD(dword, EFX_LOW_BIT(field), EFX_HIGH_BIT(field)) \ 182 EFX_EXTRACT_DWORD(dword, EFX_LOW_BIT(field), \
178 & EFX_MASK32(field)) 183 EFX_HIGH_BIT(field))
179 184
180#define EFX_OWORD_IS_ZERO64(oword) \ 185#define EFX_OWORD_IS_ZERO64(oword) \
181 (((oword).u64[0] | (oword).u64[1]) == (__force __le64) 0) 186 (((oword).u64[0] | (oword).u64[1]) == (__force __le64) 0)
@@ -417,63 +422,85 @@ typedef union efx_oword {
417 (oword).u64[1] = ~((oword).u64[1]); \ 422 (oword).u64[1] = ~((oword).u64[1]); \
418 } while (0) 423 } while (0)
419 424
420#define EFX_INSERT_FIELD64(...) \ 425#define EFX_INSERT64(min, max, low, high, value) \
421 cpu_to_le64(EFX_INSERT_FIELD_NATIVE(__VA_ARGS__)) 426 cpu_to_le64(EFX_INSERT_NATIVE(min, max, low, high, value))
422 427
423#define EFX_INSERT_FIELD32(...) \ 428#define EFX_INSERT32(min, max, low, high, value) \
424 cpu_to_le32(EFX_INSERT_FIELD_NATIVE(__VA_ARGS__)) 429 cpu_to_le32(EFX_INSERT_NATIVE(min, max, low, high, value))
425 430
426#define EFX_INPLACE_MASK64(min, max, field) \ 431#define EFX_INPLACE_MASK64(min, max, low, high) \
427 EFX_INSERT_FIELD64(min, max, field, EFX_MASK64(field)) 432 EFX_INSERT64(min, max, low, high, EFX_MASK64(high + 1 - low))
428 433
429#define EFX_INPLACE_MASK32(min, max, field) \ 434#define EFX_INPLACE_MASK32(min, max, low, high) \
430 EFX_INSERT_FIELD32(min, max, field, EFX_MASK32(field)) 435 EFX_INSERT32(min, max, low, high, EFX_MASK32(high + 1 - low))
431 436
432#define EFX_SET_OWORD_FIELD64(oword, field, value) do { \ 437#define EFX_SET_OWORD64(oword, low, high, value) do { \
433 (oword).u64[0] = (((oword).u64[0] \ 438 (oword).u64[0] = (((oword).u64[0] \
434 & ~EFX_INPLACE_MASK64(0, 63, field)) \ 439 & ~EFX_INPLACE_MASK64(0, 63, low, high)) \
435 | EFX_INSERT_FIELD64(0, 63, field, value)); \ 440 | EFX_INSERT64(0, 63, low, high, value)); \
436 (oword).u64[1] = (((oword).u64[1] \ 441 (oword).u64[1] = (((oword).u64[1] \
437 & ~EFX_INPLACE_MASK64(64, 127, field)) \ 442 & ~EFX_INPLACE_MASK64(64, 127, low, high)) \
438 | EFX_INSERT_FIELD64(64, 127, field, value)); \ 443 | EFX_INSERT64(64, 127, low, high, value)); \
439 } while (0) 444 } while (0)
440 445
441#define EFX_SET_QWORD_FIELD64(qword, field, value) do { \ 446#define EFX_SET_QWORD64(qword, low, high, value) do { \
442 (qword).u64[0] = (((qword).u64[0] \ 447 (qword).u64[0] = (((qword).u64[0] \
443 & ~EFX_INPLACE_MASK64(0, 63, field)) \ 448 & ~EFX_INPLACE_MASK64(0, 63, low, high)) \
444 | EFX_INSERT_FIELD64(0, 63, field, value)); \ 449 | EFX_INSERT64(0, 63, low, high, value)); \
445 } while (0) 450 } while (0)
446 451
447#define EFX_SET_OWORD_FIELD32(oword, field, value) do { \ 452#define EFX_SET_OWORD32(oword, low, high, value) do { \
448 (oword).u32[0] = (((oword).u32[0] \ 453 (oword).u32[0] = (((oword).u32[0] \
449 & ~EFX_INPLACE_MASK32(0, 31, field)) \ 454 & ~EFX_INPLACE_MASK32(0, 31, low, high)) \
450 | EFX_INSERT_FIELD32(0, 31, field, value)); \ 455 | EFX_INSERT32(0, 31, low, high, value)); \
451 (oword).u32[1] = (((oword).u32[1] \ 456 (oword).u32[1] = (((oword).u32[1] \
452 & ~EFX_INPLACE_MASK32(32, 63, field)) \ 457 & ~EFX_INPLACE_MASK32(32, 63, low, high)) \
453 | EFX_INSERT_FIELD32(32, 63, field, value)); \ 458 | EFX_INSERT32(32, 63, low, high, value)); \
454 (oword).u32[2] = (((oword).u32[2] \ 459 (oword).u32[2] = (((oword).u32[2] \
455 & ~EFX_INPLACE_MASK32(64, 95, field)) \ 460 & ~EFX_INPLACE_MASK32(64, 95, low, high)) \
456 | EFX_INSERT_FIELD32(64, 95, field, value)); \ 461 | EFX_INSERT32(64, 95, low, high, value)); \
457 (oword).u32[3] = (((oword).u32[3] \ 462 (oword).u32[3] = (((oword).u32[3] \
458 & ~EFX_INPLACE_MASK32(96, 127, field)) \ 463 & ~EFX_INPLACE_MASK32(96, 127, low, high)) \
459 | EFX_INSERT_FIELD32(96, 127, field, value)); \ 464 | EFX_INSERT32(96, 127, low, high, value)); \
460 } while (0) 465 } while (0)
461 466
462#define EFX_SET_QWORD_FIELD32(qword, field, value) do { \ 467#define EFX_SET_QWORD32(qword, low, high, value) do { \
463 (qword).u32[0] = (((qword).u32[0] \ 468 (qword).u32[0] = (((qword).u32[0] \
464 & ~EFX_INPLACE_MASK32(0, 31, field)) \ 469 & ~EFX_INPLACE_MASK32(0, 31, low, high)) \
465 | EFX_INSERT_FIELD32(0, 31, field, value)); \ 470 | EFX_INSERT32(0, 31, low, high, value)); \
466 (qword).u32[1] = (((qword).u32[1] \ 471 (qword).u32[1] = (((qword).u32[1] \
467 & ~EFX_INPLACE_MASK32(32, 63, field)) \ 472 & ~EFX_INPLACE_MASK32(32, 63, low, high)) \
468 | EFX_INSERT_FIELD32(32, 63, field, value)); \ 473 | EFX_INSERT32(32, 63, low, high, value)); \
469 } while (0) 474 } while (0)
470 475
471#define EFX_SET_DWORD_FIELD(dword, field, value) do { \ 476#define EFX_SET_DWORD32(dword, low, high, value) do { \
472 (dword).u32[0] = (((dword).u32[0] \ 477 (dword).u32[0] = (((dword).u32[0] \
473 & ~EFX_INPLACE_MASK32(0, 31, field)) \ 478 & ~EFX_INPLACE_MASK32(0, 31, low, high)) \
474 | EFX_INSERT_FIELD32(0, 31, field, value)); \ 479 | EFX_INSERT32(0, 31, low, high, value)); \
475 } while (0) 480 } while (0)
476 481
482#define EFX_SET_OWORD_FIELD64(oword, field, value) \
483 EFX_SET_OWORD64(oword, EFX_LOW_BIT(field), \
484 EFX_HIGH_BIT(field), value)
485
486#define EFX_SET_QWORD_FIELD64(qword, field, value) \
487 EFX_SET_QWORD64(qword, EFX_LOW_BIT(field), \
488 EFX_HIGH_BIT(field), value)
489
490#define EFX_SET_OWORD_FIELD32(oword, field, value) \
491 EFX_SET_OWORD32(oword, EFX_LOW_BIT(field), \
492 EFX_HIGH_BIT(field), value)
493
494#define EFX_SET_QWORD_FIELD32(qword, field, value) \
495 EFX_SET_QWORD32(qword, EFX_LOW_BIT(field), \
496 EFX_HIGH_BIT(field), value)
497
498#define EFX_SET_DWORD_FIELD(dword, field, value) \
499 EFX_SET_DWORD32(dword, EFX_LOW_BIT(field), \
500 EFX_HIGH_BIT(field), value)
501
502
503
477#if BITS_PER_LONG == 64 504#if BITS_PER_LONG == 64
478#define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD64 505#define EFX_SET_OWORD_FIELD EFX_SET_OWORD_FIELD64
479#define EFX_SET_QWORD_FIELD EFX_SET_QWORD_FIELD64 506#define EFX_SET_QWORD_FIELD EFX_SET_QWORD_FIELD64
diff --git a/drivers/net/sfc/falcon_hwdefs.h b/drivers/net/sfc/falcon_hwdefs.h
index 7c784f71f185..a3260dfb49a3 100644
--- a/drivers/net/sfc/falcon_hwdefs.h
+++ b/drivers/net/sfc/falcon_hwdefs.h
@@ -1147,8 +1147,8 @@ struct falcon_nvconfig_board_v3 {
1147#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5 1147#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
1148#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24 1148#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
1149#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5 1149#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
1150#define SPI_DEV_TYPE_FIELD(type, field) \ 1150#define SPI_DEV_TYPE_FIELD(type, field) \
1151 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(field)) 1151 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
1152 1152
1153#define NVCONFIG_BASE 0x300 1153#define NVCONFIG_BASE 0x300
1154#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C 1154#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C