diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2009-04-29 04:05:08 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-04-29 20:32:30 -0400 |
commit | 68e7f45e118f98b77cfa007aa2d97b5dac69fe6b (patch) | |
tree | d2e05579a0fc1f5a28bce8ff09ac6863d1907186 /drivers/net/sfc/tenxpress.c | |
parent | 1b1c2e95103ce391c2ea39a9460968fcb73deb30 (diff) |
sfc: Use generic MDIO functions and definitions
Make use of the newly-added generic MDIO clause 45 support and remove
redundant definitions.
Add an 'efx_' prefix to the remaining driver-specific MDIO functions
and remove arguments which are redundant with efx->mdio.prtad.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/tenxpress.c')
-rw-r--r-- | drivers/net/sfc/tenxpress.c | 227 |
1 files changed, 90 insertions, 137 deletions
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c index e61dc4d4741c..403f7d70c223 100644 --- a/drivers/net/sfc/tenxpress.c +++ b/drivers/net/sfc/tenxpress.c | |||
@@ -23,10 +23,10 @@ | |||
23 | * clause 22 extension MMD, but since it doesn't have all the generic | 23 | * clause 22 extension MMD, but since it doesn't have all the generic |
24 | * MMD registers it is pointless to include it here. | 24 | * MMD registers it is pointless to include it here. |
25 | */ | 25 | */ |
26 | #define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS_PMAPMD | \ | 26 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
27 | MDIO_MMDREG_DEVS_PCS | \ | 27 | MDIO_DEVS_PCS | \ |
28 | MDIO_MMDREG_DEVS_PHYXS | \ | 28 | MDIO_DEVS_PHYXS | \ |
29 | MDIO_MMDREG_DEVS_AN) | 29 | MDIO_DEVS_AN) |
30 | 30 | ||
31 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ | 31 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
32 | (1 << LOOPBACK_PCS) | \ | 32 | (1 << LOOPBACK_PCS) | \ |
@@ -153,10 +153,6 @@ | |||
153 | #define LOOPBACK_NEAR_LBN (8) | 153 | #define LOOPBACK_NEAR_LBN (8) |
154 | #define LOOPBACK_NEAR_WIDTH (1) | 154 | #define LOOPBACK_NEAR_WIDTH (1) |
155 | 155 | ||
156 | #define PCS_10GBASET_STAT1 32 | ||
157 | #define PCS_10GBASET_BLKLK_LBN 0 | ||
158 | #define PCS_10GBASET_BLKLK_WIDTH 1 | ||
159 | |||
160 | /* Boot status register */ | 156 | /* Boot status register */ |
161 | #define PCS_BOOT_STATUS_REG 53248 | 157 | #define PCS_BOOT_STATUS_REG 53248 |
162 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | 158 | #define PCS_BOOT_FATAL_ERROR_LBN 0 |
@@ -206,10 +202,8 @@ static ssize_t show_phy_short_reach(struct device *dev, | |||
206 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | 202 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
207 | int reg; | 203 | int reg; |
208 | 204 | ||
209 | reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | 205 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); |
210 | MDIO_PMAPMD_10GBT_TXPWR); | 206 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); |
211 | return sprintf(buf, "%d\n", | ||
212 | !!(reg & (1 << MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN))); | ||
213 | } | 207 | } |
214 | 208 | ||
215 | static ssize_t set_phy_short_reach(struct device *dev, | 209 | static ssize_t set_phy_short_reach(struct device *dev, |
@@ -219,10 +213,9 @@ static ssize_t set_phy_short_reach(struct device *dev, | |||
219 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | 213 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); |
220 | 214 | ||
221 | rtnl_lock(); | 215 | rtnl_lock(); |
222 | mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | 216 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, |
223 | MDIO_PMAPMD_10GBT_TXPWR, | 217 | MDIO_PMA_10GBT_TXPWR_SHORT, |
224 | MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN, | 218 | count != 0 && *buf != '0'); |
225 | count != 0 && *buf != '0'); | ||
226 | efx_reconfigure_port(efx); | 219 | efx_reconfigure_port(efx); |
227 | rtnl_unlock(); | 220 | rtnl_unlock(); |
228 | 221 | ||
@@ -238,9 +231,8 @@ int sft9001_wait_boot(struct efx_nic *efx) | |||
238 | int boot_stat; | 231 | int boot_stat; |
239 | 232 | ||
240 | for (;;) { | 233 | for (;;) { |
241 | boot_stat = mdio_clause45_read(efx, efx->mii.phy_id, | 234 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, |
242 | MDIO_MMD_PCS, | 235 | PCS_BOOT_STATUS_REG); |
243 | PCS_BOOT_STATUS_REG); | ||
244 | if (boot_stat >= 0) { | 236 | if (boot_stat >= 0) { |
245 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | 237 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); |
246 | switch (boot_stat & | 238 | switch (boot_stat & |
@@ -286,38 +278,32 @@ int sft9001_wait_boot(struct efx_nic *efx) | |||
286 | 278 | ||
287 | static int tenxpress_init(struct efx_nic *efx) | 279 | static int tenxpress_init(struct efx_nic *efx) |
288 | { | 280 | { |
289 | int phy_id = efx->mii.phy_id; | ||
290 | int reg; | 281 | int reg; |
291 | 282 | ||
292 | if (efx->phy_type == PHY_TYPE_SFX7101) { | 283 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
293 | /* Enable 312.5 MHz clock */ | 284 | /* Enable 312.5 MHz clock */ |
294 | mdio_clause45_write(efx, phy_id, | 285 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, |
295 | MDIO_MMD_PCS, PCS_TEST_SELECT_REG, | 286 | 1 << CLK312_EN_LBN); |
296 | 1 << CLK312_EN_LBN); | ||
297 | } else { | 287 | } else { |
298 | /* Enable 312.5 MHz clock and GMII */ | 288 | /* Enable 312.5 MHz clock and GMII */ |
299 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | 289 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
300 | PMA_PMD_XCONTROL_REG); | ||
301 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | | 290 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | |
302 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | 291 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | |
303 | (1 << PMA_PMD_EXT_CLK312_LBN) | | 292 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
304 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | 293 | (1 << PMA_PMD_EXT_ROBUST_LBN)); |
305 | 294 | ||
306 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | 295 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
307 | PMA_PMD_XCONTROL_REG, reg); | 296 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, |
308 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | 297 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, |
309 | GPHY_XCONTROL_REG, GPHY_ISOLATE_LBN, | 298 | false); |
310 | false); | ||
311 | } | 299 | } |
312 | 300 | ||
313 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ | 301 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
314 | if (efx->phy_type == PHY_TYPE_SFX7101) { | 302 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
315 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PMAPMD, | 303 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
316 | PMA_PMD_LED_CTRL_REG, | 304 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); |
317 | PMA_PMA_LED_ACTIVITY_LBN, | 305 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, |
318 | true); | 306 | PMA_PMD_LED_DEFAULT); |
319 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | ||
320 | PMA_PMD_LED_OVERR_REG, PMA_PMD_LED_DEFAULT); | ||
321 | } | 307 | } |
322 | 308 | ||
323 | return 0; | 309 | return 0; |
@@ -337,22 +323,19 @@ static int tenxpress_phy_init(struct efx_nic *efx) | |||
337 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { | 323 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
338 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | 324 | if (efx->phy_type == PHY_TYPE_SFT9001A) { |
339 | int reg; | 325 | int reg; |
340 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | 326 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
341 | MDIO_MMD_PMAPMD, | 327 | PMA_PMD_XCONTROL_REG); |
342 | PMA_PMD_XCONTROL_REG); | ||
343 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); | 328 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
344 | mdio_clause45_write(efx, efx->mii.phy_id, | 329 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
345 | MDIO_MMD_PMAPMD, | 330 | PMA_PMD_XCONTROL_REG, reg); |
346 | PMA_PMD_XCONTROL_REG, reg); | ||
347 | mdelay(200); | 331 | mdelay(200); |
348 | } | 332 | } |
349 | 333 | ||
350 | rc = mdio_clause45_wait_reset_mmds(efx, | 334 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
351 | TENXPRESS_REQUIRED_DEVS); | ||
352 | if (rc < 0) | 335 | if (rc < 0) |
353 | goto fail; | 336 | goto fail; |
354 | 337 | ||
355 | rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); | 338 | rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); |
356 | if (rc < 0) | 339 | if (rc < 0) |
357 | goto fail; | 340 | goto fail; |
358 | } | 341 | } |
@@ -360,7 +343,7 @@ static int tenxpress_phy_init(struct efx_nic *efx) | |||
360 | rc = tenxpress_init(efx); | 343 | rc = tenxpress_init(efx); |
361 | if (rc < 0) | 344 | if (rc < 0) |
362 | goto fail; | 345 | goto fail; |
363 | mdio_clause45_set_pause(efx); | 346 | efx_mdio_set_pause(efx); |
364 | 347 | ||
365 | if (efx->phy_type == PHY_TYPE_SFT9001B) { | 348 | if (efx->phy_type == PHY_TYPE_SFT9001B) { |
366 | rc = device_create_file(&efx->pci_dev->dev, | 349 | rc = device_create_file(&efx->pci_dev->dev, |
@@ -395,17 +378,14 @@ static int tenxpress_special_reset(struct efx_nic *efx) | |||
395 | efx_stats_disable(efx); | 378 | efx_stats_disable(efx); |
396 | 379 | ||
397 | /* Initiate reset */ | 380 | /* Initiate reset */ |
398 | reg = mdio_clause45_read(efx, efx->mii.phy_id, | 381 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
399 | MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); | ||
400 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); | 382 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
401 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | 383 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
402 | PMA_PMD_XCONTROL_REG, reg); | ||
403 | 384 | ||
404 | mdelay(200); | 385 | mdelay(200); |
405 | 386 | ||
406 | /* Wait for the blocks to come out of reset */ | 387 | /* Wait for the blocks to come out of reset */ |
407 | rc = mdio_clause45_wait_reset_mmds(efx, | 388 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
408 | TENXPRESS_REQUIRED_DEVS); | ||
409 | if (rc < 0) | 389 | if (rc < 0) |
410 | goto out; | 390 | goto out; |
411 | 391 | ||
@@ -424,7 +404,6 @@ out: | |||
424 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) | 404 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
425 | { | 405 | { |
426 | struct tenxpress_phy_data *pd = efx->phy_data; | 406 | struct tenxpress_phy_data *pd = efx->phy_data; |
427 | int phy_id = efx->mii.phy_id; | ||
428 | bool bad_lp; | 407 | bool bad_lp; |
429 | int reg; | 408 | int reg; |
430 | 409 | ||
@@ -432,11 +411,10 @@ static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) | |||
432 | bad_lp = false; | 411 | bad_lp = false; |
433 | } else { | 412 | } else { |
434 | /* Check that AN has started but not completed. */ | 413 | /* Check that AN has started but not completed. */ |
435 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, | 414 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); |
436 | MDIO_AN_STATUS); | 415 | if (!(reg & MDIO_AN_STAT1_LPABLE)) |
437 | if (!(reg & (1 << MDIO_AN_STATUS_LP_AN_CAP_LBN))) | ||
438 | return; /* LP status is unknown */ | 416 | return; /* LP status is unknown */ |
439 | bad_lp = !(reg & (1 << MDIO_AN_STATUS_AN_DONE_LBN)); | 417 | bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); |
440 | if (bad_lp) | 418 | if (bad_lp) |
441 | pd->bad_lp_tries++; | 419 | pd->bad_lp_tries++; |
442 | } | 420 | } |
@@ -448,8 +426,8 @@ static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) | |||
448 | /* Use the RX (red) LED as an error indicator once we've seen AN | 426 | /* Use the RX (red) LED as an error indicator once we've seen AN |
449 | * failure several times in a row, and also log a message. */ | 427 | * failure several times in a row, and also log a message. */ |
450 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | 428 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { |
451 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | 429 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
452 | PMA_PMD_LED_OVERR_REG); | 430 | PMA_PMD_LED_OVERR_REG); |
453 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); | 431 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); |
454 | if (!bad_lp) { | 432 | if (!bad_lp) { |
455 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | 433 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; |
@@ -460,23 +438,22 @@ static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) | |||
460 | " supports 10GBASE-T ONLY, so no link can" | 438 | " supports 10GBASE-T ONLY, so no link can" |
461 | " be established\n"); | 439 | " be established\n"); |
462 | } | 440 | } |
463 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | 441 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
464 | PMA_PMD_LED_OVERR_REG, reg); | 442 | PMA_PMD_LED_OVERR_REG, reg); |
465 | pd->bad_lp_tries = bad_lp; | 443 | pd->bad_lp_tries = bad_lp; |
466 | } | 444 | } |
467 | } | 445 | } |
468 | 446 | ||
469 | static bool sfx7101_link_ok(struct efx_nic *efx) | 447 | static bool sfx7101_link_ok(struct efx_nic *efx) |
470 | { | 448 | { |
471 | return mdio_clause45_links_ok(efx, | 449 | return efx_mdio_links_ok(efx, |
472 | MDIO_MMDREG_DEVS_PMAPMD | | 450 | MDIO_DEVS_PMAPMD | |
473 | MDIO_MMDREG_DEVS_PCS | | 451 | MDIO_DEVS_PCS | |
474 | MDIO_MMDREG_DEVS_PHYXS); | 452 | MDIO_DEVS_PHYXS); |
475 | } | 453 | } |
476 | 454 | ||
477 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | 455 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
478 | { | 456 | { |
479 | int phy_id = efx->mii.phy_id; | ||
480 | u32 reg; | 457 | u32 reg; |
481 | 458 | ||
482 | if (efx_phy_mode_disabled(efx->phy_mode)) | 459 | if (efx_phy_mode_disabled(efx->phy_mode)) |
@@ -484,50 +461,43 @@ static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |||
484 | else if (efx->loopback_mode == LOOPBACK_GPHY) | 461 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
485 | return true; | 462 | return true; |
486 | else if (efx->loopback_mode) | 463 | else if (efx->loopback_mode) |
487 | return mdio_clause45_links_ok(efx, | 464 | return efx_mdio_links_ok(efx, |
488 | MDIO_MMDREG_DEVS_PMAPMD | | 465 | MDIO_DEVS_PMAPMD | |
489 | MDIO_MMDREG_DEVS_PHYXS); | 466 | MDIO_DEVS_PHYXS); |
490 | 467 | ||
491 | /* We must use the same definition of link state as LASI, | 468 | /* We must use the same definition of link state as LASI, |
492 | * otherwise we can miss a link state transition | 469 | * otherwise we can miss a link state transition |
493 | */ | 470 | */ |
494 | if (ecmd->speed == 10000) { | 471 | if (ecmd->speed == 10000) { |
495 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_PCS, | 472 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
496 | PCS_10GBASET_STAT1); | 473 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; |
497 | return reg & (1 << PCS_10GBASET_BLKLK_LBN); | ||
498 | } else { | 474 | } else { |
499 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, | 475 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); |
500 | C22EXT_STATUS_REG); | ||
501 | return reg & (1 << C22EXT_STATUS_LINK_LBN); | 476 | return reg & (1 << C22EXT_STATUS_LINK_LBN); |
502 | } | 477 | } |
503 | } | 478 | } |
504 | 479 | ||
505 | static void tenxpress_ext_loopback(struct efx_nic *efx) | 480 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
506 | { | 481 | { |
507 | int phy_id = efx->mii.phy_id; | 482 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
508 | 483 | 1 << LOOPBACK_NEAR_LBN, | |
509 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_PHYXS, | 484 | efx->loopback_mode == LOOPBACK_PHYXS); |
510 | PHYXS_TEST1, LOOPBACK_NEAR_LBN, | ||
511 | efx->loopback_mode == LOOPBACK_PHYXS); | ||
512 | if (efx->phy_type != PHY_TYPE_SFX7101) | 485 | if (efx->phy_type != PHY_TYPE_SFX7101) |
513 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | 486 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, |
514 | GPHY_XCONTROL_REG, | 487 | 1 << GPHY_LOOPBACK_NEAR_LBN, |
515 | GPHY_LOOPBACK_NEAR_LBN, | 488 | efx->loopback_mode == LOOPBACK_GPHY); |
516 | efx->loopback_mode == LOOPBACK_GPHY); | ||
517 | } | 489 | } |
518 | 490 | ||
519 | static void tenxpress_low_power(struct efx_nic *efx) | 491 | static void tenxpress_low_power(struct efx_nic *efx) |
520 | { | 492 | { |
521 | int phy_id = efx->mii.phy_id; | ||
522 | |||
523 | if (efx->phy_type == PHY_TYPE_SFX7101) | 493 | if (efx->phy_type == PHY_TYPE_SFX7101) |
524 | mdio_clause45_set_mmds_lpower( | 494 | efx_mdio_set_mmds_lpower( |
525 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), | 495 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
526 | TENXPRESS_REQUIRED_DEVS); | 496 | TENXPRESS_REQUIRED_DEVS); |
527 | else | 497 | else |
528 | mdio_clause45_set_flag( | 498 | efx_mdio_set_flag( |
529 | efx, phy_id, MDIO_MMD_PMAPMD, | 499 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, |
530 | PMA_PMD_XCONTROL_REG, PMA_PMD_EXT_LPOWER_LBN, | 500 | 1 << PMA_PMD_EXT_LPOWER_LBN, |
531 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); | 501 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); |
532 | } | 502 | } |
533 | 503 | ||
@@ -568,8 +538,8 @@ static void tenxpress_phy_reconfigure(struct efx_nic *efx) | |||
568 | WARN_ON(rc); | 538 | WARN_ON(rc); |
569 | } | 539 | } |
570 | 540 | ||
571 | mdio_clause45_transmit_disable(efx); | 541 | efx_mdio_transmit_disable(efx); |
572 | mdio_clause45_phy_reconfigure(efx); | 542 | efx_mdio_phy_reconfigure(efx); |
573 | tenxpress_ext_loopback(efx); | 543 | tenxpress_ext_loopback(efx); |
574 | 544 | ||
575 | phy_data->loopback_mode = efx->loopback_mode; | 545 | phy_data->loopback_mode = efx->loopback_mode; |
@@ -585,7 +555,7 @@ static void tenxpress_phy_reconfigure(struct efx_nic *efx) | |||
585 | efx->link_fd = ecmd.duplex == DUPLEX_FULL; | 555 | efx->link_fd = ecmd.duplex == DUPLEX_FULL; |
586 | efx->link_up = sft9001_link_ok(efx, &ecmd); | 556 | efx->link_up = sft9001_link_ok(efx, &ecmd); |
587 | } | 557 | } |
588 | efx->link_fc = mdio_clause45_get_pause(efx); | 558 | efx->link_fc = efx_mdio_get_pause(efx); |
589 | } | 559 | } |
590 | 560 | ||
591 | /* Poll PHY for interrupt */ | 561 | /* Poll PHY for interrupt */ |
@@ -599,7 +569,7 @@ static void tenxpress_phy_poll(struct efx_nic *efx) | |||
599 | if (link_ok != efx->link_up) { | 569 | if (link_ok != efx->link_up) { |
600 | change = true; | 570 | change = true; |
601 | } else { | 571 | } else { |
602 | unsigned int link_fc = mdio_clause45_get_pause(efx); | 572 | unsigned int link_fc = efx_mdio_get_pause(efx); |
603 | if (link_fc != efx->link_fc) | 573 | if (link_fc != efx->link_fc) |
604 | change = true; | 574 | change = true; |
605 | } | 575 | } |
@@ -609,9 +579,8 @@ static void tenxpress_phy_poll(struct efx_nic *efx) | |||
609 | if (link_ok != efx->link_up) | 579 | if (link_ok != efx->link_up) |
610 | change = true; | 580 | change = true; |
611 | } else { | 581 | } else { |
612 | u32 status = mdio_clause45_read(efx, efx->mii.phy_id, | 582 | int status = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
613 | MDIO_MMD_PMAPMD, | 583 | PMA_PMD_LASI_STATUS); |
614 | PMA_PMD_LASI_STATUS); | ||
615 | if (status & (1 << PMA_PMD_LS_ALARM_LBN)) | 584 | if (status & (1 << PMA_PMD_LS_ALARM_LBN)) |
616 | change = true; | 585 | change = true; |
617 | } | 586 | } |
@@ -634,8 +603,7 @@ static void tenxpress_phy_fini(struct efx_nic *efx) | |||
634 | if (efx->phy_type == PHY_TYPE_SFX7101) { | 603 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
635 | /* Power down the LNPGA */ | 604 | /* Power down the LNPGA */ |
636 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | 605 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); |
637 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | 606 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
638 | PMA_PMD_XCONTROL_REG, reg); | ||
639 | 607 | ||
640 | /* Waiting here ensures that the board fini, which can turn | 608 | /* Waiting here ensures that the board fini, which can turn |
641 | * off the power to the PHY, won't get run until the LNPGA | 609 | * off the power to the PHY, won't get run until the LNPGA |
@@ -661,8 +629,7 @@ void tenxpress_phy_blink(struct efx_nic *efx, bool blink) | |||
661 | else | 629 | else |
662 | reg = PMA_PMD_LED_DEFAULT; | 630 | reg = PMA_PMD_LED_DEFAULT; |
663 | 631 | ||
664 | mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | 632 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); |
665 | PMA_PMD_LED_OVERR_REG, reg); | ||
666 | } | 633 | } |
667 | 634 | ||
668 | static const char *const sfx7101_test_names[] = { | 635 | static const char *const sfx7101_test_names[] = { |
@@ -698,7 +665,6 @@ static const char *const sft9001_test_names[] = { | |||
698 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | 665 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
699 | { | 666 | { |
700 | struct ethtool_cmd ecmd; | 667 | struct ethtool_cmd ecmd; |
701 | int phy_id = efx->mii.phy_id; | ||
702 | int rc = 0, rc2, i, ctrl_reg, res_reg; | 668 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
703 | 669 | ||
704 | if (flags & ETH_TEST_FL_OFFLINE) | 670 | if (flags & ETH_TEST_FL_OFFLINE) |
@@ -717,11 +683,10 @@ static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |||
717 | * must reset the PHY to resume normal service. */ | 683 | * must reset the PHY to resume normal service. */ |
718 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | 684 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); |
719 | } | 685 | } |
720 | mdio_clause45_write(efx, phy_id, MDIO_MMD_PMAPMD, | 686 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, |
721 | PMA_PMD_CDIAG_CTRL_REG, ctrl_reg); | 687 | ctrl_reg); |
722 | i = 0; | 688 | i = 0; |
723 | while (mdio_clause45_read(efx, phy_id, MDIO_MMD_PMAPMD, | 689 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & |
724 | PMA_PMD_CDIAG_CTRL_REG) & | ||
725 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { | 690 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { |
726 | if (++i == 50) { | 691 | if (++i == 50) { |
727 | rc = -ETIMEDOUT; | 692 | rc = -ETIMEDOUT; |
@@ -729,15 +694,13 @@ static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) | |||
729 | } | 694 | } |
730 | msleep(100); | 695 | msleep(100); |
731 | } | 696 | } |
732 | res_reg = mdio_clause45_read(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD, | 697 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); |
733 | PMA_PMD_CDIAG_RES_REG); | ||
734 | for (i = 0; i < 4; i++) { | 698 | for (i = 0; i < 4; i++) { |
735 | int pair_res = | 699 | int pair_res = |
736 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | 700 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) |
737 | & ((1 << CDIAG_RES_WIDTH) - 1); | 701 | & ((1 << CDIAG_RES_WIDTH) - 1); |
738 | int len_reg = mdio_clause45_read(efx, efx->mii.phy_id, | 702 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
739 | MDIO_MMD_PMAPMD, | 703 | PMA_PMD_CDIAG_LEN_REG + i); |
740 | PMA_PMD_CDIAG_LEN_REG + i); | ||
741 | if (pair_res == CDIAG_RES_OK) | 704 | if (pair_res == CDIAG_RES_OK) |
742 | results[1 + i] = 1; | 705 | results[1 + i] = 1; |
743 | else if (pair_res == CDIAG_RES_INVALID) | 706 | else if (pair_res == CDIAG_RES_INVALID) |
@@ -769,32 +732,27 @@ out: | |||
769 | static void | 732 | static void |
770 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | 733 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
771 | { | 734 | { |
772 | int phy_id = efx->mii.phy_id; | ||
773 | u32 adv = 0, lpa = 0; | 735 | u32 adv = 0, lpa = 0; |
774 | int reg; | 736 | int reg; |
775 | 737 | ||
776 | if (efx->phy_type != PHY_TYPE_SFX7101) { | 738 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
777 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, | 739 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); |
778 | C22EXT_MSTSLV_CTRL); | ||
779 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) | 740 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) |
780 | adv |= ADVERTISED_1000baseT_Full; | 741 | adv |= ADVERTISED_1000baseT_Full; |
781 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_C22EXT, | 742 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); |
782 | C22EXT_MSTSLV_STATUS); | ||
783 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) | 743 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) |
784 | lpa |= ADVERTISED_1000baseT_Half; | 744 | lpa |= ADVERTISED_1000baseT_Half; |
785 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) | 745 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
786 | lpa |= ADVERTISED_1000baseT_Full; | 746 | lpa |= ADVERTISED_1000baseT_Full; |
787 | } | 747 | } |
788 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, | 748 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
789 | MDIO_AN_10GBT_CTRL); | 749 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) |
790 | if (reg & (1 << MDIO_AN_10GBT_CTRL_ADV_10G_LBN)) | ||
791 | adv |= ADVERTISED_10000baseT_Full; | 750 | adv |= ADVERTISED_10000baseT_Full; |
792 | reg = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN, | 751 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); |
793 | MDIO_AN_10GBT_STATUS); | 752 | if (reg & MDIO_AN_10GBT_STAT_LP10G) |
794 | if (reg & (1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN)) | ||
795 | lpa |= ADVERTISED_10000baseT_Full; | 753 | lpa |= ADVERTISED_10000baseT_Full; |
796 | 754 | ||
797 | mdio_clause45_get_settings_ext(efx, ecmd, adv, lpa); | 755 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
798 | 756 | ||
799 | if (efx->phy_type != PHY_TYPE_SFX7101) | 757 | if (efx->phy_type != PHY_TYPE_SFX7101) |
800 | ecmd->supported |= (SUPPORTED_100baseT_Full | | 758 | ecmd->supported |= (SUPPORTED_100baseT_Full | |
@@ -813,29 +771,24 @@ static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |||
813 | if (!ecmd->autoneg) | 771 | if (!ecmd->autoneg) |
814 | return -EINVAL; | 772 | return -EINVAL; |
815 | 773 | ||
816 | return mdio_clause45_set_settings(efx, ecmd); | 774 | return efx_mdio_set_settings(efx, ecmd); |
817 | } | 775 | } |
818 | 776 | ||
819 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) | 777 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
820 | { | 778 | { |
821 | mdio_clause45_set_flag(efx, efx->mii.phy_id, MDIO_MMD_AN, | 779 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
822 | MDIO_AN_10GBT_CTRL, | 780 | MDIO_AN_10GBT_CTRL_ADV10G, |
823 | MDIO_AN_10GBT_CTRL_ADV_10G_LBN, | 781 | advertising & ADVERTISED_10000baseT_Full); |
824 | advertising & ADVERTISED_10000baseT_Full); | ||
825 | } | 782 | } |
826 | 783 | ||
827 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) | 784 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
828 | { | 785 | { |
829 | int phy_id = efx->mii.phy_id; | 786 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, |
830 | 787 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
831 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_C22EXT, | 788 | advertising & ADVERTISED_1000baseT_Full); |
832 | C22EXT_MSTSLV_CTRL, | 789 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
833 | C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | 790 | MDIO_AN_10GBT_CTRL_ADV10G, |
834 | advertising & ADVERTISED_1000baseT_Full); | 791 | advertising & ADVERTISED_10000baseT_Full); |
835 | mdio_clause45_set_flag(efx, phy_id, MDIO_MMD_AN, | ||
836 | MDIO_AN_10GBT_CTRL, | ||
837 | MDIO_AN_10GBT_CTRL_ADV_10G_LBN, | ||
838 | advertising & ADVERTISED_10000baseT_Full); | ||
839 | } | 792 | } |
840 | 793 | ||
841 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | 794 | struct efx_phy_operations falcon_sfx7101_phy_ops = { |