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authorBen Hutchings <bhutchings@solarflare.com>2008-09-01 07:49:20 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-09-24 18:54:35 -0400
commitef08af03ef85373901a2ca0241617e6e7e42685d (patch)
treeeb89fcfb1a05422e091762477bfd737093c7cd25 /drivers/net/sfc/tenxpress.c
parente1074a0d966ac372bb0abd5eee926a0b57316582 (diff)
sfc: Remove workaround for old firmware bug
There was a bug in XAUI synchronisation in early 10Xpress firmware versions. This is fixed in released firmware and we do not need to work around it. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/sfc/tenxpress.c')
-rw-r--r--drivers/net/sfc/tenxpress.c51
1 files changed, 0 insertions, 51 deletions
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c
index 8412dbe1e8fb..77e7f3a94b25 100644
--- a/drivers/net/sfc/tenxpress.c
+++ b/drivers/net/sfc/tenxpress.c
@@ -146,8 +146,6 @@ static int tenxpress_phy_check(struct efx_nic *efx)
146 return 0; 146 return 0;
147} 147}
148 148
149static void tenxpress_reset_xaui(struct efx_nic *efx);
150
151static int tenxpress_init(struct efx_nic *efx) 149static int tenxpress_init(struct efx_nic *efx)
152{ 150{
153 int rc, reg; 151 int rc, reg;
@@ -428,54 +426,6 @@ void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
428 PMA_PMD_LED_OVERR_REG, reg); 426 PMA_PMD_LED_OVERR_REG, reg);
429} 427}
430 428
431static void tenxpress_reset_xaui(struct efx_nic *efx)
432{
433 int phy = efx->mii.phy_id;
434 int clk_ctrl, test_select, soft_rst2;
435
436 /* Real work is done on clock_ctrl other resets are thought to be
437 * optional but make the reset more reliable
438 */
439
440 /* Read */
441 clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
442 PCS_CLOCK_CTRL_REG);
443 test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
444 PCS_TEST_SELECT_REG);
445 soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS,
446 PCS_SOFT_RST2_REG);
447
448 /* Put in reset */
449 test_select &= ~(1 << CLK312_EN_LBN);
450 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
451 PCS_TEST_SELECT_REG, test_select);
452
453 soft_rst2 &= ~((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
454 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
455 PCS_SOFT_RST2_REG, soft_rst2);
456
457 clk_ctrl &= ~(1 << PLL312_RST_N_LBN);
458 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
459 PCS_CLOCK_CTRL_REG, clk_ctrl);
460 udelay(10);
461
462 /* Remove reset */
463 clk_ctrl |= (1 << PLL312_RST_N_LBN);
464 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
465 PCS_CLOCK_CTRL_REG, clk_ctrl);
466 udelay(10);
467
468 soft_rst2 |= ((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN));
469 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
470 PCS_SOFT_RST2_REG, soft_rst2);
471 udelay(10);
472
473 test_select |= (1 << CLK312_EN_LBN);
474 mdio_clause45_write(efx, phy, MDIO_MMD_PCS,
475 PCS_TEST_SELECT_REG, test_select);
476 udelay(10);
477}
478
479static int tenxpress_phy_test(struct efx_nic *efx) 429static int tenxpress_phy_test(struct efx_nic *efx)
480{ 430{
481 /* BIST is automatically run after a special software reset */ 431 /* BIST is automatically run after a special software reset */
@@ -488,7 +438,6 @@ struct efx_phy_operations falcon_tenxpress_phy_ops = {
488 .check_hw = tenxpress_phy_check_hw, 438 .check_hw = tenxpress_phy_check_hw,
489 .fini = tenxpress_phy_fini, 439 .fini = tenxpress_phy_fini,
490 .clear_interrupt = tenxpress_phy_clear_interrupt, 440 .clear_interrupt = tenxpress_phy_clear_interrupt,
491 .reset_xaui = tenxpress_reset_xaui,
492 .test = tenxpress_phy_test, 441 .test = tenxpress_phy_test,
493 .mmds = TENXPRESS_REQUIRED_DEVS, 442 .mmds = TENXPRESS_REQUIRED_DEVS,
494 .loopbacks = TENXPRESS_LOOPBACKS, 443 .loopbacks = TENXPRESS_LOOPBACKS,