diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2008-09-01 07:49:02 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-09-03 09:53:48 -0400 |
commit | 8c8661e4cefdd1ddbfe7d5120f046694555d9e5c (patch) | |
tree | 0618e0392140bccadf012381e64a795dfe2e41a4 /drivers/net/sfc/tenxpress.c | |
parent | a515089c963b045f65c495cee1d344d8cb75e1d1 (diff) |
sfc: Extend self-tests
Include PMA/PMD in loopback self-tests as intended.
Add NVRAM checksum validation and include it in self-tests.
Add register self-tests.
Run PHY self-tests where available.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/sfc/tenxpress.c')
-rw-r--r-- | drivers/net/sfc/tenxpress.c | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c index 499e127f6dd5..8412dbe1e8fb 100644 --- a/drivers/net/sfc/tenxpress.c +++ b/drivers/net/sfc/tenxpress.c | |||
@@ -65,25 +65,10 @@ | |||
65 | #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | 65 | #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
66 | 66 | ||
67 | 67 | ||
68 | /* Self test (BIST) control register */ | ||
69 | #define PMA_PMD_BIST_CTRL_REG (0xc014) | ||
70 | #define PMA_PMD_BIST_BER_LBN (2) /* Run BER test */ | ||
71 | #define PMA_PMD_BIST_CONT_LBN (1) /* Run continuous BIST until cleared */ | ||
72 | #define PMA_PMD_BIST_SINGLE_LBN (0) /* Run 1 BIST iteration (self clears) */ | ||
73 | /* Self test status register */ | ||
74 | #define PMA_PMD_BIST_STAT_REG (0xc015) | ||
75 | #define PMA_PMD_BIST_ENX_LBN (3) | ||
76 | #define PMA_PMD_BIST_PMA_LBN (2) | ||
77 | #define PMA_PMD_BIST_RXD_LBN (1) | ||
78 | #define PMA_PMD_BIST_AFE_LBN (0) | ||
79 | |||
80 | /* Special Software reset register */ | 68 | /* Special Software reset register */ |
81 | #define PMA_PMD_EXT_CTRL_REG 49152 | 69 | #define PMA_PMD_EXT_CTRL_REG 49152 |
82 | #define PMA_PMD_EXT_SSR_LBN 15 | 70 | #define PMA_PMD_EXT_SSR_LBN 15 |
83 | 71 | ||
84 | #define BIST_MAX_DELAY (1000) | ||
85 | #define BIST_POLL_DELAY (10) | ||
86 | |||
87 | /* Misc register defines */ | 72 | /* Misc register defines */ |
88 | #define PCS_CLOCK_CTRL_REG 0xd801 | 73 | #define PCS_CLOCK_CTRL_REG 0xd801 |
89 | #define PLL312_RST_N_LBN 2 | 74 | #define PLL312_RST_N_LBN 2 |
@@ -491,6 +476,12 @@ static void tenxpress_reset_xaui(struct efx_nic *efx) | |||
491 | udelay(10); | 476 | udelay(10); |
492 | } | 477 | } |
493 | 478 | ||
479 | static int tenxpress_phy_test(struct efx_nic *efx) | ||
480 | { | ||
481 | /* BIST is automatically run after a special software reset */ | ||
482 | return tenxpress_special_reset(efx); | ||
483 | } | ||
484 | |||
494 | struct efx_phy_operations falcon_tenxpress_phy_ops = { | 485 | struct efx_phy_operations falcon_tenxpress_phy_ops = { |
495 | .init = tenxpress_phy_init, | 486 | .init = tenxpress_phy_init, |
496 | .reconfigure = tenxpress_phy_reconfigure, | 487 | .reconfigure = tenxpress_phy_reconfigure, |
@@ -498,6 +489,7 @@ struct efx_phy_operations falcon_tenxpress_phy_ops = { | |||
498 | .fini = tenxpress_phy_fini, | 489 | .fini = tenxpress_phy_fini, |
499 | .clear_interrupt = tenxpress_phy_clear_interrupt, | 490 | .clear_interrupt = tenxpress_phy_clear_interrupt, |
500 | .reset_xaui = tenxpress_reset_xaui, | 491 | .reset_xaui = tenxpress_reset_xaui, |
492 | .test = tenxpress_phy_test, | ||
501 | .mmds = TENXPRESS_REQUIRED_DEVS, | 493 | .mmds = TENXPRESS_REQUIRED_DEVS, |
502 | .loopbacks = TENXPRESS_LOOPBACKS, | 494 | .loopbacks = TENXPRESS_LOOPBACKS, |
503 | }; | 495 | }; |