diff options
| author | Ben Hutchings <bhutchings@solarflare.com> | 2011-06-24 15:50:07 -0400 |
|---|---|---|
| committer | Ben Hutchings <bhutchings@solarflare.com> | 2011-06-24 19:43:48 -0400 |
| commit | 0e2a9c7cb941db993f481cdd6a99d70a302053e0 (patch) | |
| tree | 1b71555f2b37dfcc10d7471c96a3de56293a1f84 /drivers/net/sfc/siena.c | |
| parent | a7d529ae2158b5300e4aa16c21f1828bc864449b (diff) | |
sfc: Fix mapping of reset reasons and flags to methods
There are certain hardware bugs that may occur on Falcon during normal
operation, that require a reset to recover from. We try to minimise
disruption by keeping the PHY running, following a reset sequence
labelled as 'invisible'.
Siena does not suffer from these hardware bugs, so we have not
implemented an 'invisible' reset sequence. However, if a similar
error does occur (due to a hardware fault or software bug) then the
code shared with Falcon will wrongly assume that the PHY is not being
reset.
Since the mapping of reset reasons (internal) and flags (ethtool) to
methods must differ significantly between NIC types, move it into
per-NIC-type functions (replacing the insufficient reset_world_flags
field).
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat (limited to 'drivers/net/sfc/siena.c')
| -rw-r--r-- | drivers/net/sfc/siena.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/drivers/net/sfc/siena.c b/drivers/net/sfc/siena.c index a66818ed4011..442897b14270 100644 --- a/drivers/net/sfc/siena.c +++ b/drivers/net/sfc/siena.c | |||
| @@ -177,6 +177,36 @@ static int siena_test_registers(struct efx_nic *efx) | |||
| 177 | ************************************************************************** | 177 | ************************************************************************** |
| 178 | */ | 178 | */ |
| 179 | 179 | ||
| 180 | static enum reset_type siena_map_reset_reason(enum reset_type reason) | ||
| 181 | { | ||
| 182 | return RESET_TYPE_ALL; | ||
| 183 | } | ||
| 184 | |||
| 185 | static int siena_map_reset_flags(u32 *flags) | ||
| 186 | { | ||
| 187 | enum { | ||
| 188 | SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER | | ||
| 189 | ETH_RESET_OFFLOAD | ETH_RESET_MAC | | ||
| 190 | ETH_RESET_PHY), | ||
| 191 | SIENA_RESET_MC = (SIENA_RESET_PORT | | ||
| 192 | ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT), | ||
| 193 | }; | ||
| 194 | |||
| 195 | if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) { | ||
| 196 | *flags &= ~SIENA_RESET_MC; | ||
| 197 | return RESET_TYPE_WORLD; | ||
| 198 | } | ||
| 199 | |||
| 200 | if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) { | ||
| 201 | *flags &= ~SIENA_RESET_PORT; | ||
| 202 | return RESET_TYPE_ALL; | ||
| 203 | } | ||
| 204 | |||
| 205 | /* no invisible reset implemented */ | ||
| 206 | |||
| 207 | return -EINVAL; | ||
| 208 | } | ||
| 209 | |||
| 180 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method) | 210 | static int siena_reset_hw(struct efx_nic *efx, enum reset_type method) |
| 181 | { | 211 | { |
| 182 | int rc; | 212 | int rc; |
| @@ -605,6 +635,8 @@ const struct efx_nic_type siena_a0_nic_type = { | |||
| 605 | .init = siena_init_nic, | 635 | .init = siena_init_nic, |
| 606 | .fini = efx_port_dummy_op_void, | 636 | .fini = efx_port_dummy_op_void, |
| 607 | .monitor = NULL, | 637 | .monitor = NULL, |
| 638 | .map_reset_reason = siena_map_reset_reason, | ||
| 639 | .map_reset_flags = siena_map_reset_flags, | ||
| 608 | .reset = siena_reset_hw, | 640 | .reset = siena_reset_hw, |
| 609 | .probe_port = siena_probe_port, | 641 | .probe_port = siena_probe_port, |
| 610 | .remove_port = siena_remove_port, | 642 | .remove_port = siena_remove_port, |
| @@ -641,5 +673,4 @@ const struct efx_nic_type siena_a0_nic_type = { | |||
| 641 | .rx_dc_base = 0x68000, | 673 | .rx_dc_base = 0x68000, |
| 642 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | | 674 | .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | |
| 643 | NETIF_F_RXHASH | NETIF_F_NTUPLE), | 675 | NETIF_F_RXHASH | NETIF_F_NTUPLE), |
| 644 | .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT, | ||
| 645 | }; | 676 | }; |