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authorBen Hutchings <bhutchings@solarflare.com>2010-06-23 07:31:28 -0400
committerDavid S. Miller <davem@davemloft.net>2010-06-25 01:13:24 -0400
commit39c9cf07077146b14ab077a0e27c869c6f0e6199 (patch)
treee30b746b36ebb36af8776658e8ce3f8bcd4e118d /drivers/net/sfc/siena.c
parent2822235278c6385191a590c63098e728d0062987 (diff)
sfc: Record hardware RX hash on each skb where possible
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/siena.c')
-rw-r--r--drivers/net/sfc/siena.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/net/sfc/siena.c b/drivers/net/sfc/siena.c
index 59d1dc6db1c6..f1741b4af1b3 100644
--- a/drivers/net/sfc/siena.c
+++ b/drivers/net/sfc/siena.c
@@ -331,6 +331,7 @@ static int siena_init_nic(struct efx_nic *efx)
331 331
332 efx_reado(efx, &temp, FR_AZ_RX_CFG); 332 efx_reado(efx, &temp, FR_AZ_RX_CFG);
333 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0); 333 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
334 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
334 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1); 335 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
335 efx_writeo(efx, &temp, FR_AZ_RX_CFG); 336 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
336 337
@@ -636,6 +637,7 @@ struct efx_nic_type siena_a0_nic_type = {
636 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, 637 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
637 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, 638 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
638 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), 639 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
640 .rx_buffer_hash_size = 0x10,
639 .rx_buffer_padding = 0, 641 .rx_buffer_padding = 0,
640 .max_interrupt_mode = EFX_INT_MODE_MSIX, 642 .max_interrupt_mode = EFX_INT_MODE_MSIX,
641 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy 643 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
@@ -643,6 +645,7 @@ struct efx_nic_type siena_a0_nic_type = {
643 * channels */ 645 * channels */
644 .tx_dc_base = 0x88000, 646 .tx_dc_base = 0x88000,
645 .rx_dc_base = 0x68000, 647 .rx_dc_base = 0x68000,
646 .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM, 648 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
649 NETIF_F_RXHASH),
647 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT, 650 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
648}; 651};