diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2008-04-27 07:55:59 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-04-29 01:42:43 -0400 |
commit | 8ceee660aacb29721e26f08e336c58dc4847d1bd (patch) | |
tree | 158122642e6f21fe85d072c50d6185a0d0cf6834 /drivers/net/sfc/sfe4001.c | |
parent | 358c12953b88c5a06a57c33eb27c753b2e7934d1 (diff) |
New driver "sfc" for Solarstorm SFC4000 controller.
The driver supports the 10Xpress PHY and XFP modules on our reference
designs SFE4001 and SFE4002 and the SMC models SMC10GPCIe-XFP and
SMC10GPCIe-10BT.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/sfc/sfe4001.c')
-rw-r--r-- | drivers/net/sfc/sfe4001.c | 252 |
1 files changed, 252 insertions, 0 deletions
diff --git a/drivers/net/sfc/sfe4001.c b/drivers/net/sfc/sfe4001.c new file mode 100644 index 000000000000..11fa9fb8f48b --- /dev/null +++ b/drivers/net/sfc/sfe4001.c | |||
@@ -0,0 +1,252 @@ | |||
1 | /**************************************************************************** | ||
2 | * Driver for Solarflare Solarstorm network controllers and boards | ||
3 | * Copyright 2007 Solarflare Communications Inc. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms of the GNU General Public License version 2 as published | ||
7 | * by the Free Software Foundation, incorporated herein by reference. | ||
8 | */ | ||
9 | |||
10 | /***************************************************************************** | ||
11 | * Support for the SFE4001 NIC: driver code for the PCA9539 I/O expander that | ||
12 | * controls the PHY power rails, and for the MAX6647 temp. sensor used to check | ||
13 | * the PHY | ||
14 | */ | ||
15 | #include <linux/delay.h> | ||
16 | #include "efx.h" | ||
17 | #include "phy.h" | ||
18 | #include "boards.h" | ||
19 | #include "falcon.h" | ||
20 | #include "falcon_hwdefs.h" | ||
21 | #include "mac.h" | ||
22 | |||
23 | /************************************************************************** | ||
24 | * | ||
25 | * I2C IO Expander device | ||
26 | * | ||
27 | **************************************************************************/ | ||
28 | #define PCA9539 0x74 | ||
29 | |||
30 | #define P0_IN 0x00 | ||
31 | #define P0_OUT 0x02 | ||
32 | #define P0_INVERT 0x04 | ||
33 | #define P0_CONFIG 0x06 | ||
34 | |||
35 | #define P0_EN_1V0X_LBN 0 | ||
36 | #define P0_EN_1V0X_WIDTH 1 | ||
37 | #define P0_EN_1V2_LBN 1 | ||
38 | #define P0_EN_1V2_WIDTH 1 | ||
39 | #define P0_EN_2V5_LBN 2 | ||
40 | #define P0_EN_2V5_WIDTH 1 | ||
41 | #define P0_EN_3V3X_LBN 3 | ||
42 | #define P0_EN_3V3X_WIDTH 1 | ||
43 | #define P0_EN_5V_LBN 4 | ||
44 | #define P0_EN_5V_WIDTH 1 | ||
45 | #define P0_SHORTEN_JTAG_LBN 5 | ||
46 | #define P0_SHORTEN_JTAG_WIDTH 1 | ||
47 | #define P0_X_TRST_LBN 6 | ||
48 | #define P0_X_TRST_WIDTH 1 | ||
49 | #define P0_DSP_RESET_LBN 7 | ||
50 | #define P0_DSP_RESET_WIDTH 1 | ||
51 | |||
52 | #define P1_IN 0x01 | ||
53 | #define P1_OUT 0x03 | ||
54 | #define P1_INVERT 0x05 | ||
55 | #define P1_CONFIG 0x07 | ||
56 | |||
57 | #define P1_AFE_PWD_LBN 0 | ||
58 | #define P1_AFE_PWD_WIDTH 1 | ||
59 | #define P1_DSP_PWD25_LBN 1 | ||
60 | #define P1_DSP_PWD25_WIDTH 1 | ||
61 | #define P1_RESERVED_LBN 2 | ||
62 | #define P1_RESERVED_WIDTH 2 | ||
63 | #define P1_SPARE_LBN 4 | ||
64 | #define P1_SPARE_WIDTH 4 | ||
65 | |||
66 | |||
67 | /************************************************************************** | ||
68 | * | ||
69 | * Temperature Sensor | ||
70 | * | ||
71 | **************************************************************************/ | ||
72 | #define MAX6647 0x4e | ||
73 | |||
74 | #define RLTS 0x00 | ||
75 | #define RLTE 0x01 | ||
76 | #define RSL 0x02 | ||
77 | #define RCL 0x03 | ||
78 | #define RCRA 0x04 | ||
79 | #define RLHN 0x05 | ||
80 | #define RLLI 0x06 | ||
81 | #define RRHI 0x07 | ||
82 | #define RRLS 0x08 | ||
83 | #define WCRW 0x0a | ||
84 | #define WLHO 0x0b | ||
85 | #define WRHA 0x0c | ||
86 | #define WRLN 0x0e | ||
87 | #define OSHT 0x0f | ||
88 | #define REET 0x10 | ||
89 | #define RIET 0x11 | ||
90 | #define RWOE 0x19 | ||
91 | #define RWOI 0x20 | ||
92 | #define HYS 0x21 | ||
93 | #define QUEUE 0x22 | ||
94 | #define MFID 0xfe | ||
95 | #define REVID 0xff | ||
96 | |||
97 | /* Status bits */ | ||
98 | #define MAX6647_BUSY (1 << 7) /* ADC is converting */ | ||
99 | #define MAX6647_LHIGH (1 << 6) /* Local high temp. alarm */ | ||
100 | #define MAX6647_LLOW (1 << 5) /* Local low temp. alarm */ | ||
101 | #define MAX6647_RHIGH (1 << 4) /* Remote high temp. alarm */ | ||
102 | #define MAX6647_RLOW (1 << 3) /* Remote low temp. alarm */ | ||
103 | #define MAX6647_FAULT (1 << 2) /* DXN/DXP short/open circuit */ | ||
104 | #define MAX6647_EOT (1 << 1) /* Remote junction overtemp. */ | ||
105 | #define MAX6647_IOT (1 << 0) /* Local junction overtemp. */ | ||
106 | |||
107 | static const u8 xgphy_max_temperature = 90; | ||
108 | |||
109 | void sfe4001_poweroff(struct efx_nic *efx) | ||
110 | { | ||
111 | struct efx_i2c_interface *i2c = &efx->i2c; | ||
112 | |||
113 | u8 cfg, out, in; | ||
114 | |||
115 | EFX_INFO(efx, "%s\n", __func__); | ||
116 | |||
117 | /* Turn off all power rails */ | ||
118 | out = 0xff; | ||
119 | (void) efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); | ||
120 | |||
121 | /* Disable port 1 outputs on IO expander */ | ||
122 | cfg = 0xff; | ||
123 | (void) efx_i2c_write(i2c, PCA9539, P1_CONFIG, &cfg, 1); | ||
124 | |||
125 | /* Disable port 0 outputs on IO expander */ | ||
126 | cfg = 0xff; | ||
127 | (void) efx_i2c_write(i2c, PCA9539, P0_CONFIG, &cfg, 1); | ||
128 | |||
129 | /* Clear any over-temperature alert */ | ||
130 | (void) efx_i2c_read(i2c, MAX6647, RSL, &in, 1); | ||
131 | } | ||
132 | |||
133 | /* This board uses an I2C expander to provider power to the PHY, which needs to | ||
134 | * be turned on before the PHY can be used. | ||
135 | * Context: Process context, rtnl lock held | ||
136 | */ | ||
137 | int sfe4001_poweron(struct efx_nic *efx) | ||
138 | { | ||
139 | struct efx_i2c_interface *i2c = &efx->i2c; | ||
140 | unsigned int count; | ||
141 | int rc; | ||
142 | u8 out, in, cfg; | ||
143 | efx_dword_t reg; | ||
144 | |||
145 | /* 10Xpress has fixed-function LED pins, so there is no board-specific | ||
146 | * blink code. */ | ||
147 | efx->board_info.blink = tenxpress_phy_blink; | ||
148 | |||
149 | /* Ensure that XGXS and XAUI SerDes are held in reset */ | ||
150 | EFX_POPULATE_DWORD_7(reg, XX_PWRDNA_EN, 1, | ||
151 | XX_PWRDNB_EN, 1, | ||
152 | XX_RSTPLLAB_EN, 1, | ||
153 | XX_RESETA_EN, 1, | ||
154 | XX_RESETB_EN, 1, | ||
155 | XX_RSTXGXSRX_EN, 1, | ||
156 | XX_RSTXGXSTX_EN, 1); | ||
157 | falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC); | ||
158 | udelay(10); | ||
159 | |||
160 | /* Set DSP over-temperature alert threshold */ | ||
161 | EFX_INFO(efx, "DSP cut-out at %dC\n", xgphy_max_temperature); | ||
162 | rc = efx_i2c_write(i2c, MAX6647, WLHO, | ||
163 | &xgphy_max_temperature, 1); | ||
164 | if (rc) | ||
165 | goto fail1; | ||
166 | |||
167 | /* Read it back and verify */ | ||
168 | rc = efx_i2c_read(i2c, MAX6647, RLHN, &in, 1); | ||
169 | if (rc) | ||
170 | goto fail1; | ||
171 | if (in != xgphy_max_temperature) { | ||
172 | rc = -EFAULT; | ||
173 | goto fail1; | ||
174 | } | ||
175 | |||
176 | /* Clear any previous over-temperature alert */ | ||
177 | rc = efx_i2c_read(i2c, MAX6647, RSL, &in, 1); | ||
178 | if (rc) | ||
179 | goto fail1; | ||
180 | |||
181 | /* Enable port 0 and port 1 outputs on IO expander */ | ||
182 | cfg = 0x00; | ||
183 | rc = efx_i2c_write(i2c, PCA9539, P0_CONFIG, &cfg, 1); | ||
184 | if (rc) | ||
185 | goto fail1; | ||
186 | cfg = 0xff & ~(1 << P1_SPARE_LBN); | ||
187 | rc = efx_i2c_write(i2c, PCA9539, P1_CONFIG, &cfg, 1); | ||
188 | if (rc) | ||
189 | goto fail2; | ||
190 | |||
191 | /* Turn all power off then wait 1 sec. This ensures PHY is reset */ | ||
192 | out = 0xff & ~((0 << P0_EN_1V2_LBN) | (0 << P0_EN_2V5_LBN) | | ||
193 | (0 << P0_EN_3V3X_LBN) | (0 << P0_EN_5V_LBN) | | ||
194 | (0 << P0_EN_1V0X_LBN)); | ||
195 | rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); | ||
196 | if (rc) | ||
197 | goto fail3; | ||
198 | |||
199 | schedule_timeout_uninterruptible(HZ); | ||
200 | count = 0; | ||
201 | do { | ||
202 | /* Turn on 1.2V, 2.5V, 3.3V and 5V power rails */ | ||
203 | out = 0xff & ~((1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) | | ||
204 | (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) | | ||
205 | (1 << P0_X_TRST_LBN)); | ||
206 | |||
207 | rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); | ||
208 | if (rc) | ||
209 | goto fail3; | ||
210 | msleep(10); | ||
211 | |||
212 | /* Turn on 1V power rail */ | ||
213 | out &= ~(1 << P0_EN_1V0X_LBN); | ||
214 | rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); | ||
215 | if (rc) | ||
216 | goto fail3; | ||
217 | |||
218 | EFX_INFO(efx, "waiting for power (attempt %d)...\n", count); | ||
219 | |||
220 | schedule_timeout_uninterruptible(HZ); | ||
221 | |||
222 | /* Check DSP is powered */ | ||
223 | rc = efx_i2c_read(i2c, PCA9539, P1_IN, &in, 1); | ||
224 | if (rc) | ||
225 | goto fail3; | ||
226 | if (in & (1 << P1_AFE_PWD_LBN)) | ||
227 | goto done; | ||
228 | |||
229 | } while (++count < 20); | ||
230 | |||
231 | EFX_INFO(efx, "timed out waiting for power\n"); | ||
232 | rc = -ETIMEDOUT; | ||
233 | goto fail3; | ||
234 | |||
235 | done: | ||
236 | EFX_INFO(efx, "PHY is powered on\n"); | ||
237 | return 0; | ||
238 | |||
239 | fail3: | ||
240 | /* Turn off all power rails */ | ||
241 | out = 0xff; | ||
242 | (void) efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); | ||
243 | /* Disable port 1 outputs on IO expander */ | ||
244 | out = 0xff; | ||
245 | (void) efx_i2c_write(i2c, PCA9539, P1_CONFIG, &out, 1); | ||
246 | fail2: | ||
247 | /* Disable port 0 outputs on IO expander */ | ||
248 | out = 0xff; | ||
249 | (void) efx_i2c_write(i2c, PCA9539, P0_CONFIG, &out, 1); | ||
250 | fail1: | ||
251 | return rc; | ||
252 | } | ||