diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2008-05-07 07:55:13 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-05-13 01:31:40 -0400 |
commit | 75f2d3eac93277fa022b2fbe51257e856575e757 (patch) | |
tree | 72c693ec5039e4c30b51713a6a550829fd17c1d1 /drivers/net/sfc/sfe4001.c | |
parent | b9b39b625cf57cd0ea998717598b68963cbec3cb (diff) |
[netdrvr] sfc: Add phy_flash_cfg module parameter and implementation
The 10Xpress PHY supports flash upgrades through MDIO, but needs to be
put in upgrade mode at power-up. This adds a module parameter and other
logic to support that.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/sfc/sfe4001.c')
-rw-r--r-- | drivers/net/sfc/sfe4001.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/sfc/sfe4001.c b/drivers/net/sfc/sfe4001.c index 11fa9fb8f48b..725d1a539c49 100644 --- a/drivers/net/sfc/sfe4001.c +++ b/drivers/net/sfc/sfe4001.c | |||
@@ -130,6 +130,15 @@ void sfe4001_poweroff(struct efx_nic *efx) | |||
130 | (void) efx_i2c_read(i2c, MAX6647, RSL, &in, 1); | 130 | (void) efx_i2c_read(i2c, MAX6647, RSL, &in, 1); |
131 | } | 131 | } |
132 | 132 | ||
133 | /* The P0_EN_3V3X line on SFE4001 boards (from A2 onward) is connected | ||
134 | * to the FLASH_CFG_1 input on the DSP. We must keep it high at power- | ||
135 | * up to allow writing the flash (done through MDIO from userland). | ||
136 | */ | ||
137 | unsigned int sfe4001_phy_flash_cfg; | ||
138 | module_param_named(phy_flash_cfg, sfe4001_phy_flash_cfg, uint, 0444); | ||
139 | MODULE_PARM_DESC(phy_flash_cfg, | ||
140 | "Force PHY to enter flash configuration mode"); | ||
141 | |||
133 | /* This board uses an I2C expander to provider power to the PHY, which needs to | 142 | /* This board uses an I2C expander to provider power to the PHY, which needs to |
134 | * be turned on before the PHY can be used. | 143 | * be turned on before the PHY can be used. |
135 | * Context: Process context, rtnl lock held | 144 | * Context: Process context, rtnl lock held |
@@ -203,6 +212,8 @@ int sfe4001_poweron(struct efx_nic *efx) | |||
203 | out = 0xff & ~((1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) | | 212 | out = 0xff & ~((1 << P0_EN_1V2_LBN) | (1 << P0_EN_2V5_LBN) | |
204 | (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) | | 213 | (1 << P0_EN_3V3X_LBN) | (1 << P0_EN_5V_LBN) | |
205 | (1 << P0_X_TRST_LBN)); | 214 | (1 << P0_X_TRST_LBN)); |
215 | if (sfe4001_phy_flash_cfg) | ||
216 | out |= 1 << P0_EN_3V3X_LBN; | ||
206 | 217 | ||
207 | rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); | 218 | rc = efx_i2c_write(i2c, PCA9539, P0_OUT, &out, 1); |
208 | if (rc) | 219 | if (rc) |
@@ -226,6 +237,9 @@ int sfe4001_poweron(struct efx_nic *efx) | |||
226 | if (in & (1 << P1_AFE_PWD_LBN)) | 237 | if (in & (1 << P1_AFE_PWD_LBN)) |
227 | goto done; | 238 | goto done; |
228 | 239 | ||
240 | /* DSP doesn't look powered in flash config mode */ | ||
241 | if (sfe4001_phy_flash_cfg) | ||
242 | goto done; | ||
229 | } while (++count < 20); | 243 | } while (++count < 20); |
230 | 244 | ||
231 | EFX_INFO(efx, "timed out waiting for power\n"); | 245 | EFX_INFO(efx, "timed out waiting for power\n"); |