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authorBen Hutchings <bhutchings@solarflare.com>2010-12-02 08:46:37 -0500
committerDavid S. Miller <davem@davemloft.net>2010-12-03 12:08:04 -0500
commit3157183a90fdbd686f939d2f032b675f7e9983d6 (patch)
tree14bd61a1eada344db7778aa66a0aaf4c8d67870c /drivers/net/sfc/qt202x_phy.c
parentadc1d234116c22247e3886fb6e9bef450a0110f2 (diff)
sfc: Clear RXIN_SEL when soft-resetting QT2025C
When we enable PMA/PMD loopback this automatically sets RXIN_SEL (inverse polarity for RXIN). We need to clear that bit during the soft-reset sequence, as it is not done automatically. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/qt202x_phy.c')
-rw-r--r--drivers/net/sfc/qt202x_phy.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/sfc/qt202x_phy.c b/drivers/net/sfc/qt202x_phy.c
index 68813d1d85f3..ea3ae0089315 100644
--- a/drivers/net/sfc/qt202x_phy.c
+++ b/drivers/net/sfc/qt202x_phy.c
@@ -41,6 +41,8 @@
41#define PCS_UC_STATUS_LBN 0 41#define PCS_UC_STATUS_LBN 0
42#define PCS_UC_STATUS_WIDTH 8 42#define PCS_UC_STATUS_WIDTH 8
43#define PCS_UC_STATUS_FW_SAVE 0x20 43#define PCS_UC_STATUS_FW_SAVE 0x20
44#define PMA_PMD_MODE_REG 0xc301
45#define PMA_PMD_RXIN_SEL_LBN 6
44#define PMA_PMD_FTX_CTRL2_REG 0xc309 46#define PMA_PMD_FTX_CTRL2_REG 0xc309
45#define PMA_PMD_FTX_STATIC_LBN 13 47#define PMA_PMD_FTX_STATIC_LBN 13
46#define PMA_PMD_VEND1_REG 0xc001 48#define PMA_PMD_VEND1_REG 0xc001
@@ -282,6 +284,10 @@ static int qt2025c_select_phy_mode(struct efx_nic *efx)
282 * slow) reload of the firmware image (the microcontroller's code 284 * slow) reload of the firmware image (the microcontroller's code
283 * memory is not affected by the microcontroller reset). */ 285 * memory is not affected by the microcontroller reset). */
284 efx_mdio_write(efx, 1, 0xc317, 0x00ff); 286 efx_mdio_write(efx, 1, 0xc317, 0x00ff);
287 /* PMA/PMD loopback sets RXIN to inverse polarity and the firmware
288 * restart doesn't reset it. We need to do that ourselves. */
289 efx_mdio_set_flag(efx, 1, PMA_PMD_MODE_REG,
290 1 << PMA_PMD_RXIN_SEL_LBN, false);
285 efx_mdio_write(efx, 1, 0xc300, 0x0002); 291 efx_mdio_write(efx, 1, 0xc300, 0x0002);
286 msleep(20); 292 msleep(20);
287 293