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authorBen Hutchings <bhutchings@solarflare.com>2008-05-07 08:36:19 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-05-13 01:31:44 -0400
commit3273c2e8c66a21ae1c53b0c730ee937c6efde7e2 (patch)
treeee2a1f187c0310e229f51fbfc5fbbe7a5fce5b76 /drivers/net/sfc/mdio_10g.h
parent05e3ec04460180f48810cddc2f78e80a725657ad (diff)
[netdrvr] sfc: sfc: Add self-test support
Add a set of self-tests accessible thorugh ethtool. Add hardware loopback and TX disable control code to support them. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/sfc/mdio_10g.h')
-rw-r--r--drivers/net/sfc/mdio_10g.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/sfc/mdio_10g.h b/drivers/net/sfc/mdio_10g.h
index 338c62c1195b..cb99f3f4491c 100644
--- a/drivers/net/sfc/mdio_10g.h
+++ b/drivers/net/sfc/mdio_10g.h
@@ -44,11 +44,16 @@
44#define MDIO_MMDREG_DEVS1 (6) 44#define MDIO_MMDREG_DEVS1 (6)
45#define MDIO_MMDREG_CTRL2 (7) 45#define MDIO_MMDREG_CTRL2 (7)
46#define MDIO_MMDREG_STAT2 (8) 46#define MDIO_MMDREG_STAT2 (8)
47#define MDIO_MMDREG_TXDIS (9)
47 48
48/* Bits in MMDREG_CTRL1 */ 49/* Bits in MMDREG_CTRL1 */
49/* Reset */ 50/* Reset */
50#define MDIO_MMDREG_CTRL1_RESET_LBN (15) 51#define MDIO_MMDREG_CTRL1_RESET_LBN (15)
51#define MDIO_MMDREG_CTRL1_RESET_WIDTH (1) 52#define MDIO_MMDREG_CTRL1_RESET_WIDTH (1)
53/* Loopback */
54/* Loopback bit for WIS, PCS, PHYSX and DTEXS */
55#define MDIO_MMDREG_CTRL1_LBACK_LBN (14)
56#define MDIO_MMDREG_CTRL1_LBACK_WIDTH (1)
52 57
53/* Bits in MMDREG_STAT1 */ 58/* Bits in MMDREG_STAT1 */
54#define MDIO_MMDREG_STAT1_FAULT_LBN (7) 59#define MDIO_MMDREG_STAT1_FAULT_LBN (7)
@@ -56,6 +61,9 @@
56/* Link state */ 61/* Link state */
57#define MDIO_MMDREG_STAT1_LINK_LBN (2) 62#define MDIO_MMDREG_STAT1_LINK_LBN (2)
58#define MDIO_MMDREG_STAT1_LINK_WIDTH (1) 63#define MDIO_MMDREG_STAT1_LINK_WIDTH (1)
64/* Low power ability */
65#define MDIO_MMDREG_STAT1_LPABLE_LBN (1)
66#define MDIO_MMDREG_STAT1_LPABLE_WIDTH (1)
59 67
60/* Bits in ID reg */ 68/* Bits in ID reg */
61#define MDIO_ID_REV(_id32) (_id32 & 0xf) 69#define MDIO_ID_REV(_id32) (_id32 & 0xf)
@@ -76,6 +84,14 @@
76#define MDIO_MMDREG_STAT2_PRESENT_LBN (14) 84#define MDIO_MMDREG_STAT2_PRESENT_LBN (14)
77#define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2) 85#define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
78 86
87/* Bits in MMDREG_TXDIS */
88#define MDIO_MMDREG_TXDIS_GLOBAL_LBN (0)
89#define MDIO_MMDREG_TXDIS_GLOBAL_WIDTH (1)
90
91/* MMD-specific bits, ordered by MMD, then register */
92#define MDIO_PMAPMD_CTRL1_LBACK_LBN (0)
93#define MDIO_PMAPMD_CTRL1_LBACK_WIDTH (1)
94
79/* PMA type (4 bits) */ 95/* PMA type (4 bits) */
80#define MDIO_PMAPMD_CTRL2_10G_CX4 (0x0) 96#define MDIO_PMAPMD_CTRL2_10G_CX4 (0x0)
81#define MDIO_PMAPMD_CTRL2_10G_EW (0x1) 97#define MDIO_PMAPMD_CTRL2_10G_EW (0x1)
@@ -217,6 +233,12 @@ int mdio_clause45_check_mmds(struct efx_nic *efx,
217extern int mdio_clause45_links_ok(struct efx_nic *efx, 233extern int mdio_clause45_links_ok(struct efx_nic *efx,
218 unsigned int mmd_mask); 234 unsigned int mmd_mask);
219 235
236/* Generic transmit disable support though PMAPMD */
237extern void mdio_clause45_transmit_disable(struct efx_nic *efx);
238
239/* Generic part of reconfigure: set/clear loopback bits */
240extern void mdio_clause45_phy_reconfigure(struct efx_nic *efx);
241
220/* Read (some of) the PHY settings over MDIO */ 242/* Read (some of) the PHY settings over MDIO */
221extern void mdio_clause45_get_settings(struct efx_nic *efx, 243extern void mdio_clause45_get_settings(struct efx_nic *efx,
222 struct ethtool_cmd *ecmd); 244 struct ethtool_cmd *ecmd);