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authorBen Hutchings <bhutchings@solarflare.com>2009-04-29 04:05:08 -0400
committerDavid S. Miller <davem@davemloft.net>2009-04-29 20:32:30 -0400
commit68e7f45e118f98b77cfa007aa2d97b5dac69fe6b (patch)
treed2e05579a0fc1f5a28bce8ff09ac6863d1907186 /drivers/net/sfc/mdio_10g.h
parent1b1c2e95103ce391c2ea39a9460968fcb73deb30 (diff)
sfc: Use generic MDIO functions and definitions
Make use of the newly-added generic MDIO clause 45 support and remove redundant definitions. Add an 'efx_' prefix to the remaining driver-specific MDIO functions and remove arguments which are redundant with efx->mdio.prtad. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/mdio_10g.h')
-rw-r--r--drivers/net/sfc/mdio_10g.h281
1 files changed, 40 insertions, 241 deletions
diff --git a/drivers/net/sfc/mdio_10g.h b/drivers/net/sfc/mdio_10g.h
index 7014d2279c20..ea4587d93698 100644
--- a/drivers/net/sfc/mdio_10g.h
+++ b/drivers/net/sfc/mdio_10g.h
@@ -10,247 +10,53 @@
10#ifndef EFX_MDIO_10G_H 10#ifndef EFX_MDIO_10G_H
11#define EFX_MDIO_10G_H 11#define EFX_MDIO_10G_H
12 12
13#include <linux/mdio.h>
14
13/* 15/*
14 * Definitions needed for doing 10G MDIO as specified in clause 45 16 * Helper functions for doing 10G MDIO as specified in IEEE 802.3 clause 45.
15 * MDIO, which do not appear in Linux yet. Also some helper functions.
16 */ 17 */
17 18
18#include "efx.h" 19#include "efx.h"
19#include "boards.h" 20#include "boards.h"
20 21
21/* Numbering of the MDIO Manageable Devices (MMDs) */ 22static inline unsigned efx_mdio_id_rev(u32 id) { return id & 0xf; }
22/* Physical Medium Attachment/ Physical Medium Dependent sublayer */ 23static inline unsigned efx_mdio_id_model(u32 id) { return (id >> 4) & 0x3f; }
23#define MDIO_MMD_PMAPMD (1) 24extern unsigned efx_mdio_id_oui(u32 id);
24/* WAN Interface Sublayer */
25#define MDIO_MMD_WIS (2)
26/* Physical Coding Sublayer */
27#define MDIO_MMD_PCS (3)
28/* PHY Extender Sublayer */
29#define MDIO_MMD_PHYXS (4)
30/* Extender Sublayer */
31#define MDIO_MMD_DTEXS (5)
32/* Transmission convergence */
33#define MDIO_MMD_TC (6)
34/* Auto negotiation */
35#define MDIO_MMD_AN (7)
36/* Clause 22 extension */
37#define MDIO_MMD_C22EXT 29
38
39/* Generic register locations */
40#define MDIO_MMDREG_CTRL1 (0)
41#define MDIO_MMDREG_STAT1 (1)
42#define MDIO_MMDREG_IDHI (2)
43#define MDIO_MMDREG_IDLOW (3)
44#define MDIO_MMDREG_SPEED (4)
45#define MDIO_MMDREG_DEVS0 (5)
46#define MDIO_MMDREG_DEVS1 (6)
47#define MDIO_MMDREG_CTRL2 (7)
48#define MDIO_MMDREG_STAT2 (8)
49#define MDIO_MMDREG_TXDIS (9)
50
51/* Bits in MMDREG_CTRL1 */
52/* Reset */
53#define MDIO_MMDREG_CTRL1_RESET_LBN (15)
54#define MDIO_MMDREG_CTRL1_RESET_WIDTH (1)
55/* Loopback */
56/* Loopback bit for WIS, PCS, PHYSX and DTEXS */
57#define MDIO_MMDREG_CTRL1_LBACK_LBN (14)
58#define MDIO_MMDREG_CTRL1_LBACK_WIDTH (1)
59/* Low power */
60#define MDIO_MMDREG_CTRL1_LPOWER_LBN (11)
61#define MDIO_MMDREG_CTRL1_LPOWER_WIDTH (1)
62
63/* Bits in MMDREG_STAT1 */
64#define MDIO_MMDREG_STAT1_FAULT_LBN (7)
65#define MDIO_MMDREG_STAT1_FAULT_WIDTH (1)
66/* Link state */
67#define MDIO_MMDREG_STAT1_LINK_LBN (2)
68#define MDIO_MMDREG_STAT1_LINK_WIDTH (1)
69/* Low power ability */
70#define MDIO_MMDREG_STAT1_LPABLE_LBN (1)
71#define MDIO_MMDREG_STAT1_LPABLE_WIDTH (1)
72
73/* Bits in combined ID regs */
74static inline unsigned mdio_id_rev(u32 id) { return id & 0xf; }
75static inline unsigned mdio_id_model(u32 id) { return (id >> 4) & 0x3f; }
76extern unsigned mdio_id_oui(u32 id);
77
78/* Bits in MMDREG_DEVS0/1. Someone thoughtfully layed things out
79 * so the 'bit present' bit number of an MMD is the number of
80 * that MMD */
81#define DEV_PRESENT_BIT(_b) (1 << _b)
82
83#define MDIO_MMDREG_DEVS_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
84#define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS)
85#define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
86#define MDIO_MMDREG_DEVS_AN DEV_PRESENT_BIT(MDIO_MMD_AN)
87#define MDIO_MMDREG_DEVS_C22EXT DEV_PRESENT_BIT(MDIO_MMD_C22EXT)
88
89/* Bits in MMDREG_SPEED */
90#define MDIO_MMDREG_SPEED_10G_LBN 0
91#define MDIO_MMDREG_SPEED_10G_WIDTH 1
92#define MDIO_MMDREG_SPEED_1000M_LBN 4
93#define MDIO_MMDREG_SPEED_1000M_WIDTH 1
94#define MDIO_MMDREG_SPEED_100M_LBN 5
95#define MDIO_MMDREG_SPEED_100M_WIDTH 1
96#define MDIO_MMDREG_SPEED_10M_LBN 6
97#define MDIO_MMDREG_SPEED_10M_WIDTH 1
98
99/* Bits in MMDREG_STAT2 */
100#define MDIO_MMDREG_STAT2_PRESENT_VAL (2)
101#define MDIO_MMDREG_STAT2_PRESENT_LBN (14)
102#define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
103
104/* Bits in MMDREG_TXDIS */
105#define MDIO_MMDREG_TXDIS_GLOBAL_LBN (0)
106#define MDIO_MMDREG_TXDIS_GLOBAL_WIDTH (1)
107
108/* MMD-specific bits, ordered by MMD, then register */
109#define MDIO_PMAPMD_CTRL1_LBACK_LBN (0)
110#define MDIO_PMAPMD_CTRL1_LBACK_WIDTH (1)
111
112/* PMA type (4 bits) */
113#define MDIO_PMAPMD_CTRL2_10G_CX4 (0x0)
114#define MDIO_PMAPMD_CTRL2_10G_EW (0x1)
115#define MDIO_PMAPMD_CTRL2_10G_LW (0x2)
116#define MDIO_PMAPMD_CTRL2_10G_SW (0x3)
117#define MDIO_PMAPMD_CTRL2_10G_LX4 (0x4)
118#define MDIO_PMAPMD_CTRL2_10G_ER (0x5)
119#define MDIO_PMAPMD_CTRL2_10G_LR (0x6)
120#define MDIO_PMAPMD_CTRL2_10G_SR (0x7)
121/* Reserved */
122#define MDIO_PMAPMD_CTRL2_10G_BT (0x9)
123/* Reserved */
124/* Reserved */
125#define MDIO_PMAPMD_CTRL2_1G_BT (0xc)
126/* Reserved */
127#define MDIO_PMAPMD_CTRL2_100_BT (0xe)
128#define MDIO_PMAPMD_CTRL2_10_BT (0xf)
129#define MDIO_PMAPMD_CTRL2_TYPE_MASK (0xf)
130
131/* PMA 10GBT registers */
132#define MDIO_PMAPMD_10GBT_TXPWR (131)
133#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN (0)
134#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_WIDTH (1)
135
136/* PHY XGXS Status 2 */
137#define MDIO_PHYXS_STATUS2 (8)
138#define MDIO_PHYXS_STATUS2_RX_FAULT_LBN 10
139
140/* PHY XGXS lane state */
141#define MDIO_PHYXS_LANE_STATE (0x18)
142#define MDIO_PHYXS_LANE_ALIGNED_LBN (12)
143
144/* AN registers */
145#define MDIO_AN_CTRL_XNP_LBN 13
146#define MDIO_AN_STATUS (1)
147#define MDIO_AN_STATUS_XNP_LBN (7)
148#define MDIO_AN_STATUS_PAGE_LBN (6)
149#define MDIO_AN_STATUS_AN_DONE_LBN (5)
150#define MDIO_AN_STATUS_LP_AN_CAP_LBN (0)
151
152#define MDIO_AN_ADVERTISE 16
153#define MDIO_AN_ADVERTISE_XNP_LBN 12
154#define MDIO_AN_LPA 19
155#define MDIO_AN_XNP 22
156#define MDIO_AN_LPA_XNP 25
157
158#define MDIO_AN_10GBT_CTRL 32
159#define MDIO_AN_10GBT_CTRL_ADV_10G_LBN 12
160#define MDIO_AN_10GBT_STATUS (33)
161#define MDIO_AN_10GBT_STATUS_MS_FLT_LBN (15) /* MASTER/SLAVE config fault */
162#define MDIO_AN_10GBT_STATUS_MS_LBN (14) /* MASTER/SLAVE config */
163#define MDIO_AN_10GBT_STATUS_LOC_OK_LBN (13) /* Local OK */
164#define MDIO_AN_10GBT_STATUS_REM_OK_LBN (12) /* Remote OK */
165#define MDIO_AN_10GBT_STATUS_LP_10G_LBN (11) /* Link partner is 10GBT capable */
166#define MDIO_AN_10GBT_STATUS_LP_LTA_LBN (10) /* LP loop timing ability */
167#define MDIO_AN_10GBT_STATUS_LP_TRR_LBN (9) /* LP Training Reset Request */
168 25
169 26static inline int efx_mdio_read(struct efx_nic *efx, int devad, int addr)
170/* Packing of the prt and dev arguments of clause 45 style MDIO into a
171 * single int so they can be passed into the mdio_read/write functions
172 * that currently exist. Note that as Falcon is the only current user,
173 * the packed form is chosen to match what Falcon needs to write into
174 * a register. This is checked at compile-time so do not change it. If
175 * your target chip needs things layed out differently you will need
176 * to unpack the arguments in your chip-specific mdio functions.
177 */
178 /* These are defined by the standard. */
179#define MDIO45_PRT_ID_WIDTH (5)
180#define MDIO45_DEV_ID_WIDTH (5)
181
182/* The prt ID is just packed in immediately to the left of the dev ID */
183#define MDIO45_PRT_DEV_WIDTH (MDIO45_PRT_ID_WIDTH + MDIO45_DEV_ID_WIDTH)
184
185#define MDIO45_PRT_ID_MASK ((1 << MDIO45_PRT_DEV_WIDTH) - 1)
186/* This is the prt + dev extended by 1 bit to hold the 'is clause 45' flag. */
187#define MDIO45_XPRT_ID_WIDTH (MDIO45_PRT_DEV_WIDTH + 1)
188#define MDIO45_XPRT_ID_MASK ((1 << MDIO45_XPRT_ID_WIDTH) - 1)
189#define MDIO45_XPRT_ID_IS10G (1 << (MDIO45_XPRT_ID_WIDTH - 1))
190
191
192#define MDIO45_PRT_ID_COMP_LBN MDIO45_DEV_ID_WIDTH
193#define MDIO45_PRT_ID_COMP_WIDTH MDIO45_PRT_ID_WIDTH
194#define MDIO45_DEV_ID_COMP_LBN 0
195#define MDIO45_DEV_ID_COMP_WIDTH MDIO45_DEV_ID_WIDTH
196
197/* Compose port and device into a phy_id */
198static inline int mdio_clause45_pack(u8 prt, u8 dev)
199{
200 efx_dword_t phy_id;
201 EFX_POPULATE_DWORD_2(phy_id, MDIO45_PRT_ID_COMP, prt,
202 MDIO45_DEV_ID_COMP, dev);
203 return MDIO45_XPRT_ID_IS10G | EFX_DWORD_VAL(phy_id);
204}
205
206static inline void mdio_clause45_unpack(u32 val, u8 *prt, u8 *dev)
207{ 27{
208 efx_dword_t phy_id; 28 return efx->mdio.mdio_read(efx->net_dev, efx->mdio.prtad, devad, addr);
209 EFX_POPULATE_DWORD_1(phy_id, EFX_DWORD_0, val);
210 *prt = EFX_DWORD_FIELD(phy_id, MDIO45_PRT_ID_COMP);
211 *dev = EFX_DWORD_FIELD(phy_id, MDIO45_DEV_ID_COMP);
212} 29}
213 30
214static inline int mdio_clause45_read(struct efx_nic *efx, 31static inline void
215 u8 prt, u8 dev, u16 addr) 32efx_mdio_write(struct efx_nic *efx, int devad, int addr, int value)
216{ 33{
217 return efx->mii.mdio_read(efx->net_dev, 34 efx->mdio.mdio_write(efx->net_dev, efx->mdio.prtad, devad, addr, value);
218 mdio_clause45_pack(prt, dev), addr);
219} 35}
220 36
221static inline void mdio_clause45_write(struct efx_nic *efx, 37static inline u32 efx_mdio_read_id(struct efx_nic *efx, int mmd)
222 u8 prt, u8 dev, u16 addr, int value)
223{
224 efx->mii.mdio_write(efx->net_dev,
225 mdio_clause45_pack(prt, dev), addr, value);
226}
227
228
229static inline u32 mdio_clause45_read_id(struct efx_nic *efx, int mmd)
230{ 38{
231 int phy_id = efx->mii.phy_id; 39 u16 id_low = efx_mdio_read(efx, mmd, MDIO_DEVID2);
232 u16 id_low = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDLOW); 40 u16 id_hi = efx_mdio_read(efx, mmd, MDIO_DEVID1);
233 u16 id_hi = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDHI);
234 return (id_hi << 16) | (id_low); 41 return (id_hi << 16) | (id_low);
235} 42}
236 43
237static inline bool mdio_clause45_phyxgxs_lane_sync(struct efx_nic *efx) 44static inline bool efx_mdio_phyxgxs_lane_sync(struct efx_nic *efx)
238{ 45{
239 int i, lane_status; 46 int i, lane_status;
240 bool sync; 47 bool sync;
241 48
242 for (i = 0; i < 2; ++i) 49 for (i = 0; i < 2; ++i)
243 lane_status = mdio_clause45_read(efx, efx->mii.phy_id, 50 lane_status = efx_mdio_read(efx, MDIO_MMD_PHYXS,
244 MDIO_MMD_PHYXS, 51 MDIO_PHYXS_LNSTAT);
245 MDIO_PHYXS_LANE_STATE);
246 52
247 sync = !!(lane_status & (1 << MDIO_PHYXS_LANE_ALIGNED_LBN)); 53 sync = !!(lane_status & MDIO_PHYXS_LNSTAT_ALIGN);
248 if (!sync) 54 if (!sync)
249 EFX_LOG(efx, "XGXS lane status: %x\n", lane_status); 55 EFX_LOG(efx, "XGXS lane status: %x\n", lane_status);
250 return sync; 56 return sync;
251} 57}
252 58
253extern const char *mdio_clause45_mmd_name(int mmd); 59extern const char *efx_mdio_mmd_name(int mmd);
254 60
255/* 61/*
256 * Reset a specific MMD and wait for reset to clear. 62 * Reset a specific MMD and wait for reset to clear.
@@ -258,54 +64,47 @@ extern const char *mdio_clause45_mmd_name(int mmd);
258 * 64 *
259 * This function will sleep 65 * This function will sleep
260 */ 66 */
261extern int mdio_clause45_reset_mmd(struct efx_nic *efx, int mmd, 67extern int efx_mdio_reset_mmd(struct efx_nic *efx, int mmd,
262 int spins, int spintime); 68 int spins, int spintime);
263 69
264/* As mdio_clause45_check_mmd but for multiple MMDs */ 70/* As efx_mdio_check_mmd but for multiple MMDs */
265int mdio_clause45_check_mmds(struct efx_nic *efx, 71int efx_mdio_check_mmds(struct efx_nic *efx,
266 unsigned int mmd_mask, unsigned int fatal_mask); 72 unsigned int mmd_mask, unsigned int fatal_mask);
267 73
268/* Check the link status of specified mmds in bit mask */ 74/* Check the link status of specified mmds in bit mask */
269extern bool mdio_clause45_links_ok(struct efx_nic *efx, 75extern bool efx_mdio_links_ok(struct efx_nic *efx, unsigned int mmd_mask);
270 unsigned int mmd_mask);
271 76
272/* Generic transmit disable support though PMAPMD */ 77/* Generic transmit disable support though PMAPMD */
273extern void mdio_clause45_transmit_disable(struct efx_nic *efx); 78extern void efx_mdio_transmit_disable(struct efx_nic *efx);
274 79
275/* Generic part of reconfigure: set/clear loopback bits */ 80/* Generic part of reconfigure: set/clear loopback bits */
276extern void mdio_clause45_phy_reconfigure(struct efx_nic *efx); 81extern void efx_mdio_phy_reconfigure(struct efx_nic *efx);
277 82
278/* Set the power state of the specified MMDs */ 83/* Set the power state of the specified MMDs */
279extern void mdio_clause45_set_mmds_lpower(struct efx_nic *efx, 84extern void efx_mdio_set_mmds_lpower(struct efx_nic *efx,
280 int low_power, unsigned int mmd_mask); 85 int low_power, unsigned int mmd_mask);
281
282/* Read (some of) the PHY settings over MDIO */
283extern void mdio_clause45_get_settings(struct efx_nic *efx,
284 struct ethtool_cmd *ecmd);
285
286/* Read (some of) the PHY settings over MDIO */
287extern void
288mdio_clause45_get_settings_ext(struct efx_nic *efx, struct ethtool_cmd *ecmd,
289 u32 xnp, u32 xnp_lpa);
290 86
291/* Set (some of) the PHY settings over MDIO */ 87/* Set (some of) the PHY settings over MDIO */
292extern int mdio_clause45_set_settings(struct efx_nic *efx, 88extern int efx_mdio_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd);
293 struct ethtool_cmd *ecmd);
294 89
295/* Set pause parameters to be advertised through AN (if available) */ 90/* Set pause parameters to be advertised through AN (if available) */
296extern void mdio_clause45_set_pause(struct efx_nic *efx); 91extern void efx_mdio_set_pause(struct efx_nic *efx);
297 92
298/* Get pause parameters from AN if available (otherwise return 93/* Get pause parameters from AN if available (otherwise return
299 * requested pause parameters) 94 * requested pause parameters)
300 */ 95 */
301enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx); 96enum efx_fc_type efx_mdio_get_pause(struct efx_nic *efx);
302 97
303/* Wait for specified MMDs to exit reset within a timeout */ 98/* Wait for specified MMDs to exit reset within a timeout */
304extern int mdio_clause45_wait_reset_mmds(struct efx_nic *efx, 99extern int efx_mdio_wait_reset_mmds(struct efx_nic *efx,
305 unsigned int mmd_mask); 100 unsigned int mmd_mask);
306 101
307/* Set or clear flag, debouncing */ 102/* Set or clear flag, debouncing */
308extern void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev, 103static inline void
309 u16 addr, int bit, bool sense); 104efx_mdio_set_flag(struct efx_nic *efx, int devad, int addr,
105 int mask, bool state)
106{
107 mdio_set_flag(&efx->mdio, efx->mdio.prtad, devad, addr, mask, state);
108}
310 109
311#endif /* EFX_MDIO_10G_H */ 110#endif /* EFX_MDIO_10G_H */
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