diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2008-12-13 00:50:46 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-12-13 00:58:17 -0500 |
commit | 04cc8cacb01c09fba2297faf1477cd570ba43f0b (patch) | |
tree | f17dbd584b072d14f1500c6f6d659be993ae35c7 /drivers/net/sfc/mdio_10g.h | |
parent | 177dfcd80f28f8fbc3e22c2d8b24d21cb86f1d97 (diff) |
sfc: Implement auto-negotiation
Add infrastructure for auto-negotiation of speed, duplex and flow
control.
When using 10Xpress, auto-negotiate flow control. While we're
at it, clean up the code to warn when partner is not 10GBASE-T
capable.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/mdio_10g.h')
-rw-r--r-- | drivers/net/sfc/mdio_10g.h | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/net/sfc/mdio_10g.h b/drivers/net/sfc/mdio_10g.h index 4830e0c1da0b..80c63dde8864 100644 --- a/drivers/net/sfc/mdio_10g.h +++ b/drivers/net/sfc/mdio_10g.h | |||
@@ -81,6 +81,17 @@ | |||
81 | #define MDIO_MMDREG_DEVS_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS) | 81 | #define MDIO_MMDREG_DEVS_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS) |
82 | #define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) | 82 | #define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) |
83 | #define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) | 83 | #define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) |
84 | #define MDIO_MMDREG_DEVS_AN DEV_PRESENT_BIT(MDIO_MMD_AN) | ||
85 | |||
86 | /* Bits in MMDREG_SPEED */ | ||
87 | #define MDIO_MMDREG_SPEED_10G_LBN 0 | ||
88 | #define MDIO_MMDREG_SPEED_10G_WIDTH 1 | ||
89 | #define MDIO_MMDREG_SPEED_1000M_LBN 4 | ||
90 | #define MDIO_MMDREG_SPEED_1000M_WIDTH 1 | ||
91 | #define MDIO_MMDREG_SPEED_100M_LBN 5 | ||
92 | #define MDIO_MMDREG_SPEED_100M_WIDTH 1 | ||
93 | #define MDIO_MMDREG_SPEED_10M_LBN 6 | ||
94 | #define MDIO_MMDREG_SPEED_10M_WIDTH 1 | ||
84 | 95 | ||
85 | /* Bits in MMDREG_STAT2 */ | 96 | /* Bits in MMDREG_STAT2 */ |
86 | #define MDIO_MMDREG_STAT2_PRESENT_VAL (2) | 97 | #define MDIO_MMDREG_STAT2_PRESENT_VAL (2) |
@@ -119,12 +130,20 @@ | |||
119 | #define MDIO_PHYXS_LANE_ALIGNED_LBN (12) | 130 | #define MDIO_PHYXS_LANE_ALIGNED_LBN (12) |
120 | 131 | ||
121 | /* AN registers */ | 132 | /* AN registers */ |
133 | #define MDIO_AN_CTRL_XNP_LBN 13 | ||
122 | #define MDIO_AN_STATUS (1) | 134 | #define MDIO_AN_STATUS (1) |
123 | #define MDIO_AN_STATUS_XNP_LBN (7) | 135 | #define MDIO_AN_STATUS_XNP_LBN (7) |
124 | #define MDIO_AN_STATUS_PAGE_LBN (6) | 136 | #define MDIO_AN_STATUS_PAGE_LBN (6) |
125 | #define MDIO_AN_STATUS_AN_DONE_LBN (5) | 137 | #define MDIO_AN_STATUS_AN_DONE_LBN (5) |
126 | #define MDIO_AN_STATUS_LP_AN_CAP_LBN (0) | 138 | #define MDIO_AN_STATUS_LP_AN_CAP_LBN (0) |
127 | 139 | ||
140 | #define MDIO_AN_ADVERTISE 16 | ||
141 | #define MDIO_AN_ADVERTISE_XNP_LBN 12 | ||
142 | #define MDIO_AN_LPA 19 | ||
143 | #define MDIO_AN_XNP 22 | ||
144 | #define MDIO_AN_LPA_XNP 25 | ||
145 | |||
146 | #define MDIO_AN_10GBT_ADVERTISE 32 | ||
128 | #define MDIO_AN_10GBT_STATUS (33) | 147 | #define MDIO_AN_10GBT_STATUS (33) |
129 | #define MDIO_AN_10GBT_STATUS_MS_FLT_LBN (15) /* MASTER/SLAVE config fault */ | 148 | #define MDIO_AN_10GBT_STATUS_MS_FLT_LBN (15) /* MASTER/SLAVE config fault */ |
130 | #define MDIO_AN_10GBT_STATUS_MS_LBN (14) /* MASTER/SLAVE config */ | 149 | #define MDIO_AN_10GBT_STATUS_MS_LBN (14) /* MASTER/SLAVE config */ |
@@ -251,10 +270,23 @@ extern void mdio_clause45_set_mmds_lpower(struct efx_nic *efx, | |||
251 | extern void mdio_clause45_get_settings(struct efx_nic *efx, | 270 | extern void mdio_clause45_get_settings(struct efx_nic *efx, |
252 | struct ethtool_cmd *ecmd); | 271 | struct ethtool_cmd *ecmd); |
253 | 272 | ||
273 | /* Read (some of) the PHY settings over MDIO */ | ||
274 | extern void | ||
275 | mdio_clause45_get_settings_ext(struct efx_nic *efx, struct ethtool_cmd *ecmd, | ||
276 | u32 xnp, u32 xnp_lpa); | ||
277 | |||
254 | /* Set (some of) the PHY settings over MDIO */ | 278 | /* Set (some of) the PHY settings over MDIO */ |
255 | extern int mdio_clause45_set_settings(struct efx_nic *efx, | 279 | extern int mdio_clause45_set_settings(struct efx_nic *efx, |
256 | struct ethtool_cmd *ecmd); | 280 | struct ethtool_cmd *ecmd); |
257 | 281 | ||
282 | /* Set pause parameters to be advertised through AN (if available) */ | ||
283 | extern void mdio_clause45_set_pause(struct efx_nic *efx); | ||
284 | |||
285 | /* Get pause parameters from AN if available (otherwise return | ||
286 | * requested pause parameters) | ||
287 | */ | ||
288 | enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx); | ||
289 | |||
258 | /* Wait for specified MMDs to exit reset within a timeout */ | 290 | /* Wait for specified MMDs to exit reset within a timeout */ |
259 | extern int mdio_clause45_wait_reset_mmds(struct efx_nic *efx, | 291 | extern int mdio_clause45_wait_reset_mmds(struct efx_nic *efx, |
260 | unsigned int mmd_mask); | 292 | unsigned int mmd_mask); |