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authorBen Hutchings <bhutchings@solarflare.com>2009-11-25 11:08:41 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-26 18:59:00 -0500
commit80cb9a0f7f381e1c0e9f6dabec6e67db0dd3a0d9 (patch)
treef64ca5e6a4d30831109163bdfaffa3e3f8ab7a93 /drivers/net/sfc/falcon_xmac.c
parent46e1ac0f42c7ff20a7e47c172e4835273b0e6899 (diff)
sfc: Treat all MAC registers as 128-bit
Although all the defined fields in these registers are within 32 bits, they are architecturally defined as 128-bit like most other Falcon registers. In particular, we must use efx_reado() to ensure proper locking when reading MD_STAT_REG. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/falcon_xmac.c')
-rw-r--r--drivers/net/sfc/falcon_xmac.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c
index 69cb55fc615a..cf24513900e7 100644
--- a/drivers/net/sfc/falcon_xmac.c
+++ b/drivers/net/sfc/falcon_xmac.c
@@ -64,7 +64,7 @@ int falcon_reset_xaui(struct efx_nic *efx)
64 int count; 64 int count;
65 65
66 /* Start reset sequence */ 66 /* Start reset sequence */
67 EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1); 67 EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
68 efx_writeo(efx, &reg, FR_AB_XX_PWR_RST); 68 efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
69 69
70 /* Wait up to 10 ms for completion, then reinitialise */ 70 /* Wait up to 10 ms for completion, then reinitialise */
@@ -146,14 +146,14 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
146 bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX); 146 bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
147 147
148 /* Configure MAC - cut-thru mode is hard wired on */ 148 /* Configure MAC - cut-thru mode is hard wired on */
149 EFX_POPULATE_DWORD_3(reg, 149 EFX_POPULATE_OWORD_3(reg,
150 FRF_AB_XM_RX_JUMBO_MODE, 1, 150 FRF_AB_XM_RX_JUMBO_MODE, 1,
151 FRF_AB_XM_TX_STAT_EN, 1, 151 FRF_AB_XM_TX_STAT_EN, 1,
152 FRF_AB_XM_RX_STAT_EN, 1); 152 FRF_AB_XM_RX_STAT_EN, 1);
153 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG); 153 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
154 154
155 /* Configure TX */ 155 /* Configure TX */
156 EFX_POPULATE_DWORD_6(reg, 156 EFX_POPULATE_OWORD_6(reg,
157 FRF_AB_XM_TXEN, 1, 157 FRF_AB_XM_TXEN, 1,
158 FRF_AB_XM_TX_PRMBL, 1, 158 FRF_AB_XM_TX_PRMBL, 1,
159 FRF_AB_XM_AUTO_PAD, 1, 159 FRF_AB_XM_AUTO_PAD, 1,
@@ -163,7 +163,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
163 efx_writeo(efx, &reg, FR_AB_XM_TX_CFG); 163 efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
164 164
165 /* Configure RX */ 165 /* Configure RX */
166 EFX_POPULATE_DWORD_5(reg, 166 EFX_POPULATE_OWORD_5(reg,
167 FRF_AB_XM_RXEN, 1, 167 FRF_AB_XM_RXEN, 1,
168 FRF_AB_XM_AUTO_DEPAD, 0, 168 FRF_AB_XM_AUTO_DEPAD, 0,
169 FRF_AB_XM_ACPT_ALL_MCAST, 1, 169 FRF_AB_XM_ACPT_ALL_MCAST, 1,
@@ -173,14 +173,14 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
173 173
174 /* Set frame length */ 174 /* Set frame length */
175 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 175 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
176 EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len); 176 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
177 efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM); 177 efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
178 EFX_POPULATE_DWORD_2(reg, 178 EFX_POPULATE_OWORD_2(reg,
179 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len, 179 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
180 FRF_AB_XM_TX_JUMBO_MODE, 1); 180 FRF_AB_XM_TX_JUMBO_MODE, 1);
181 efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM); 181 efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
182 182
183 EFX_POPULATE_DWORD_2(reg, 183 EFX_POPULATE_OWORD_2(reg,
184 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ 184 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
185 FRF_AB_XM_DIS_FCNTL, !rx_fc); 185 FRF_AB_XM_DIS_FCNTL, !rx_fc);
186 efx_writeo(efx, &reg, FR_AB_XM_FC); 186 efx_writeo(efx, &reg, FR_AB_XM_FC);