diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2009-10-23 04:30:46 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-10-24 07:27:04 -0400 |
commit | 12d00cadcc45382fc127712aa35bd0c96cbf81d9 (patch) | |
tree | 96239fbc49d4907fd1677b9d9a2558525673c11e /drivers/net/sfc/falcon_xmac.c | |
parent | 3e6c4538542ab2103ab7c01f4458bc2e21b672a1 (diff) |
sfc: Rename register I/O header and functions used by both Falcon and Siena
While we're at it, use type suffixes of 'd', 'q' and 'o', consistent
with register type names.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/falcon_xmac.c')
-rw-r--r-- | drivers/net/sfc/falcon_xmac.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c index 44e65584ee32..7e57b4a54b37 100644 --- a/drivers/net/sfc/falcon_xmac.c +++ b/drivers/net/sfc/falcon_xmac.c | |||
@@ -13,7 +13,7 @@ | |||
13 | #include "efx.h" | 13 | #include "efx.h" |
14 | #include "falcon.h" | 14 | #include "falcon.h" |
15 | #include "regs.h" | 15 | #include "regs.h" |
16 | #include "falcon_io.h" | 16 | #include "io.h" |
17 | #include "mac.h" | 17 | #include "mac.h" |
18 | #include "mdio_10g.h" | 18 | #include "mdio_10g.h" |
19 | #include "phy.h" | 19 | #include "phy.h" |
@@ -35,7 +35,7 @@ static void falcon_setup_xaui(struct efx_nic *efx) | |||
35 | if (efx->phy_type == PHY_TYPE_NONE) | 35 | if (efx->phy_type == PHY_TYPE_NONE) |
36 | return; | 36 | return; |
37 | 37 | ||
38 | falcon_read(efx, &sdctl, FR_AB_XX_SD_CTL); | 38 | efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL); |
39 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF); | 39 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF); |
40 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF); | 40 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF); |
41 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF); | 41 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF); |
@@ -44,7 +44,7 @@ static void falcon_setup_xaui(struct efx_nic *efx) | |||
44 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF); | 44 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF); |
45 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF); | 45 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF); |
46 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF); | 46 | EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF); |
47 | falcon_write(efx, &sdctl, FR_AB_XX_SD_CTL); | 47 | efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL); |
48 | 48 | ||
49 | EFX_POPULATE_OWORD_8(txdrv, | 49 | EFX_POPULATE_OWORD_8(txdrv, |
50 | FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF, | 50 | FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF, |
@@ -55,7 +55,7 @@ static void falcon_setup_xaui(struct efx_nic *efx) | |||
55 | FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF, | 55 | FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF, |
56 | FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF, | 56 | FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF, |
57 | FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF); | 57 | FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF); |
58 | falcon_write(efx, &txdrv, FR_AB_XX_TXDRV_CTL); | 58 | efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL); |
59 | } | 59 | } |
60 | 60 | ||
61 | int falcon_reset_xaui(struct efx_nic *efx) | 61 | int falcon_reset_xaui(struct efx_nic *efx) |
@@ -65,11 +65,11 @@ int falcon_reset_xaui(struct efx_nic *efx) | |||
65 | 65 | ||
66 | /* Start reset sequence */ | 66 | /* Start reset sequence */ |
67 | EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1); | 67 | EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1); |
68 | falcon_write(efx, ®, FR_AB_XX_PWR_RST); | 68 | efx_writeo(efx, ®, FR_AB_XX_PWR_RST); |
69 | 69 | ||
70 | /* Wait up to 10 ms for completion, then reinitialise */ | 70 | /* Wait up to 10 ms for completion, then reinitialise */ |
71 | for (count = 0; count < 1000; count++) { | 71 | for (count = 0; count < 1000; count++) { |
72 | falcon_read(efx, ®, FR_AB_XX_PWR_RST); | 72 | efx_reado(efx, ®, FR_AB_XX_PWR_RST); |
73 | if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 && | 73 | if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 && |
74 | EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) { | 74 | EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) { |
75 | falcon_setup_xaui(efx); | 75 | falcon_setup_xaui(efx); |
@@ -99,12 +99,12 @@ static void falcon_mask_status_intr(struct efx_nic *efx, bool enable) | |||
99 | 99 | ||
100 | /* Flush the ISR */ | 100 | /* Flush the ISR */ |
101 | if (enable) | 101 | if (enable) |
102 | falcon_read(efx, ®, FR_AB_XM_MGT_INT_MSK); | 102 | efx_reado(efx, ®, FR_AB_XM_MGT_INT_MSK); |
103 | 103 | ||
104 | EFX_POPULATE_OWORD_2(reg, | 104 | EFX_POPULATE_OWORD_2(reg, |
105 | FRF_AB_XM_MSK_RMTFLT, !enable, | 105 | FRF_AB_XM_MSK_RMTFLT, !enable, |
106 | FRF_AB_XM_MSK_LCLFLT, !enable); | 106 | FRF_AB_XM_MSK_LCLFLT, !enable); |
107 | falcon_write(efx, ®, FR_AB_XM_MGT_INT_MASK); | 107 | efx_writeo(efx, ®, FR_AB_XM_MGT_INT_MASK); |
108 | } | 108 | } |
109 | 109 | ||
110 | /* Get status of XAUI link */ | 110 | /* Get status of XAUI link */ |
@@ -118,7 +118,7 @@ bool falcon_xaui_link_ok(struct efx_nic *efx) | |||
118 | return true; | 118 | return true; |
119 | 119 | ||
120 | /* Read link status */ | 120 | /* Read link status */ |
121 | falcon_read(efx, ®, FR_AB_XX_CORE_STAT); | 121 | efx_reado(efx, ®, FR_AB_XX_CORE_STAT); |
122 | 122 | ||
123 | align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE); | 123 | align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE); |
124 | sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT); | 124 | sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT); |
@@ -129,7 +129,7 @@ bool falcon_xaui_link_ok(struct efx_nic *efx) | |||
129 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES); | 129 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES); |
130 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES); | 130 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES); |
131 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES); | 131 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES); |
132 | falcon_write(efx, ®, FR_AB_XX_CORE_STAT); | 132 | efx_writeo(efx, ®, FR_AB_XX_CORE_STAT); |
133 | 133 | ||
134 | /* If the link is up, then check the phy side of the xaui link */ | 134 | /* If the link is up, then check the phy side of the xaui link */ |
135 | if (efx->link_up && link_ok) | 135 | if (efx->link_up && link_ok) |
@@ -150,7 +150,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx) | |||
150 | FRF_AB_XM_RX_JUMBO_MODE, 1, | 150 | FRF_AB_XM_RX_JUMBO_MODE, 1, |
151 | FRF_AB_XM_TX_STAT_EN, 1, | 151 | FRF_AB_XM_TX_STAT_EN, 1, |
152 | FRF_AB_XM_RX_STAT_EN, 1); | 152 | FRF_AB_XM_RX_STAT_EN, 1); |
153 | falcon_write(efx, ®, FR_AB_XM_GLB_CFG); | 153 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
154 | 154 | ||
155 | /* Configure TX */ | 155 | /* Configure TX */ |
156 | EFX_POPULATE_DWORD_6(reg, | 156 | EFX_POPULATE_DWORD_6(reg, |
@@ -160,7 +160,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx) | |||
160 | FRF_AB_XM_TXCRC, 1, | 160 | FRF_AB_XM_TXCRC, 1, |
161 | FRF_AB_XM_FCNTL, 1, | 161 | FRF_AB_XM_FCNTL, 1, |
162 | FRF_AB_XM_IPG, 0x3); | 162 | FRF_AB_XM_IPG, 0x3); |
163 | falcon_write(efx, ®, FR_AB_XM_TX_CFG); | 163 | efx_writeo(efx, ®, FR_AB_XM_TX_CFG); |
164 | 164 | ||
165 | /* Configure RX */ | 165 | /* Configure RX */ |
166 | EFX_POPULATE_DWORD_5(reg, | 166 | EFX_POPULATE_DWORD_5(reg, |
@@ -169,27 +169,27 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx) | |||
169 | FRF_AB_XM_ACPT_ALL_MCAST, 1, | 169 | FRF_AB_XM_ACPT_ALL_MCAST, 1, |
170 | FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous, | 170 | FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous, |
171 | FRF_AB_XM_PASS_CRC_ERR, 1); | 171 | FRF_AB_XM_PASS_CRC_ERR, 1); |
172 | falcon_write(efx, ®, FR_AB_XM_RX_CFG); | 172 | efx_writeo(efx, ®, FR_AB_XM_RX_CFG); |
173 | 173 | ||
174 | /* Set frame length */ | 174 | /* Set frame length */ |
175 | max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); | 175 | max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); |
176 | EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len); | 176 | EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len); |
177 | falcon_write(efx, ®, FR_AB_XM_RX_PARAM); | 177 | efx_writeo(efx, ®, FR_AB_XM_RX_PARAM); |
178 | EFX_POPULATE_DWORD_2(reg, | 178 | EFX_POPULATE_DWORD_2(reg, |
179 | FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len, | 179 | FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len, |
180 | FRF_AB_XM_TX_JUMBO_MODE, 1); | 180 | FRF_AB_XM_TX_JUMBO_MODE, 1); |
181 | falcon_write(efx, ®, FR_AB_XM_TX_PARAM); | 181 | efx_writeo(efx, ®, FR_AB_XM_TX_PARAM); |
182 | 182 | ||
183 | EFX_POPULATE_DWORD_2(reg, | 183 | EFX_POPULATE_DWORD_2(reg, |
184 | FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ | 184 | FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ |
185 | FRF_AB_XM_DIS_FCNTL, !rx_fc); | 185 | FRF_AB_XM_DIS_FCNTL, !rx_fc); |
186 | falcon_write(efx, ®, FR_AB_XM_FC); | 186 | efx_writeo(efx, ®, FR_AB_XM_FC); |
187 | 187 | ||
188 | /* Set MAC address */ | 188 | /* Set MAC address */ |
189 | memcpy(®, &efx->net_dev->dev_addr[0], 4); | 189 | memcpy(®, &efx->net_dev->dev_addr[0], 4); |
190 | falcon_write(efx, ®, FR_AB_XM_ADR_LO); | 190 | efx_writeo(efx, ®, FR_AB_XM_ADR_LO); |
191 | memcpy(®, &efx->net_dev->dev_addr[4], 2); | 191 | memcpy(®, &efx->net_dev->dev_addr[4], 2); |
192 | falcon_write(efx, ®, FR_AB_XM_ADR_HI); | 192 | efx_writeo(efx, ®, FR_AB_XM_ADR_HI); |
193 | } | 193 | } |
194 | 194 | ||
195 | static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) | 195 | static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) |
@@ -205,12 +205,12 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) | |||
205 | bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; | 205 | bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; |
206 | bool reset_xgxs; | 206 | bool reset_xgxs; |
207 | 207 | ||
208 | falcon_read(efx, ®, FR_AB_XX_CORE_STAT); | 208 | efx_reado(efx, ®, FR_AB_XX_CORE_STAT); |
209 | old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN); | 209 | old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN); |
210 | old_xgmii_loopback = | 210 | old_xgmii_loopback = |
211 | EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN); | 211 | EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN); |
212 | 212 | ||
213 | falcon_read(efx, ®, FR_AB_XX_SD_CTL); | 213 | efx_reado(efx, ®, FR_AB_XX_SD_CTL); |
214 | old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA); | 214 | old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA); |
215 | 215 | ||
216 | /* The PHY driver may have turned XAUI off */ | 216 | /* The PHY driver may have turned XAUI off */ |
@@ -222,20 +222,20 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) | |||
222 | falcon_reset_xaui(efx); | 222 | falcon_reset_xaui(efx); |
223 | } | 223 | } |
224 | 224 | ||
225 | falcon_read(efx, ®, FR_AB_XX_CORE_STAT); | 225 | efx_reado(efx, ®, FR_AB_XX_CORE_STAT); |
226 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG, | 226 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG, |
227 | (xgxs_loopback || xaui_loopback) ? | 227 | (xgxs_loopback || xaui_loopback) ? |
228 | FFE_AB_XX_FORCE_SIG_ALL_LANES : 0); | 228 | FFE_AB_XX_FORCE_SIG_ALL_LANES : 0); |
229 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback); | 229 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback); |
230 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback); | 230 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback); |
231 | falcon_write(efx, ®, FR_AB_XX_CORE_STAT); | 231 | efx_writeo(efx, ®, FR_AB_XX_CORE_STAT); |
232 | 232 | ||
233 | falcon_read(efx, ®, FR_AB_XX_SD_CTL); | 233 | efx_reado(efx, ®, FR_AB_XX_SD_CTL); |
234 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback); | 234 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback); |
235 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback); | 235 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback); |
236 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback); | 236 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback); |
237 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback); | 237 | EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback); |
238 | falcon_write(efx, ®, FR_AB_XX_SD_CTL); | 238 | efx_writeo(efx, ®, FR_AB_XX_SD_CTL); |
239 | } | 239 | } |
240 | 240 | ||
241 | 241 | ||