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authorBen Hutchings <bhutchings@solarflare.com>2008-09-01 07:47:16 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-09-03 09:53:45 -0400
commit4a5b504d0c582db80813b70359b616ea30e91743 (patch)
treec3b10e411914a42c21d2a525e26eb440e37c6651 /drivers/net/sfc/falcon_hwdefs.h
parent4d566063a799231b99d9a21128634ea78b89ab72 (diff)
sfc: Export boot configuration in EEPROM through ethtool
Extend the SPI device setup code to support this. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/sfc/falcon_hwdefs.h')
-rw-r--r--drivers/net/sfc/falcon_hwdefs.h35
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/net/sfc/falcon_hwdefs.h b/drivers/net/sfc/falcon_hwdefs.h
index 6d003114eeab..626735e73429 100644
--- a/drivers/net/sfc/falcon_hwdefs.h
+++ b/drivers/net/sfc/falcon_hwdefs.h
@@ -92,6 +92,17 @@
92/* SPI host data register */ 92/* SPI host data register */
93#define EE_SPI_HDATA_REG_KER 0x0120 93#define EE_SPI_HDATA_REG_KER 0x0120
94 94
95/* SPI/VPD config register */
96#define EE_VPD_CFG_REG_KER 0x0140
97#define EE_VPD_EN_LBN 0
98#define EE_VPD_EN_WIDTH 1
99#define EE_VPD_EN_AD9_MODE_LBN 1
100#define EE_VPD_EN_AD9_MODE_WIDTH 1
101#define EE_EE_CLOCK_DIV_LBN 112
102#define EE_EE_CLOCK_DIV_WIDTH 7
103#define EE_SF_CLOCK_DIV_LBN 120
104#define EE_SF_CLOCK_DIV_WIDTH 7
105
95/* PCIE CORE ACCESS REG */ 106/* PCIE CORE ACCESS REG */
96#define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68 107#define PCIE_CORE_ADDR_PCIE_DEVICE_CTRL_STAT 0x68
97#define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70 108#define PCIE_CORE_ADDR_PCIE_LINK_CTRL_STAT 0x70
@@ -115,6 +126,9 @@
115#define STRAP_PCIE_LBN 0 126#define STRAP_PCIE_LBN 0
116#define STRAP_PCIE_WIDTH 1 127#define STRAP_PCIE_WIDTH 1
117 128
129#define BOOTED_USING_NVDEVICE_LBN 3
130#define BOOTED_USING_NVDEVICE_WIDTH 1
131
118/* GPIO control register */ 132/* GPIO control register */
119#define GPIO_CTL_REG_KER 0x0210 133#define GPIO_CTL_REG_KER 0x0210
120#define GPIO_OUTPUTS_LBN (16) 134#define GPIO_OUTPUTS_LBN (16)
@@ -1127,6 +1141,25 @@ struct falcon_nvconfig_board_v2 {
1127 __le16 board_revision; 1141 __le16 board_revision;
1128} __packed; 1142} __packed;
1129 1143
1144/* Board configuration v3 extra information */
1145struct falcon_nvconfig_board_v3 {
1146 __le32 spi_device_type[2];
1147} __packed;
1148
1149/* Bit numbers for spi_device_type */
1150#define SPI_DEV_TYPE_SIZE_LBN 0
1151#define SPI_DEV_TYPE_SIZE_WIDTH 5
1152#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
1153#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
1154#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
1155#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
1156#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
1157#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
1158#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
1159#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
1160#define SPI_DEV_TYPE_FIELD(type, field) \
1161 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(field))
1162
1130#define NVCONFIG_BASE 0x300 1163#define NVCONFIG_BASE 0x300
1131#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C 1164#define NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
1132struct falcon_nvconfig { 1165struct falcon_nvconfig {
@@ -1144,6 +1177,8 @@ struct falcon_nvconfig {
1144 __le16 board_struct_ver; 1177 __le16 board_struct_ver;
1145 __le16 board_checksum; 1178 __le16 board_checksum;
1146 struct falcon_nvconfig_board_v2 board_v2; 1179 struct falcon_nvconfig_board_v2 board_v2;
1180 efx_oword_t ee_base_page_reg; /* 0x3B0 */
1181 struct falcon_nvconfig_board_v3 board_v3;
1147} __packed; 1182} __packed;
1148 1183
1149#endif /* EFX_FALCON_HWDEFS_H */ 1184#endif /* EFX_FALCON_HWDEFS_H */