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authorBen Hutchings <bhutchings@solarflare.com>2009-11-29 10:14:45 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-29 20:23:55 -0500
commit8e730c15e1560415f33d7301b617be26050ffb86 (patch)
tree452b02c5cb91f48f392c635a0191e7dfecc9590d /drivers/net/sfc/falcon.c
parent744093c98363f8a65853aed39708c9effc80f8ff (diff)
sfc: Move shared NIC code from falcon.c to new source file nic.c
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/falcon.c')
-rw-r--r--drivers/net/sfc/falcon.c1536
1 files changed, 0 insertions, 1536 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 64b47da12326..48d28d828d46 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -29,26 +29,6 @@
29 29
30/* Hardware control for SFC4000 (aka Falcon). */ 30/* Hardware control for SFC4000 (aka Falcon). */
31 31
32/**************************************************************************
33 *
34 * Configurable values
35 *
36 **************************************************************************
37 */
38
39/* This is set to 16 for a good reason. In summary, if larger than
40 * 16, the descriptor cache holds more than a default socket
41 * buffer's worth of packets (for UDP we can only have at most one
42 * socket buffer's worth outstanding). This combined with the fact
43 * that we only get 1 TX event per descriptor cache means the NIC
44 * goes idle.
45 */
46#define TX_DC_ENTRIES 16
47#define TX_DC_ENTRIES_ORDER 1
48
49#define RX_DC_ENTRIES 64
50#define RX_DC_ENTRIES_ORDER 3
51
52static const unsigned int 32static const unsigned int
53/* "Large" EEPROM device: Atmel AT25640 or similar 33/* "Large" EEPROM device: Atmel AT25640 or similar
54 * 8 KB, 16-bit address, 32 B write block */ 34 * 8 KB, 16-bit address, 32 B write block */
@@ -63,87 +43,6 @@ default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
63 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) 43 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
64 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); 44 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
65 45
66/* RX FIFO XOFF watermark
67 *
68 * When the amount of the RX FIFO increases used increases past this
69 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
70 * This also has an effect on RX/TX arbitration
71 */
72int efx_nic_rx_xoff_thresh = -1;
73module_param_named(rx_xoff_thresh_bytes, efx_nic_rx_xoff_thresh, int, 0644);
74MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
75
76/* RX FIFO XON watermark
77 *
78 * When the amount of the RX FIFO used decreases below this
79 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
80 * This also has an effect on RX/TX arbitration
81 */
82int efx_nic_rx_xon_thresh = -1;
83module_param_named(rx_xon_thresh_bytes, efx_nic_rx_xon_thresh, int, 0644);
84MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
85
86/* If EFX_MAX_INT_ERRORS internal errors occur within
87 * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
88 * disable it.
89 */
90#define EFX_INT_ERROR_EXPIRE 3600
91#define EFX_MAX_INT_ERRORS 5
92
93/* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
94 */
95#define EFX_FLUSH_INTERVAL 10
96#define EFX_FLUSH_POLL_COUNT 100
97
98/**************************************************************************
99 *
100 * Falcon constants
101 *
102 **************************************************************************
103 */
104
105/* Size and alignment of special buffers (4KB) */
106#define EFX_BUF_SIZE 4096
107
108/* Depth of RX flush request fifo */
109#define EFX_RX_FLUSH_COUNT 4
110
111/**************************************************************************
112 *
113 * Solarstorm hardware access
114 *
115 **************************************************************************/
116
117static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
118 unsigned int index)
119{
120 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
121 value, index);
122}
123
124/* Read the current event from the event queue */
125static inline efx_qword_t *efx_event(struct efx_channel *channel,
126 unsigned int index)
127{
128 return (((efx_qword_t *) (channel->eventq.addr)) + index);
129}
130
131/* See if an event is present
132 *
133 * We check both the high and low dword of the event for all ones. We
134 * wrote all ones when we cleared the event, and no valid event can
135 * have all ones in either its high or low dwords. This approach is
136 * robust against reordering.
137 *
138 * Note that using a single 64-bit comparison is incorrect; even
139 * though the CPU read will be atomic, the DMA write may not be.
140 */
141static inline int efx_event_present(efx_qword_t *event)
142{
143 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
144 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
145}
146
147/************************************************************************** 46/**************************************************************************
148 * 47 *
149 * I2C bus - this is a bit-bashing interface using GPIO pins 48 * I2C bus - this is a bit-bashing interface using GPIO pins
@@ -200,841 +99,6 @@ static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
200 .timeout = DIV_ROUND_UP(HZ, 20), 99 .timeout = DIV_ROUND_UP(HZ, 20),
201}; 100};
202 101
203/**************************************************************************
204 *
205 * Special buffer handling
206 * Special buffers are used for event queues and the TX and RX
207 * descriptor rings.
208 *
209 *************************************************************************/
210
211/*
212 * Initialise a special buffer
213 *
214 * This will define a buffer (previously allocated via
215 * efx_alloc_special_buffer()) in the buffer table, allowing
216 * it to be used for event queues, descriptor rings etc.
217 */
218static void
219efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
220{
221 efx_qword_t buf_desc;
222 int index;
223 dma_addr_t dma_addr;
224 int i;
225
226 EFX_BUG_ON_PARANOID(!buffer->addr);
227
228 /* Write buffer descriptors to NIC */
229 for (i = 0; i < buffer->entries; i++) {
230 index = buffer->index + i;
231 dma_addr = buffer->dma_addr + (i * 4096);
232 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
233 index, (unsigned long long)dma_addr);
234 EFX_POPULATE_QWORD_3(buf_desc,
235 FRF_AZ_BUF_ADR_REGION, 0,
236 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
237 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
238 efx_write_buf_tbl(efx, &buf_desc, index);
239 }
240}
241
242/* Unmaps a buffer and clears the buffer table entries */
243static void
244efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
245{
246 efx_oword_t buf_tbl_upd;
247 unsigned int start = buffer->index;
248 unsigned int end = (buffer->index + buffer->entries - 1);
249
250 if (!buffer->entries)
251 return;
252
253 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
254 buffer->index, buffer->index + buffer->entries - 1);
255
256 EFX_POPULATE_OWORD_4(buf_tbl_upd,
257 FRF_AZ_BUF_UPD_CMD, 0,
258 FRF_AZ_BUF_CLR_CMD, 1,
259 FRF_AZ_BUF_CLR_END_ID, end,
260 FRF_AZ_BUF_CLR_START_ID, start);
261 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
262}
263
264/*
265 * Allocate a new special buffer
266 *
267 * This allocates memory for a new buffer, clears it and allocates a
268 * new buffer ID range. It does not write into the buffer table.
269 *
270 * This call will allocate 4KB buffers, since 8KB buffers can't be
271 * used for event queues and descriptor rings.
272 */
273static int efx_alloc_special_buffer(struct efx_nic *efx,
274 struct efx_special_buffer *buffer,
275 unsigned int len)
276{
277 len = ALIGN(len, EFX_BUF_SIZE);
278
279 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
280 &buffer->dma_addr);
281 if (!buffer->addr)
282 return -ENOMEM;
283 buffer->len = len;
284 buffer->entries = len / EFX_BUF_SIZE;
285 BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1));
286
287 /* All zeros is a potentially valid event so memset to 0xff */
288 memset(buffer->addr, 0xff, len);
289
290 /* Select new buffer ID */
291 buffer->index = efx->next_buffer_table;
292 efx->next_buffer_table += buffer->entries;
293
294 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
295 "(virt %p phys %llx)\n", buffer->index,
296 buffer->index + buffer->entries - 1,
297 (u64)buffer->dma_addr, len,
298 buffer->addr, (u64)virt_to_phys(buffer->addr));
299
300 return 0;
301}
302
303static void
304efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
305{
306 if (!buffer->addr)
307 return;
308
309 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
310 "(virt %p phys %llx)\n", buffer->index,
311 buffer->index + buffer->entries - 1,
312 (u64)buffer->dma_addr, buffer->len,
313 buffer->addr, (u64)virt_to_phys(buffer->addr));
314
315 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
316 buffer->dma_addr);
317 buffer->addr = NULL;
318 buffer->entries = 0;
319}
320
321/**************************************************************************
322 *
323 * Generic buffer handling
324 * These buffers are used for interrupt status and MAC stats
325 *
326 **************************************************************************/
327
328int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
329 unsigned int len)
330{
331 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
332 &buffer->dma_addr);
333 if (!buffer->addr)
334 return -ENOMEM;
335 buffer->len = len;
336 memset(buffer->addr, 0, len);
337 return 0;
338}
339
340void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
341{
342 if (buffer->addr) {
343 pci_free_consistent(efx->pci_dev, buffer->len,
344 buffer->addr, buffer->dma_addr);
345 buffer->addr = NULL;
346 }
347}
348
349/**************************************************************************
350 *
351 * TX path
352 *
353 **************************************************************************/
354
355/* Returns a pointer to the specified transmit descriptor in the TX
356 * descriptor queue belonging to the specified channel.
357 */
358static inline efx_qword_t *
359efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index)
360{
361 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
362}
363
364/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
365static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
366{
367 unsigned write_ptr;
368 efx_dword_t reg;
369
370 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
371 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
372 efx_writed_page(tx_queue->efx, &reg,
373 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
374}
375
376
377/* For each entry inserted into the software descriptor ring, create a
378 * descriptor in the hardware TX descriptor ring (in host memory), and
379 * write a doorbell.
380 */
381void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
382{
383
384 struct efx_tx_buffer *buffer;
385 efx_qword_t *txd;
386 unsigned write_ptr;
387
388 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
389
390 do {
391 write_ptr = tx_queue->write_count & EFX_TXQ_MASK;
392 buffer = &tx_queue->buffer[write_ptr];
393 txd = efx_tx_desc(tx_queue, write_ptr);
394 ++tx_queue->write_count;
395
396 /* Create TX descriptor ring entry */
397 EFX_POPULATE_QWORD_4(*txd,
398 FSF_AZ_TX_KER_CONT, buffer->continuation,
399 FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
400 FSF_AZ_TX_KER_BUF_REGION, 0,
401 FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
402 } while (tx_queue->write_count != tx_queue->insert_count);
403
404 wmb(); /* Ensure descriptors are written before they are fetched */
405 efx_notify_tx_desc(tx_queue);
406}
407
408/* Allocate hardware resources for a TX queue */
409int efx_nic_probe_tx(struct efx_tx_queue *tx_queue)
410{
411 struct efx_nic *efx = tx_queue->efx;
412 BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 ||
413 EFX_TXQ_SIZE & EFX_TXQ_MASK);
414 return efx_alloc_special_buffer(efx, &tx_queue->txd,
415 EFX_TXQ_SIZE * sizeof(efx_qword_t));
416}
417
418void efx_nic_init_tx(struct efx_tx_queue *tx_queue)
419{
420 efx_oword_t tx_desc_ptr;
421 struct efx_nic *efx = tx_queue->efx;
422
423 tx_queue->flushed = FLUSH_NONE;
424
425 /* Pin TX descriptor ring */
426 efx_init_special_buffer(efx, &tx_queue->txd);
427
428 /* Push TX descriptor ring to card */
429 EFX_POPULATE_OWORD_10(tx_desc_ptr,
430 FRF_AZ_TX_DESCQ_EN, 1,
431 FRF_AZ_TX_ISCSI_DDIG_EN, 0,
432 FRF_AZ_TX_ISCSI_HDIG_EN, 0,
433 FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
434 FRF_AZ_TX_DESCQ_EVQ_ID,
435 tx_queue->channel->channel,
436 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
437 FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
438 FRF_AZ_TX_DESCQ_SIZE,
439 __ffs(tx_queue->txd.entries),
440 FRF_AZ_TX_DESCQ_TYPE, 0,
441 FRF_BZ_TX_NON_IP_DROP_DIS, 1);
442
443 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
444 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
445 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
446 EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
447 !csum);
448 }
449
450 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
451 tx_queue->queue);
452
453 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
454 efx_oword_t reg;
455
456 /* Only 128 bits in this register */
457 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
458
459 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
460 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
461 clear_bit_le(tx_queue->queue, (void *)&reg);
462 else
463 set_bit_le(tx_queue->queue, (void *)&reg);
464 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
465 }
466}
467
468static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue)
469{
470 struct efx_nic *efx = tx_queue->efx;
471 efx_oword_t tx_flush_descq;
472
473 tx_queue->flushed = FLUSH_PENDING;
474
475 /* Post a flush command */
476 EFX_POPULATE_OWORD_2(tx_flush_descq,
477 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
478 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
479 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
480}
481
482void efx_nic_fini_tx(struct efx_tx_queue *tx_queue)
483{
484 struct efx_nic *efx = tx_queue->efx;
485 efx_oword_t tx_desc_ptr;
486
487 /* The queue should have been flushed */
488 WARN_ON(tx_queue->flushed != FLUSH_DONE);
489
490 /* Remove TX descriptor ring from card */
491 EFX_ZERO_OWORD(tx_desc_ptr);
492 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
493 tx_queue->queue);
494
495 /* Unpin TX descriptor ring */
496 efx_fini_special_buffer(efx, &tx_queue->txd);
497}
498
499/* Free buffers backing TX queue */
500void efx_nic_remove_tx(struct efx_tx_queue *tx_queue)
501{
502 efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
503}
504
505/**************************************************************************
506 *
507 * RX path
508 *
509 **************************************************************************/
510
511/* Returns a pointer to the specified descriptor in the RX descriptor queue */
512static inline efx_qword_t *
513efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index)
514{
515 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
516}
517
518/* This creates an entry in the RX descriptor queue */
519static inline void
520efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
521{
522 struct efx_rx_buffer *rx_buf;
523 efx_qword_t *rxd;
524
525 rxd = efx_rx_desc(rx_queue, index);
526 rx_buf = efx_rx_buffer(rx_queue, index);
527 EFX_POPULATE_QWORD_3(*rxd,
528 FSF_AZ_RX_KER_BUF_SIZE,
529 rx_buf->len -
530 rx_queue->efx->type->rx_buffer_padding,
531 FSF_AZ_RX_KER_BUF_REGION, 0,
532 FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
533}
534
535/* This writes to the RX_DESC_WPTR register for the specified receive
536 * descriptor ring.
537 */
538void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue)
539{
540 efx_dword_t reg;
541 unsigned write_ptr;
542
543 while (rx_queue->notified_count != rx_queue->added_count) {
544 efx_build_rx_desc(rx_queue,
545 rx_queue->notified_count &
546 EFX_RXQ_MASK);
547 ++rx_queue->notified_count;
548 }
549
550 wmb();
551 write_ptr = rx_queue->added_count & EFX_RXQ_MASK;
552 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
553 efx_writed_page(rx_queue->efx, &reg,
554 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
555}
556
557int efx_nic_probe_rx(struct efx_rx_queue *rx_queue)
558{
559 struct efx_nic *efx = rx_queue->efx;
560 BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 ||
561 EFX_RXQ_SIZE & EFX_RXQ_MASK);
562 return efx_alloc_special_buffer(efx, &rx_queue->rxd,
563 EFX_RXQ_SIZE * sizeof(efx_qword_t));
564}
565
566void efx_nic_init_rx(struct efx_rx_queue *rx_queue)
567{
568 efx_oword_t rx_desc_ptr;
569 struct efx_nic *efx = rx_queue->efx;
570 bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
571 bool iscsi_digest_en = is_b0;
572
573 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
574 rx_queue->queue, rx_queue->rxd.index,
575 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
576
577 rx_queue->flushed = FLUSH_NONE;
578
579 /* Pin RX descriptor ring */
580 efx_init_special_buffer(efx, &rx_queue->rxd);
581
582 /* Push RX descriptor ring to card */
583 EFX_POPULATE_OWORD_10(rx_desc_ptr,
584 FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en,
585 FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en,
586 FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
587 FRF_AZ_RX_DESCQ_EVQ_ID,
588 rx_queue->channel->channel,
589 FRF_AZ_RX_DESCQ_OWNER_ID, 0,
590 FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue,
591 FRF_AZ_RX_DESCQ_SIZE,
592 __ffs(rx_queue->rxd.entries),
593 FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
594 /* For >=B0 this is scatter so disable */
595 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
596 FRF_AZ_RX_DESCQ_EN, 1);
597 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
598 rx_queue->queue);
599}
600
601static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue)
602{
603 struct efx_nic *efx = rx_queue->efx;
604 efx_oword_t rx_flush_descq;
605
606 rx_queue->flushed = FLUSH_PENDING;
607
608 /* Post a flush command */
609 EFX_POPULATE_OWORD_2(rx_flush_descq,
610 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
611 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
612 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
613}
614
615void efx_nic_fini_rx(struct efx_rx_queue *rx_queue)
616{
617 efx_oword_t rx_desc_ptr;
618 struct efx_nic *efx = rx_queue->efx;
619
620 /* The queue should already have been flushed */
621 WARN_ON(rx_queue->flushed != FLUSH_DONE);
622
623 /* Remove RX descriptor ring from card */
624 EFX_ZERO_OWORD(rx_desc_ptr);
625 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
626 rx_queue->queue);
627
628 /* Unpin RX descriptor ring */
629 efx_fini_special_buffer(efx, &rx_queue->rxd);
630}
631
632/* Free buffers backing RX queue */
633void efx_nic_remove_rx(struct efx_rx_queue *rx_queue)
634{
635 efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
636}
637
638/**************************************************************************
639 *
640 * Event queue processing
641 * Event queues are processed by per-channel tasklets.
642 *
643 **************************************************************************/
644
645/* Update a channel's event queue's read pointer (RPTR) register
646 *
647 * This writes the EVQ_RPTR_REG register for the specified channel's
648 * event queue.
649 *
650 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
651 * whereas channel->eventq_read_ptr contains the index of the "next to
652 * read" event.
653 */
654void efx_nic_eventq_read_ack(struct efx_channel *channel)
655{
656 efx_dword_t reg;
657 struct efx_nic *efx = channel->efx;
658
659 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
660 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
661 channel->channel);
662}
663
664/* Use HW to insert a SW defined event */
665void efx_generate_event(struct efx_channel *channel, efx_qword_t *event)
666{
667 efx_oword_t drv_ev_reg;
668
669 BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
670 FRF_AZ_DRV_EV_DATA_WIDTH != 64);
671 drv_ev_reg.u32[0] = event->u32[0];
672 drv_ev_reg.u32[1] = event->u32[1];
673 drv_ev_reg.u32[2] = 0;
674 drv_ev_reg.u32[3] = 0;
675 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
676 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
677}
678
679/* Handle a transmit completion event
680 *
681 * The NIC batches TX completion events; the message we receive is of
682 * the form "complete all TX events up to this index".
683 */
684static void
685efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
686{
687 unsigned int tx_ev_desc_ptr;
688 unsigned int tx_ev_q_label;
689 struct efx_tx_queue *tx_queue;
690 struct efx_nic *efx = channel->efx;
691
692 if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
693 /* Transmit completion */
694 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
695 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
696 tx_queue = &efx->tx_queue[tx_ev_q_label];
697 channel->irq_mod_score +=
698 (tx_ev_desc_ptr - tx_queue->read_count) &
699 EFX_TXQ_MASK;
700 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
701 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
702 /* Rewrite the FIFO write pointer */
703 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
704 tx_queue = &efx->tx_queue[tx_ev_q_label];
705
706 if (efx_dev_registered(efx))
707 netif_tx_lock(efx->net_dev);
708 efx_notify_tx_desc(tx_queue);
709 if (efx_dev_registered(efx))
710 netif_tx_unlock(efx->net_dev);
711 } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) &&
712 EFX_WORKAROUND_10727(efx)) {
713 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
714 } else {
715 EFX_ERR(efx, "channel %d unexpected TX event "
716 EFX_QWORD_FMT"\n", channel->channel,
717 EFX_QWORD_VAL(*event));
718 }
719}
720
721/* Detect errors included in the rx_evt_pkt_ok bit. */
722static void efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
723 const efx_qword_t *event,
724 bool *rx_ev_pkt_ok,
725 bool *discard)
726{
727 struct efx_nic *efx = rx_queue->efx;
728 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
729 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
730 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
731 bool rx_ev_other_err, rx_ev_pause_frm;
732 bool rx_ev_hdr_type, rx_ev_mcast_pkt;
733 unsigned rx_ev_pkt_type;
734
735 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
736 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
737 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
738 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
739 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
740 FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
741 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
742 FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
743 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
744 FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
745 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
746 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
747 rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
748 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
749 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
750
751 /* Every error apart from tobe_disc and pause_frm */
752 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
753 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
754 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
755
756 /* Count errors that are not in MAC stats. Ignore expected
757 * checksum errors during self-test. */
758 if (rx_ev_frm_trunc)
759 ++rx_queue->channel->n_rx_frm_trunc;
760 else if (rx_ev_tobe_disc)
761 ++rx_queue->channel->n_rx_tobe_disc;
762 else if (!efx->loopback_selftest) {
763 if (rx_ev_ip_hdr_chksum_err)
764 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
765 else if (rx_ev_tcp_udp_chksum_err)
766 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
767 }
768
769 /* The frame must be discarded if any of these are true. */
770 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
771 rx_ev_tobe_disc | rx_ev_pause_frm);
772
773 /* TOBE_DISC is expected on unicast mismatches; don't print out an
774 * error message. FRM_TRUNC indicates RXDP dropped the packet due
775 * to a FIFO overflow.
776 */
777#ifdef EFX_ENABLE_DEBUG
778 if (rx_ev_other_err) {
779 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
780 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
781 rx_queue->queue, EFX_QWORD_VAL(*event),
782 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
783 rx_ev_ip_hdr_chksum_err ?
784 " [IP_HDR_CHKSUM_ERR]" : "",
785 rx_ev_tcp_udp_chksum_err ?
786 " [TCP_UDP_CHKSUM_ERR]" : "",
787 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
788 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
789 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
790 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
791 rx_ev_pause_frm ? " [PAUSE]" : "");
792 }
793#endif
794}
795
796/* Handle receive events that are not in-order. */
797static void
798efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
799{
800 struct efx_nic *efx = rx_queue->efx;
801 unsigned expected, dropped;
802
803 expected = rx_queue->removed_count & EFX_RXQ_MASK;
804 dropped = (index - expected) & EFX_RXQ_MASK;
805 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
806 dropped, index, expected);
807
808 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
809 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
810}
811
812/* Handle a packet received event
813 *
814 * The NIC gives a "discard" flag if it's a unicast packet with the
815 * wrong destination address
816 * Also "is multicast" and "matches multicast filter" flags can be used to
817 * discard non-matching multicast packets.
818 */
819static void
820efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
821{
822 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
823 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
824 unsigned expected_ptr;
825 bool rx_ev_pkt_ok, discard = false, checksummed;
826 struct efx_rx_queue *rx_queue;
827 struct efx_nic *efx = channel->efx;
828
829 /* Basic packet information */
830 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
831 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
832 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
833 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT));
834 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1);
835 WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
836 channel->channel);
837
838 rx_queue = &efx->rx_queue[channel->channel];
839
840 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
841 expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK;
842 if (unlikely(rx_ev_desc_ptr != expected_ptr))
843 efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
844
845 if (likely(rx_ev_pkt_ok)) {
846 /* If packet is marked as OK and packet type is TCP/IP or
847 * UDP/IP, then we can rely on the hardware checksum.
848 */
849 checksummed =
850 likely(efx->rx_checksum_enabled) &&
851 (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP ||
852 rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP);
853 } else {
854 efx_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, &discard);
855 checksummed = false;
856 }
857
858 /* Detect multicast packets that didn't match the filter */
859 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
860 if (rx_ev_mcast_pkt) {
861 unsigned int rx_ev_mcast_hash_match =
862 EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
863
864 if (unlikely(!rx_ev_mcast_hash_match)) {
865 ++channel->n_rx_mcast_mismatch;
866 discard = true;
867 }
868 }
869
870 channel->irq_mod_score += 2;
871
872 /* Handle received packet */
873 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
874 checksummed, discard);
875}
876
877/* Global events are basically PHY events */
878static void
879efx_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
880{
881 struct efx_nic *efx = channel->efx;
882 bool handled = false;
883
884 if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
885 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
886 EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
887 /* Ignored */
888 handled = true;
889 }
890
891 if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
892 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
893 efx->xmac_poll_required = true;
894 handled = true;
895 }
896
897 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
898 EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
899 EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
900 EFX_ERR(efx, "channel %d seen global RX_RESET "
901 "event. Resetting.\n", channel->channel);
902
903 atomic_inc(&efx->rx_reset);
904 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
905 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
906 handled = true;
907 }
908
909 if (!handled)
910 EFX_ERR(efx, "channel %d unknown global event "
911 EFX_QWORD_FMT "\n", channel->channel,
912 EFX_QWORD_VAL(*event));
913}
914
915static void
916efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
917{
918 struct efx_nic *efx = channel->efx;
919 unsigned int ev_sub_code;
920 unsigned int ev_sub_data;
921
922 ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
923 ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
924
925 switch (ev_sub_code) {
926 case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
927 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
928 channel->channel, ev_sub_data);
929 break;
930 case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
931 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
932 channel->channel, ev_sub_data);
933 break;
934 case FSE_AZ_EVQ_INIT_DONE_EV:
935 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
936 channel->channel, ev_sub_data);
937 break;
938 case FSE_AZ_SRM_UPD_DONE_EV:
939 EFX_TRACE(efx, "channel %d SRAM update done\n",
940 channel->channel);
941 break;
942 case FSE_AZ_WAKE_UP_EV:
943 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
944 channel->channel, ev_sub_data);
945 break;
946 case FSE_AZ_TIMER_EV:
947 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
948 channel->channel, ev_sub_data);
949 break;
950 case FSE_AA_RX_RECOVER_EV:
951 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
952 "Resetting.\n", channel->channel);
953 atomic_inc(&efx->rx_reset);
954 efx_schedule_reset(efx,
955 EFX_WORKAROUND_6555(efx) ?
956 RESET_TYPE_RX_RECOVERY :
957 RESET_TYPE_DISABLE);
958 break;
959 case FSE_BZ_RX_DSC_ERROR_EV:
960 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
961 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
962 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
963 break;
964 case FSE_BZ_TX_DSC_ERROR_EV:
965 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
966 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
967 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
968 break;
969 default:
970 EFX_TRACE(efx, "channel %d unknown driver event code %d "
971 "data %04x\n", channel->channel, ev_sub_code,
972 ev_sub_data);
973 break;
974 }
975}
976
977int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota)
978{
979 unsigned int read_ptr;
980 efx_qword_t event, *p_event;
981 int ev_code;
982 int rx_packets = 0;
983
984 read_ptr = channel->eventq_read_ptr;
985
986 do {
987 p_event = efx_event(channel, read_ptr);
988 event = *p_event;
989
990 if (!efx_event_present(&event))
991 /* End of events */
992 break;
993
994 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
995 channel->channel, EFX_QWORD_VAL(event));
996
997 /* Clear this event by marking it all ones */
998 EFX_SET_QWORD(*p_event);
999
1000 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1001
1002 switch (ev_code) {
1003 case FSE_AZ_EV_CODE_RX_EV:
1004 efx_handle_rx_event(channel, &event);
1005 ++rx_packets;
1006 break;
1007 case FSE_AZ_EV_CODE_TX_EV:
1008 efx_handle_tx_event(channel, &event);
1009 break;
1010 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1011 channel->eventq_magic = EFX_QWORD_FIELD(
1012 event, FSF_AZ_DRV_GEN_EV_MAGIC);
1013 EFX_LOG(channel->efx, "channel %d received generated "
1014 "event "EFX_QWORD_FMT"\n", channel->channel,
1015 EFX_QWORD_VAL(event));
1016 break;
1017 case FSE_AZ_EV_CODE_GLOBAL_EV:
1018 efx_handle_global_event(channel, &event);
1019 break;
1020 case FSE_AZ_EV_CODE_DRIVER_EV:
1021 efx_handle_driver_event(channel, &event);
1022 break;
1023 default:
1024 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1025 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1026 ev_code, EFX_QWORD_VAL(event));
1027 }
1028
1029 /* Increment read pointer */
1030 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1031
1032 } while (rx_packets < rx_quota);
1033
1034 channel->eventq_read_ptr = read_ptr;
1035 return rx_packets;
1036}
1037
1038static void falcon_push_irq_moderation(struct efx_channel *channel) 102static void falcon_push_irq_moderation(struct efx_channel *channel)
1039{ 103{
1040 efx_dword_t timer_cmd; 104 efx_dword_t timer_cmd;
@@ -1056,135 +120,6 @@ static void falcon_push_irq_moderation(struct efx_channel *channel)
1056 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); 120 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1057 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, 121 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1058 channel->channel); 122 channel->channel);
1059
1060}
1061
1062/* Allocate buffer table entries for event queue */
1063int efx_nic_probe_eventq(struct efx_channel *channel)
1064{
1065 struct efx_nic *efx = channel->efx;
1066 BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 ||
1067 EFX_EVQ_SIZE & EFX_EVQ_MASK);
1068 return efx_alloc_special_buffer(efx, &channel->eventq,
1069 EFX_EVQ_SIZE * sizeof(efx_qword_t));
1070}
1071
1072void efx_nic_init_eventq(struct efx_channel *channel)
1073{
1074 efx_oword_t evq_ptr;
1075 struct efx_nic *efx = channel->efx;
1076
1077 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1078 channel->channel, channel->eventq.index,
1079 channel->eventq.index + channel->eventq.entries - 1);
1080
1081 /* Pin event queue buffer */
1082 efx_init_special_buffer(efx, &channel->eventq);
1083
1084 /* Fill event queue with all ones (i.e. empty events) */
1085 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1086
1087 /* Push event queue to card */
1088 EFX_POPULATE_OWORD_3(evq_ptr,
1089 FRF_AZ_EVQ_EN, 1,
1090 FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1091 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1092 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1093 channel->channel);
1094
1095 efx->type->push_irq_moderation(channel);
1096}
1097
1098void efx_nic_fini_eventq(struct efx_channel *channel)
1099{
1100 efx_oword_t eventq_ptr;
1101 struct efx_nic *efx = channel->efx;
1102
1103 /* Remove event queue from card */
1104 EFX_ZERO_OWORD(eventq_ptr);
1105 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1106 channel->channel);
1107
1108 /* Unpin event queue */
1109 efx_fini_special_buffer(efx, &channel->eventq);
1110}
1111
1112/* Free buffers backing event queue */
1113void efx_nic_remove_eventq(struct efx_channel *channel)
1114{
1115 efx_free_special_buffer(channel->efx, &channel->eventq);
1116}
1117
1118
1119/* Generates a test event on the event queue. A subsequent call to
1120 * process_eventq() should pick up the event and place the value of
1121 * "magic" into channel->eventq_magic;
1122 */
1123void efx_nic_generate_test_event(struct efx_channel *channel, unsigned int magic)
1124{
1125 efx_qword_t test_event;
1126
1127 EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE,
1128 FSE_AZ_EV_CODE_DRV_GEN_EV,
1129 FSF_AZ_DRV_GEN_EV_MAGIC, magic);
1130 efx_generate_event(channel, &test_event);
1131}
1132
1133/**************************************************************************
1134 *
1135 * Flush handling
1136 *
1137 **************************************************************************/
1138
1139
1140static void efx_poll_flush_events(struct efx_nic *efx)
1141{
1142 struct efx_channel *channel = &efx->channel[0];
1143 struct efx_tx_queue *tx_queue;
1144 struct efx_rx_queue *rx_queue;
1145 unsigned int read_ptr = channel->eventq_read_ptr;
1146 unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK;
1147
1148 do {
1149 efx_qword_t *event = efx_event(channel, read_ptr);
1150 int ev_code, ev_sub_code, ev_queue;
1151 bool ev_failed;
1152
1153 if (!efx_event_present(event))
1154 break;
1155
1156 ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE);
1157 ev_sub_code = EFX_QWORD_FIELD(*event,
1158 FSF_AZ_DRIVER_EV_SUBCODE);
1159 if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1160 ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) {
1161 ev_queue = EFX_QWORD_FIELD(*event,
1162 FSF_AZ_DRIVER_EV_SUBDATA);
1163 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1164 tx_queue = efx->tx_queue + ev_queue;
1165 tx_queue->flushed = FLUSH_DONE;
1166 }
1167 } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV &&
1168 ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) {
1169 ev_queue = EFX_QWORD_FIELD(
1170 *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1171 ev_failed = EFX_QWORD_FIELD(
1172 *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1173 if (ev_queue < efx->n_rx_queues) {
1174 rx_queue = efx->rx_queue + ev_queue;
1175 rx_queue->flushed =
1176 ev_failed ? FLUSH_FAILED : FLUSH_DONE;
1177 }
1178 }
1179
1180 /* We're about to destroy the queue anyway, so
1181 * it's ok to throw away every non-flush event */
1182 EFX_SET_QWORD(*event);
1183
1184 read_ptr = (read_ptr + 1) & EFX_EVQ_MASK;
1185 } while (read_ptr != end_ptr);
1186
1187 channel->eventq_read_ptr = read_ptr;
1188} 123}
1189 124
1190static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); 125static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
@@ -1199,123 +134,6 @@ static void falcon_prepare_flush(struct efx_nic *efx)
1199 msleep(10); 134 msleep(10);
1200} 135}
1201 136
1202/* Handle tx and rx flushes at the same time, since they run in
1203 * parallel in the hardware and there's no reason for us to
1204 * serialise them */
1205int efx_nic_flush_queues(struct efx_nic *efx)
1206{
1207 struct efx_rx_queue *rx_queue;
1208 struct efx_tx_queue *tx_queue;
1209 int i, tx_pending, rx_pending;
1210
1211 /* If necessary prepare the hardware for flushing */
1212 efx->type->prepare_flush(efx);
1213
1214 /* Flush all tx queues in parallel */
1215 efx_for_each_tx_queue(tx_queue, efx)
1216 efx_flush_tx_queue(tx_queue);
1217
1218 /* The hardware supports four concurrent rx flushes, each of which may
1219 * need to be retried if there is an outstanding descriptor fetch */
1220 for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) {
1221 rx_pending = tx_pending = 0;
1222 efx_for_each_rx_queue(rx_queue, efx) {
1223 if (rx_queue->flushed == FLUSH_PENDING)
1224 ++rx_pending;
1225 }
1226 efx_for_each_rx_queue(rx_queue, efx) {
1227 if (rx_pending == EFX_RX_FLUSH_COUNT)
1228 break;
1229 if (rx_queue->flushed == FLUSH_FAILED ||
1230 rx_queue->flushed == FLUSH_NONE) {
1231 efx_flush_rx_queue(rx_queue);
1232 ++rx_pending;
1233 }
1234 }
1235 efx_for_each_tx_queue(tx_queue, efx) {
1236 if (tx_queue->flushed != FLUSH_DONE)
1237 ++tx_pending;
1238 }
1239
1240 if (rx_pending == 0 && tx_pending == 0)
1241 return 0;
1242
1243 msleep(EFX_FLUSH_INTERVAL);
1244 efx_poll_flush_events(efx);
1245 }
1246
1247 /* Mark the queues as all flushed. We're going to return failure
1248 * leading to a reset, or fake up success anyway */
1249 efx_for_each_tx_queue(tx_queue, efx) {
1250 if (tx_queue->flushed != FLUSH_DONE)
1251 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1252 tx_queue->queue);
1253 tx_queue->flushed = FLUSH_DONE;
1254 }
1255 efx_for_each_rx_queue(rx_queue, efx) {
1256 if (rx_queue->flushed != FLUSH_DONE)
1257 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1258 rx_queue->queue);
1259 rx_queue->flushed = FLUSH_DONE;
1260 }
1261
1262 if (EFX_WORKAROUND_7803(efx))
1263 return 0;
1264
1265 return -ETIMEDOUT;
1266}
1267
1268/**************************************************************************
1269 *
1270 * Hardware interrupts
1271 * The hardware interrupt handler does very little work; all the event
1272 * queue processing is carried out by per-channel tasklets.
1273 *
1274 **************************************************************************/
1275
1276/* Enable/disable/generate interrupts */
1277static inline void efx_nic_interrupts(struct efx_nic *efx,
1278 bool enabled, bool force)
1279{
1280 efx_oword_t int_en_reg_ker;
1281
1282 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1283 FRF_AZ_KER_INT_KER, force,
1284 FRF_AZ_DRV_INT_EN_KER, enabled);
1285 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1286}
1287
1288void efx_nic_enable_interrupts(struct efx_nic *efx)
1289{
1290 struct efx_channel *channel;
1291
1292 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1293 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1294
1295 /* Enable interrupts */
1296 efx_nic_interrupts(efx, true, false);
1297
1298 /* Force processing of all the channels to get the EVQ RPTRs up to
1299 date */
1300 efx_for_each_channel(channel, efx)
1301 efx_schedule_channel(channel);
1302}
1303
1304void efx_nic_disable_interrupts(struct efx_nic *efx)
1305{
1306 /* Disable interrupts */
1307 efx_nic_interrupts(efx, false, false);
1308}
1309
1310/* Generate a test interrupt
1311 * Interrupt must already have been enabled, otherwise nasty things
1312 * may happen.
1313 */
1314void efx_nic_generate_interrupt(struct efx_nic *efx)
1315{
1316 efx_nic_interrupts(efx, true, true);
1317}
1318
1319/* Acknowledge a legacy interrupt from Falcon 137/* Acknowledge a legacy interrupt from Falcon
1320 * 138 *
1321 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. 139 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
@@ -1335,102 +153,6 @@ inline void falcon_irq_ack_a1(struct efx_nic *efx)
1335 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS); 153 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1336} 154}
1337 155
1338/* Process a fatal interrupt
1339 * Disable bus mastering ASAP and schedule a reset
1340 */
1341irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx)
1342{
1343 struct falcon_nic_data *nic_data = efx->nic_data;
1344 efx_oword_t *int_ker = efx->irq_status.addr;
1345 efx_oword_t fatal_intr;
1346 int error, mem_perr;
1347
1348 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1349 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1350
1351 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1352 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1353 EFX_OWORD_VAL(fatal_intr),
1354 error ? "disabling bus mastering" : "no recognised error");
1355 if (error == 0)
1356 goto out;
1357
1358 /* If this is a memory parity error dump which blocks are offending */
1359 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1360 if (mem_perr) {
1361 efx_oword_t reg;
1362 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1363 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1364 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1365 }
1366
1367 /* Disable both devices */
1368 pci_clear_master(efx->pci_dev);
1369 if (efx_nic_is_dual_func(efx))
1370 pci_clear_master(nic_data->pci_dev2);
1371 efx_nic_disable_interrupts(efx);
1372
1373 /* Count errors and reset or disable the NIC accordingly */
1374 if (efx->int_error_count == 0 ||
1375 time_after(jiffies, efx->int_error_expire)) {
1376 efx->int_error_count = 0;
1377 efx->int_error_expire =
1378 jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1379 }
1380 if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1381 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1382 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1383 } else {
1384 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1385 "NIC will be disabled\n");
1386 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1387 }
1388out:
1389 return IRQ_HANDLED;
1390}
1391
1392/* Handle a legacy interrupt
1393 * Acknowledges the interrupt and schedule event queue processing.
1394 */
1395static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id)
1396{
1397 struct efx_nic *efx = dev_id;
1398 efx_oword_t *int_ker = efx->irq_status.addr;
1399 irqreturn_t result = IRQ_NONE;
1400 struct efx_channel *channel;
1401 efx_dword_t reg;
1402 u32 queues;
1403 int syserr;
1404
1405 /* Read the ISR which also ACKs the interrupts */
1406 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1407 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1408
1409 /* Check to see if we have a serious error condition */
1410 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1411 if (unlikely(syserr))
1412 return efx_nic_fatal_interrupt(efx);
1413
1414 /* Schedule processing of any interrupting queues */
1415 efx_for_each_channel(channel, efx) {
1416 if ((queues & 1) ||
1417 efx_event_present(
1418 efx_event(channel, channel->eventq_read_ptr))) {
1419 efx_schedule_channel(channel);
1420 result = IRQ_HANDLED;
1421 }
1422 queues >>= 1;
1423 }
1424
1425 if (result == IRQ_HANDLED) {
1426 efx->last_irq_cpu = raw_smp_processor_id();
1427 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1428 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1429 }
1430
1431 return result;
1432}
1433
1434 156
1435irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) 157irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1436{ 158{
@@ -1477,126 +199,6 @@ irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1477 199
1478 return IRQ_HANDLED; 200 return IRQ_HANDLED;
1479} 201}
1480
1481/* Handle an MSI interrupt
1482 *
1483 * Handle an MSI hardware interrupt. This routine schedules event
1484 * queue processing. No interrupt acknowledgement cycle is necessary.
1485 * Also, we never need to check that the interrupt is for us, since
1486 * MSI interrupts cannot be shared.
1487 */
1488static irqreturn_t efx_msi_interrupt(int irq, void *dev_id)
1489{
1490 struct efx_channel *channel = dev_id;
1491 struct efx_nic *efx = channel->efx;
1492 efx_oword_t *int_ker = efx->irq_status.addr;
1493 int syserr;
1494
1495 efx->last_irq_cpu = raw_smp_processor_id();
1496 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1497 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1498
1499 /* Check to see if we have a serious error condition */
1500 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1501 if (unlikely(syserr))
1502 return efx_nic_fatal_interrupt(efx);
1503
1504 /* Schedule processing of the channel */
1505 efx_schedule_channel(channel);
1506
1507 return IRQ_HANDLED;
1508}
1509
1510
1511/* Setup RSS indirection table.
1512 * This maps from the hash value of the packet to RXQ
1513 */
1514static void efx_setup_rss_indir_table(struct efx_nic *efx)
1515{
1516 int i = 0;
1517 unsigned long offset;
1518 efx_dword_t dword;
1519
1520 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
1521 return;
1522
1523 for (offset = FR_BZ_RX_INDIRECTION_TBL;
1524 offset < FR_BZ_RX_INDIRECTION_TBL + 0x800;
1525 offset += 0x10) {
1526 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1527 i % efx->n_rx_queues);
1528 efx_writed(efx, &dword, offset);
1529 i++;
1530 }
1531}
1532
1533/* Hook interrupt handler(s)
1534 * Try MSI and then legacy interrupts.
1535 */
1536int efx_nic_init_interrupt(struct efx_nic *efx)
1537{
1538 struct efx_channel *channel;
1539 int rc;
1540
1541 if (!EFX_INT_MODE_USE_MSI(efx)) {
1542 irq_handler_t handler;
1543 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1544 handler = efx_legacy_interrupt;
1545 else
1546 handler = falcon_legacy_interrupt_a1;
1547
1548 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1549 efx->name, efx);
1550 if (rc) {
1551 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1552 efx->pci_dev->irq);
1553 goto fail1;
1554 }
1555 return 0;
1556 }
1557
1558 /* Hook MSI or MSI-X interrupt */
1559 efx_for_each_channel(channel, efx) {
1560 rc = request_irq(channel->irq, efx_msi_interrupt,
1561 IRQF_PROBE_SHARED, /* Not shared */
1562 channel->name, channel);
1563 if (rc) {
1564 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1565 goto fail2;
1566 }
1567 }
1568
1569 return 0;
1570
1571 fail2:
1572 efx_for_each_channel(channel, efx)
1573 free_irq(channel->irq, channel);
1574 fail1:
1575 return rc;
1576}
1577
1578void efx_nic_fini_interrupt(struct efx_nic *efx)
1579{
1580 struct efx_channel *channel;
1581 efx_oword_t reg;
1582
1583 /* Disable MSI/MSI-X interrupts */
1584 efx_for_each_channel(channel, efx) {
1585 if (channel->irq)
1586 free_irq(channel->irq, channel);
1587 }
1588
1589 /* ACK legacy interrupt */
1590 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
1591 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1592 else
1593 falcon_irq_ack_a1(efx);
1594
1595 /* Disable legacy interrupt */
1596 if (efx->legacy_irq)
1597 free_irq(efx->legacy_irq, efx);
1598}
1599
1600/************************************************************************** 202/**************************************************************************
1601 * 203 *
1602 * EEPROM/flash 204 * EEPROM/flash
@@ -2440,68 +1042,6 @@ static const struct efx_nic_register_test falcon_b0_register_tests[] = {
2440 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, 1042 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2441}; 1043};
2442 1044
2443static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2444 const efx_oword_t *mask)
2445{
2446 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2447 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2448}
2449
2450int efx_nic_test_registers(struct efx_nic *efx,
2451 const struct efx_nic_register_test *regs,
2452 size_t n_regs)
2453{
2454 unsigned address = 0, i, j;
2455 efx_oword_t mask, imask, original, reg, buf;
2456
2457 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2458 WARN_ON(!LOOPBACK_INTERNAL(efx));
2459
2460 for (i = 0; i < n_regs; ++i) {
2461 address = regs[i].address;
2462 mask = imask = regs[i].mask;
2463 EFX_INVERT_OWORD(imask);
2464
2465 efx_reado(efx, &original, address);
2466
2467 /* bit sweep on and off */
2468 for (j = 0; j < 128; j++) {
2469 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2470 continue;
2471
2472 /* Test this testable bit can be set in isolation */
2473 EFX_AND_OWORD(reg, original, mask);
2474 EFX_SET_OWORD32(reg, j, j, 1);
2475
2476 efx_writeo(efx, &reg, address);
2477 efx_reado(efx, &buf, address);
2478
2479 if (efx_masked_compare_oword(&reg, &buf, &mask))
2480 goto fail;
2481
2482 /* Test this testable bit can be cleared in isolation */
2483 EFX_OR_OWORD(reg, original, mask);
2484 EFX_SET_OWORD32(reg, j, j, 0);
2485
2486 efx_writeo(efx, &reg, address);
2487 efx_reado(efx, &buf, address);
2488
2489 if (efx_masked_compare_oword(&reg, &buf, &mask))
2490 goto fail;
2491 }
2492
2493 efx_writeo(efx, &original, address);
2494 }
2495
2496 return 0;
2497
2498fail:
2499 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2500 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2501 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2502 return -EIO;
2503}
2504
2505static int falcon_b0_test_registers(struct efx_nic *efx) 1045static int falcon_b0_test_registers(struct efx_nic *efx)
2506{ 1046{
2507 return efx_nic_test_registers(efx, falcon_b0_register_tests, 1047 return efx_nic_test_registers(efx, falcon_b0_register_tests,
@@ -2719,7 +1259,6 @@ static int falcon_spi_device_init(struct efx_nic *efx,
2719 return 0; 1259 return 0;
2720} 1260}
2721 1261
2722
2723static void falcon_remove_spi_devices(struct efx_nic *efx) 1262static void falcon_remove_spi_devices(struct efx_nic *efx)
2724{ 1263{
2725 kfree(efx->spi_eeprom); 1264 kfree(efx->spi_eeprom);
@@ -2789,14 +1328,6 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
2789 return rc; 1328 return rc;
2790} 1329}
2791 1330
2792u32 efx_nic_fpga_ver(struct efx_nic *efx)
2793{
2794 efx_oword_t altera_build;
2795
2796 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2797 return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
2798}
2799
2800/* Probe all SPI devices on the NIC */ 1331/* Probe all SPI devices on the NIC */
2801static void falcon_probe_spi_devices(struct efx_nic *efx) 1332static void falcon_probe_spi_devices(struct efx_nic *efx)
2802{ 1333{
@@ -3006,73 +1537,6 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
3006 efx_writeo(efx, &reg, FR_AZ_RX_CFG); 1537 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
3007} 1538}
3008 1539
3009void efx_nic_init_common(struct efx_nic *efx)
3010{
3011 efx_oword_t temp;
3012
3013 /* Set positions of descriptor caches in SRAM. */
3014 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
3015 efx->type->tx_dc_base / 8);
3016 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3017 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
3018 efx->type->rx_dc_base / 8);
3019 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3020
3021 /* Set TX descriptor cache size. */
3022 BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
3023 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3024 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3025
3026 /* Set RX descriptor cache size. Set low watermark to size-8, as
3027 * this allows most efficient prefetching.
3028 */
3029 BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
3030 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3031 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3032 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3033 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3034
3035 /* Program INT_KER address */
3036 EFX_POPULATE_OWORD_2(temp,
3037 FRF_AZ_NORM_INT_VEC_DIS_KER,
3038 EFX_INT_MODE_USE_MSI(efx),
3039 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
3040 efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
3041
3042 /* Enable all the genuinely fatal interrupts. (They are still
3043 * masked by the overall interrupt mask, controlled by
3044 * falcon_interrupts()).
3045 *
3046 * Note: All other fatal interrupts are enabled
3047 */
3048 EFX_POPULATE_OWORD_3(temp,
3049 FRF_AZ_ILL_ADR_INT_KER_EN, 1,
3050 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3051 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3052 EFX_INVERT_OWORD(temp);
3053 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3054
3055 efx_setup_rss_indir_table(efx);
3056
3057 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3058 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3059 */
3060 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3061 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3062 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3063 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
3064 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
3065 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
3066 /* Enable SW_EV to inherit in char driver - assume harmless here */
3067 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
3068 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
3069 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
3070 /* Squash TX of packets of 16 bytes or less */
3071 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
3072 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3073 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3074}
3075
3076/* This call performs hardware-specific global initialisation, such as 1540/* This call performs hardware-specific global initialisation, such as
3077 * defining the descriptor cache sizes and number of RSS channels. 1541 * defining the descriptor cache sizes and number of RSS channels.
3078 * It does not set up any buffers, descriptor rings or event queues. 1542 * It does not set up any buffers, descriptor rings or event queues.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 17:55:42 -0500