diff options
author | Ben Hutchings <bhutchings@solarflare.com> | 2009-04-14 22:48:34 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-04-14 22:48:34 -0400 |
commit | 239795adf7f1a40cf0be0e05544d37706c9b4cf9 (patch) | |
tree | bdf142e6e9a4c610f56f51b2d4842959c611fded /drivers/net/sfc/falcon.c | |
parent | 718cff1eec595ce6ab0635b8160a51ee37d9268d (diff) |
sfc: Use correct macro to set event bitfield
falcon_sim_phy_event() used EFX_OWORD_FIELD, which operates on
bitfields in 128-bit values, on an event, which is a 64-bit value.
This should be harmless - these macros always use little-endian
ordering, so it would read and write back the following 8 bytes
unchanged - but it is obviously wrong.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/falcon.c')
-rw-r--r-- | drivers/net/sfc/falcon.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c index d4629ab2c614..466a8abb0053 100644 --- a/drivers/net/sfc/falcon.c +++ b/drivers/net/sfc/falcon.c | |||
@@ -1176,9 +1176,9 @@ void falcon_sim_phy_event(struct efx_nic *efx) | |||
1176 | 1176 | ||
1177 | EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE); | 1177 | EFX_POPULATE_QWORD_1(phy_event, EV_CODE, GLOBAL_EV_DECODE); |
1178 | if (EFX_IS10G(efx)) | 1178 | if (EFX_IS10G(efx)) |
1179 | EFX_SET_OWORD_FIELD(phy_event, XG_PHY_INTR, 1); | 1179 | EFX_SET_QWORD_FIELD(phy_event, XG_PHY_INTR, 1); |
1180 | else | 1180 | else |
1181 | EFX_SET_OWORD_FIELD(phy_event, G_PHY0_INTR, 1); | 1181 | EFX_SET_QWORD_FIELD(phy_event, G_PHY0_INTR, 1); |
1182 | 1182 | ||
1183 | falcon_generate_event(&efx->channel[0], &phy_event); | 1183 | falcon_generate_event(&efx->channel[0], &phy_event); |
1184 | } | 1184 | } |