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authorBen Hutchings <bhutchings@solarflare.com>2010-06-23 07:31:28 -0400
committerDavid S. Miller <davem@davemloft.net>2010-06-25 01:13:24 -0400
commit39c9cf07077146b14ab077a0e27c869c6f0e6199 (patch)
treee30b746b36ebb36af8776658e8ce3f8bcd4e118d /drivers/net/sfc/falcon.c
parent2822235278c6385191a590c63098e728d0062987 (diff)
sfc: Record hardware RX hash on each skb where possible
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/sfc/falcon.c')
-rw-r--r--drivers/net/sfc/falcon.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 92d38ede6bef..5a40145f6584 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -1581,6 +1581,7 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
1581 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); 1581 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1582 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); 1582 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1583 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); 1583 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1584 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1584 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); 1585 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1585 } 1586 }
1586 /* Always enable XOFF signal from RX FIFO. We enable 1587 /* Always enable XOFF signal from RX FIFO. We enable
@@ -1861,6 +1862,7 @@ struct efx_nic_type falcon_b0_nic_type = {
1861 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, 1862 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1862 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, 1863 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1863 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), 1864 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1865 .rx_buffer_hash_size = 0x10,
1864 .rx_buffer_padding = 0, 1866 .rx_buffer_padding = 0,
1865 .max_interrupt_mode = EFX_INT_MODE_MSIX, 1867 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1866 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy 1868 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
@@ -1868,7 +1870,7 @@ struct efx_nic_type falcon_b0_nic_type = {
1868 * channels */ 1870 * channels */
1869 .tx_dc_base = 0x130000, 1871 .tx_dc_base = 0x130000,
1870 .rx_dc_base = 0x100000, 1872 .rx_dc_base = 0x100000,
1871 .offload_features = NETIF_F_IP_CSUM, 1873 .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH,
1872 .reset_world_flags = ETH_RESET_IRQ, 1874 .reset_world_flags = ETH_RESET_IRQ,
1873}; 1875};
1874 1876