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authorPaul Mackerras <paulus@samba.org>2005-10-30 21:37:12 -0500
committerPaul Mackerras <paulus@samba.org>2005-10-30 21:37:12 -0500
commit23fd07750a789a66fe88cf173d52a18f1a387da4 (patch)
tree06fdd6df35fdb835abdaa9b754d62f6b84b97250 /drivers/net/sb1250-mac.c
parentbd787d438a59266af3c9f6351644c85ef1dd21fe (diff)
parented28f96ac1960f30f818374d65be71d2fdf811b0 (diff)
Merge ../linux-2.6 by hand
Diffstat (limited to 'drivers/net/sb1250-mac.c')
-rw-r--r--drivers/net/sb1250-mac.c1384
1 files changed, 694 insertions, 690 deletions
diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c
index 7abd55a4fb21..aa4ca1821759 100644
--- a/drivers/net/sb1250-mac.c
+++ b/drivers/net/sb1250-mac.c
@@ -10,7 +10,7 @@
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details. 12 * GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software 15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
@@ -118,8 +118,6 @@ MODULE_PARM_DESC(int_timeout, "Timeout value");
118 ********************************************************************* */ 118 ********************************************************************* */
119 119
120 120
121typedef unsigned long sbmac_port_t;
122
123typedef enum { sbmac_speed_auto, sbmac_speed_10, 121typedef enum { sbmac_speed_auto, sbmac_speed_10,
124 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t; 122 sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
125 123
@@ -129,7 +127,7 @@ typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
129typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame, 127typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
130 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t; 128 sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
131 129
132typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on, 130typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
133 sbmac_state_broken } sbmac_state_t; 131 sbmac_state_broken } sbmac_state_t;
134 132
135 133
@@ -144,17 +142,13 @@ typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
144 142
145#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) 143#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
146 144
147#define SBMAC_READCSR(t) __raw_readq((unsigned long)t)
148#define SBMAC_WRITECSR(t,v) __raw_writeq(v, (unsigned long)t)
149
150
151#define SBMAC_MAX_TXDESCR 32 145#define SBMAC_MAX_TXDESCR 32
152#define SBMAC_MAX_RXDESCR 32 146#define SBMAC_MAX_RXDESCR 32
153 147
154#define ETHER_ALIGN 2 148#define ETHER_ALIGN 2
155#define ETHER_ADDR_LEN 6 149#define ETHER_ADDR_LEN 6
156#define ENET_PACKET_SIZE 1518 150#define ENET_PACKET_SIZE 1518
157/*#define ENET_PACKET_SIZE 9216 */ 151/*#define ENET_PACKET_SIZE 9216 */
158 152
159/********************************************************************** 153/**********************************************************************
160 * DMA Descriptor structure 154 * DMA Descriptor structure
@@ -172,12 +166,12 @@ typedef unsigned long paddr_t;
172 ********************************************************************* */ 166 ********************************************************************* */
173 167
174typedef struct sbmacdma_s { 168typedef struct sbmacdma_s {
175 169
176 /* 170 /*
177 * This stuff is used to identify the channel and the registers 171 * This stuff is used to identify the channel and the registers
178 * associated with it. 172 * associated with it.
179 */ 173 */
180 174
181 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */ 175 struct sbmac_softc *sbdma_eth; /* back pointer to associated MAC */
182 int sbdma_channel; /* channel number */ 176 int sbdma_channel; /* channel number */
183 int sbdma_txdir; /* direction (1=transmit) */ 177 int sbdma_txdir; /* direction (1=transmit) */
@@ -187,21 +181,21 @@ typedef struct sbmacdma_s {
187 int sbdma_int_timeout; /* # usec rx/tx interrupt */ 181 int sbdma_int_timeout; /* # usec rx/tx interrupt */
188#endif 182#endif
189 183
190 sbmac_port_t sbdma_config0; /* DMA config register 0 */ 184 volatile void __iomem *sbdma_config0; /* DMA config register 0 */
191 sbmac_port_t sbdma_config1; /* DMA config register 1 */ 185 volatile void __iomem *sbdma_config1; /* DMA config register 1 */
192 sbmac_port_t sbdma_dscrbase; /* Descriptor base address */ 186 volatile void __iomem *sbdma_dscrbase; /* Descriptor base address */
193 sbmac_port_t sbdma_dscrcnt; /* Descriptor count register */ 187 volatile void __iomem *sbdma_dscrcnt; /* Descriptor count register */
194 sbmac_port_t sbdma_curdscr; /* current descriptor address */ 188 volatile void __iomem *sbdma_curdscr; /* current descriptor address */
195 189
196 /* 190 /*
197 * This stuff is for maintenance of the ring 191 * This stuff is for maintenance of the ring
198 */ 192 */
199 193
200 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */ 194 sbdmadscr_t *sbdma_dscrtable; /* base of descriptor table */
201 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */ 195 sbdmadscr_t *sbdma_dscrtable_end; /* end of descriptor table */
202 196
203 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */ 197 struct sk_buff **sbdma_ctxtable; /* context table, one per descr */
204 198
205 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */ 199 paddr_t sbdma_dscrtable_phys; /* and also the phys addr */
206 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */ 200 sbdmadscr_t *sbdma_addptr; /* next dscr for sw to add */
207 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */ 201 sbdmadscr_t *sbdma_remptr; /* next dscr for sw to remove */
@@ -213,15 +207,15 @@ typedef struct sbmacdma_s {
213 ********************************************************************* */ 207 ********************************************************************* */
214 208
215struct sbmac_softc { 209struct sbmac_softc {
216 210
217 /* 211 /*
218 * Linux-specific things 212 * Linux-specific things
219 */ 213 */
220 214
221 struct net_device *sbm_dev; /* pointer to linux device */ 215 struct net_device *sbm_dev; /* pointer to linux device */
222 spinlock_t sbm_lock; /* spin lock */ 216 spinlock_t sbm_lock; /* spin lock */
223 struct timer_list sbm_timer; /* for monitoring MII */ 217 struct timer_list sbm_timer; /* for monitoring MII */
224 struct net_device_stats sbm_stats; 218 struct net_device_stats sbm_stats;
225 int sbm_devflags; /* current device flags */ 219 int sbm_devflags; /* current device flags */
226 220
227 int sbm_phy_oldbmsr; 221 int sbm_phy_oldbmsr;
@@ -229,31 +223,31 @@ struct sbmac_softc {
229 int sbm_phy_oldk1stsr; 223 int sbm_phy_oldk1stsr;
230 int sbm_phy_oldlinkstat; 224 int sbm_phy_oldlinkstat;
231 int sbm_buffersize; 225 int sbm_buffersize;
232 226
233 unsigned char sbm_phys[2]; 227 unsigned char sbm_phys[2];
234 228
235 /* 229 /*
236 * Controller-specific things 230 * Controller-specific things
237 */ 231 */
238 232
239 unsigned long sbm_base; /* MAC's base address */ 233 volatile void __iomem *sbm_base; /* MAC's base address */
240 sbmac_state_t sbm_state; /* current state */ 234 sbmac_state_t sbm_state; /* current state */
241 235
242 sbmac_port_t sbm_macenable; /* MAC Enable Register */ 236 volatile void __iomem *sbm_macenable; /* MAC Enable Register */
243 sbmac_port_t sbm_maccfg; /* MAC Configuration Register */ 237 volatile void __iomem *sbm_maccfg; /* MAC Configuration Register */
244 sbmac_port_t sbm_fifocfg; /* FIFO configuration register */ 238 volatile void __iomem *sbm_fifocfg; /* FIFO configuration register */
245 sbmac_port_t sbm_framecfg; /* Frame configuration register */ 239 volatile void __iomem *sbm_framecfg; /* Frame configuration register */
246 sbmac_port_t sbm_rxfilter; /* receive filter register */ 240 volatile void __iomem *sbm_rxfilter; /* receive filter register */
247 sbmac_port_t sbm_isr; /* Interrupt status register */ 241 volatile void __iomem *sbm_isr; /* Interrupt status register */
248 sbmac_port_t sbm_imr; /* Interrupt mask register */ 242 volatile void __iomem *sbm_imr; /* Interrupt mask register */
249 sbmac_port_t sbm_mdio; /* MDIO register */ 243 volatile void __iomem *sbm_mdio; /* MDIO register */
250 244
251 sbmac_speed_t sbm_speed; /* current speed */ 245 sbmac_speed_t sbm_speed; /* current speed */
252 sbmac_duplex_t sbm_duplex; /* current duplex */ 246 sbmac_duplex_t sbm_duplex; /* current duplex */
253 sbmac_fc_t sbm_fc; /* current flow control setting */ 247 sbmac_fc_t sbm_fc; /* current flow control setting */
254 248
255 unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; 249 unsigned char sbm_hwaddr[ETHER_ADDR_LEN];
256 250
257 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */ 251 sbmacdma_t sbm_txdma; /* for now, only use channel 0 */
258 sbmacdma_t sbm_rxdma; 252 sbmacdma_t sbm_rxdma;
259 int rx_hw_checksum; 253 int rx_hw_checksum;
@@ -302,6 +296,7 @@ static void sbmac_set_rx_mode(struct net_device *dev);
302static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 296static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
303static int sbmac_close(struct net_device *dev); 297static int sbmac_close(struct net_device *dev);
304static int sbmac_mii_poll(struct sbmac_softc *s,int noisy); 298static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
299static int sbmac_mii_probe(struct net_device *dev);
305 300
306static void sbmac_mii_sync(struct sbmac_softc *s); 301static void sbmac_mii_sync(struct sbmac_softc *s);
307static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt); 302static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
@@ -439,6 +434,9 @@ static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
439 434
440#define MII_BMCR 0x00 /* Basic mode control register (rw) */ 435#define MII_BMCR 0x00 /* Basic mode control register (rw) */
441#define MII_BMSR 0x01 /* Basic mode status register (ro) */ 436#define MII_BMSR 0x01 /* Basic mode status register (ro) */
437#define MII_PHYIDR1 0x02
438#define MII_PHYIDR2 0x03
439
442#define MII_K1STSR 0x0A /* 1K Status Register (ro) */ 440#define MII_K1STSR 0x0A /* 1K Status Register (ro) */
443#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */ 441#define MII_ANLPAR 0x05 /* Autonegotiation lnk partner abilities (rw) */
444 442
@@ -450,13 +448,13 @@ static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
450 448
451/********************************************************************** 449/**********************************************************************
452 * SBMAC_MII_SYNC(s) 450 * SBMAC_MII_SYNC(s)
453 * 451 *
454 * Synchronize with the MII - send a pattern of bits to the MII 452 * Synchronize with the MII - send a pattern of bits to the MII
455 * that will guarantee that it is ready to accept a command. 453 * that will guarantee that it is ready to accept a command.
456 * 454 *
457 * Input parameters: 455 * Input parameters:
458 * s - sbmac structure 456 * s - sbmac structure
459 * 457 *
460 * Return value: 458 * Return value:
461 * nothing 459 * nothing
462 ********************************************************************* */ 460 ********************************************************************* */
@@ -467,25 +465,25 @@ static void sbmac_mii_sync(struct sbmac_softc *s)
467 uint64_t bits; 465 uint64_t bits;
468 int mac_mdio_genc; 466 int mac_mdio_genc;
469 467
470 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC; 468 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
471 469
472 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; 470 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
473 471
474 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc); 472 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
475 473
476 for (cnt = 0; cnt < 32; cnt++) { 474 for (cnt = 0; cnt < 32; cnt++) {
477 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc); 475 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
478 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc); 476 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
479 } 477 }
480} 478}
481 479
482/********************************************************************** 480/**********************************************************************
483 * SBMAC_MII_SENDDATA(s,data,bitcnt) 481 * SBMAC_MII_SENDDATA(s,data,bitcnt)
484 * 482 *
485 * Send some bits to the MII. The bits to be sent are right- 483 * Send some bits to the MII. The bits to be sent are right-
486 * justified in the 'data' parameter. 484 * justified in the 'data' parameter.
487 * 485 *
488 * Input parameters: 486 * Input parameters:
489 * s - sbmac structure 487 * s - sbmac structure
490 * data - data to send 488 * data - data to send
491 * bitcnt - number of bits to send 489 * bitcnt - number of bits to send
@@ -498,20 +496,20 @@ static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitc
498 unsigned int curmask; 496 unsigned int curmask;
499 int mac_mdio_genc; 497 int mac_mdio_genc;
500 498
501 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC; 499 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
502 500
503 bits = M_MAC_MDIO_DIR_OUTPUT; 501 bits = M_MAC_MDIO_DIR_OUTPUT;
504 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc); 502 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
505 503
506 curmask = 1 << (bitcnt - 1); 504 curmask = 1 << (bitcnt - 1);
507 505
508 for (i = 0; i < bitcnt; i++) { 506 for (i = 0; i < bitcnt; i++) {
509 if (data & curmask) 507 if (data & curmask)
510 bits |= M_MAC_MDIO_OUT; 508 bits |= M_MAC_MDIO_OUT;
511 else bits &= ~M_MAC_MDIO_OUT; 509 else bits &= ~M_MAC_MDIO_OUT;
512 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc); 510 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
513 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc); 511 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
514 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc); 512 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
515 curmask >>= 1; 513 curmask >>= 1;
516 } 514 }
517} 515}
@@ -520,14 +518,14 @@ static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitc
520 518
521/********************************************************************** 519/**********************************************************************
522 * SBMAC_MII_READ(s,phyaddr,regidx) 520 * SBMAC_MII_READ(s,phyaddr,regidx)
523 * 521 *
524 * Read a PHY register. 522 * Read a PHY register.
525 * 523 *
526 * Input parameters: 524 * Input parameters:
527 * s - sbmac structure 525 * s - sbmac structure
528 * phyaddr - PHY's address 526 * phyaddr - PHY's address
529 * regidx = index of register to read 527 * regidx = index of register to read
530 * 528 *
531 * Return value: 529 * Return value:
532 * value read, or 0 if an error occurred. 530 * value read, or 0 if an error occurred.
533 ********************************************************************* */ 531 ********************************************************************* */
@@ -543,9 +541,9 @@ static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
543 * Synchronize ourselves so that the PHY knows the next 541 * Synchronize ourselves so that the PHY knows the next
544 * thing coming down is a command 542 * thing coming down is a command
545 */ 543 */
546 544
547 sbmac_mii_sync(s); 545 sbmac_mii_sync(s);
548 546
549 /* 547 /*
550 * Send the data to the PHY. The sequence is 548 * Send the data to the PHY. The sequence is
551 * a "start" command (2 bits) 549 * a "start" command (2 bits)
@@ -553,59 +551,55 @@ static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
553 * the PHY addr (5 bits) 551 * the PHY addr (5 bits)
554 * the register index (5 bits) 552 * the register index (5 bits)
555 */ 553 */
556 554
557 sbmac_mii_senddata(s,MII_COMMAND_START, 2); 555 sbmac_mii_senddata(s,MII_COMMAND_START, 2);
558 sbmac_mii_senddata(s,MII_COMMAND_READ, 2); 556 sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
559 sbmac_mii_senddata(s,phyaddr, 5); 557 sbmac_mii_senddata(s,phyaddr, 5);
560 sbmac_mii_senddata(s,regidx, 5); 558 sbmac_mii_senddata(s,regidx, 5);
561 559
562 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC; 560 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
563 561
564 /* 562 /*
565 * Switch the port around without a clock transition. 563 * Switch the port around without a clock transition.
566 */ 564 */
567 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc); 565 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
568 566
569 /* 567 /*
570 * Send out a clock pulse to signal we want the status 568 * Send out a clock pulse to signal we want the status
571 */ 569 */
572 570
573 SBMAC_WRITECSR(s->sbm_mdio, 571 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
574 M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc); 572 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
575 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc); 573
576 574 /*
577 /*
578 * If an error occurred, the PHY will signal '1' back 575 * If an error occurred, the PHY will signal '1' back
579 */ 576 */
580 error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN; 577 error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
581 578
582 /* 579 /*
583 * Issue an 'idle' clock pulse, but keep the direction 580 * Issue an 'idle' clock pulse, but keep the direction
584 * the same. 581 * the same.
585 */ 582 */
586 SBMAC_WRITECSR(s->sbm_mdio, 583 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
587 M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc); 584 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
588 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc); 585
589
590 regval = 0; 586 regval = 0;
591 587
592 for (idx = 0; idx < 16; idx++) { 588 for (idx = 0; idx < 16; idx++) {
593 regval <<= 1; 589 regval <<= 1;
594 590
595 if (error == 0) { 591 if (error == 0) {
596 if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN) 592 if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
597 regval |= 1; 593 regval |= 1;
598 } 594 }
599 595
600 SBMAC_WRITECSR(s->sbm_mdio, 596 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
601 M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc); 597 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
602 SBMAC_WRITECSR(s->sbm_mdio,
603 M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
604 } 598 }
605 599
606 /* Switch back to output */ 600 /* Switch back to output */
607 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc); 601 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
608 602
609 if (error == 0) 603 if (error == 0)
610 return regval; 604 return regval;
611 return 0; 605 return 0;
@@ -614,15 +608,15 @@ static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
614 608
615/********************************************************************** 609/**********************************************************************
616 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval) 610 * SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
617 * 611 *
618 * Write a value to a PHY register. 612 * Write a value to a PHY register.
619 * 613 *
620 * Input parameters: 614 * Input parameters:
621 * s - sbmac structure 615 * s - sbmac structure
622 * phyaddr - PHY to use 616 * phyaddr - PHY to use
623 * regidx - register within the PHY 617 * regidx - register within the PHY
624 * regval - data to write to register 618 * regval - data to write to register
625 * 619 *
626 * Return value: 620 * Return value:
627 * nothing 621 * nothing
628 ********************************************************************* */ 622 ********************************************************************* */
@@ -633,7 +627,7 @@ static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
633 int mac_mdio_genc; 627 int mac_mdio_genc;
634 628
635 sbmac_mii_sync(s); 629 sbmac_mii_sync(s);
636 630
637 sbmac_mii_senddata(s,MII_COMMAND_START,2); 631 sbmac_mii_senddata(s,MII_COMMAND_START,2);
638 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2); 632 sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
639 sbmac_mii_senddata(s,phyaddr, 5); 633 sbmac_mii_senddata(s,phyaddr, 5);
@@ -641,27 +635,27 @@ static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
641 sbmac_mii_senddata(s,MII_COMMAND_ACK,2); 635 sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
642 sbmac_mii_senddata(s,regval,16); 636 sbmac_mii_senddata(s,regval,16);
643 637
644 mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC; 638 mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
645 639
646 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc); 640 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
647} 641}
648 642
649 643
650 644
651/********************************************************************** 645/**********************************************************************
652 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) 646 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
653 * 647 *
654 * Initialize a DMA channel context. Since there are potentially 648 * Initialize a DMA channel context. Since there are potentially
655 * eight DMA channels per MAC, it's nice to do this in a standard 649 * eight DMA channels per MAC, it's nice to do this in a standard
656 * way. 650 * way.
657 * 651 *
658 * Input parameters: 652 * Input parameters:
659 * d - sbmacdma_t structure (DMA channel context) 653 * d - sbmacdma_t structure (DMA channel context)
660 * s - sbmac_softc structure (pointer to a MAC) 654 * s - sbmac_softc structure (pointer to a MAC)
661 * chan - channel number (0..1 right now) 655 * chan - channel number (0..1 right now)
662 * txrx - Identifies DMA_TX or DMA_RX for channel direction 656 * txrx - Identifies DMA_TX or DMA_RX for channel direction
663 * maxdescr - number of descriptors 657 * maxdescr - number of descriptors
664 * 658 *
665 * Return value: 659 * Return value:
666 * nothing 660 * nothing
667 ********************************************************************* */ 661 ********************************************************************* */
@@ -672,101 +666,87 @@ static void sbdma_initctx(sbmacdma_t *d,
672 int txrx, 666 int txrx,
673 int maxdescr) 667 int maxdescr)
674{ 668{
675 /* 669 /*
676 * Save away interesting stuff in the structure 670 * Save away interesting stuff in the structure
677 */ 671 */
678 672
679 d->sbdma_eth = s; 673 d->sbdma_eth = s;
680 d->sbdma_channel = chan; 674 d->sbdma_channel = chan;
681 d->sbdma_txdir = txrx; 675 d->sbdma_txdir = txrx;
682 676
683#if 0 677#if 0
684 /* RMON clearing */ 678 /* RMON clearing */
685 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; 679 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
686#endif 680#endif
687 681
688 SBMAC_WRITECSR(IOADDR( 682 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
689 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0); 683 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
690 SBMAC_WRITECSR(IOADDR( 684 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
691 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0); 685 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
692 SBMAC_WRITECSR(IOADDR( 686 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
693 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0); 687 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
694 SBMAC_WRITECSR(IOADDR( 688 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
695 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0); 689 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
696 SBMAC_WRITECSR(IOADDR( 690 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
697 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0); 691 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
698 SBMAC_WRITECSR(IOADDR( 692 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
699 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0); 693 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
700 SBMAC_WRITECSR(IOADDR( 694 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
701 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0); 695 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
702 SBMAC_WRITECSR(IOADDR( 696 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
703 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0); 697 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
704 SBMAC_WRITECSR(IOADDR( 698 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
705 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0); 699 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
706 SBMAC_WRITECSR(IOADDR( 700 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
707 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0); 701 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
708 SBMAC_WRITECSR(IOADDR( 702 __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
709 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0); 703
710 SBMAC_WRITECSR(IOADDR( 704 /*
711 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0); 705 * initialize register pointers
712 SBMAC_WRITECSR(IOADDR( 706 */
713 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0); 707
714 SBMAC_WRITECSR(IOADDR( 708 d->sbdma_config0 =
715 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
716 SBMAC_WRITECSR(IOADDR(
717 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
718 SBMAC_WRITECSR(IOADDR(
719 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
720 SBMAC_WRITECSR(IOADDR(
721 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
722 SBMAC_WRITECSR(IOADDR(
723 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
724 SBMAC_WRITECSR(IOADDR(
725 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
726 SBMAC_WRITECSR(IOADDR(
727 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
728 SBMAC_WRITECSR(IOADDR(
729 A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
730
731 /*
732 * initialize register pointers
733 */
734
735 d->sbdma_config0 =
736 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); 709 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
737 d->sbdma_config1 = 710 d->sbdma_config1 =
738 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); 711 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
739 d->sbdma_dscrbase = 712 d->sbdma_dscrbase =
740 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); 713 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
741 d->sbdma_dscrcnt = 714 d->sbdma_dscrcnt =
742 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); 715 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
743 d->sbdma_curdscr = 716 d->sbdma_curdscr =
744 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); 717 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
745 718
746 /* 719 /*
747 * Allocate memory for the ring 720 * Allocate memory for the ring
748 */ 721 */
749 722
750 d->sbdma_maxdescr = maxdescr; 723 d->sbdma_maxdescr = maxdescr;
751 724
752 d->sbdma_dscrtable = (sbdmadscr_t *) 725 d->sbdma_dscrtable = (sbdmadscr_t *)
753 kmalloc(d->sbdma_maxdescr*sizeof(sbdmadscr_t), GFP_KERNEL); 726 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
754 727
728 /*
729 * The descriptor table must be aligned to at least 16 bytes or the
730 * MAC will corrupt it.
731 */
732 d->sbdma_dscrtable = (sbdmadscr_t *)
733 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
734
755 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t)); 735 memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
756 736
757 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 737 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
758 738
759 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); 739 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
760 740
761 /* 741 /*
762 * And context table 742 * And context table
763 */ 743 */
764 744
765 d->sbdma_ctxtable = (struct sk_buff **) 745 d->sbdma_ctxtable = (struct sk_buff **)
766 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL); 746 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
767 747
768 memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *)); 748 memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
769 749
770#ifdef CONFIG_SBMAC_COALESCE 750#ifdef CONFIG_SBMAC_COALESCE
771 /* 751 /*
772 * Setup Rx/Tx DMA coalescing defaults 752 * Setup Rx/Tx DMA coalescing defaults
@@ -777,7 +757,7 @@ static void sbdma_initctx(sbmacdma_t *d,
777 } else { 757 } else {
778 d->sbdma_int_pktcnt = 1; 758 d->sbdma_int_pktcnt = 1;
779 } 759 }
780 760
781 if ( int_timeout ) { 761 if ( int_timeout ) {
782 d->sbdma_int_timeout = int_timeout; 762 d->sbdma_int_timeout = int_timeout;
783 } else { 763 } else {
@@ -789,13 +769,13 @@ static void sbdma_initctx(sbmacdma_t *d,
789 769
790/********************************************************************** 770/**********************************************************************
791 * SBDMA_CHANNEL_START(d) 771 * SBDMA_CHANNEL_START(d)
792 * 772 *
793 * Initialize the hardware registers for a DMA channel. 773 * Initialize the hardware registers for a DMA channel.
794 * 774 *
795 * Input parameters: 775 * Input parameters:
796 * d - DMA channel to init (context must be previously init'd 776 * d - DMA channel to init (context must be previously init'd
797 * rxtx - DMA_RX or DMA_TX depending on what type of channel 777 * rxtx - DMA_RX or DMA_TX depending on what type of channel
798 * 778 *
799 * Return value: 779 * Return value:
800 * nothing 780 * nothing
801 ********************************************************************* */ 781 ********************************************************************* */
@@ -805,24 +785,21 @@ static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
805 /* 785 /*
806 * Turn on the DMA channel 786 * Turn on the DMA channel
807 */ 787 */
808 788
809#ifdef CONFIG_SBMAC_COALESCE 789#ifdef CONFIG_SBMAC_COALESCE
810 SBMAC_WRITECSR(d->sbdma_config1, 790 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
811 V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | 791 0, d->sbdma_config1);
812 0); 792 __raw_writeq(M_DMA_EOP_INT_EN |
813 SBMAC_WRITECSR(d->sbdma_config0,
814 M_DMA_EOP_INT_EN |
815 V_DMA_RINGSZ(d->sbdma_maxdescr) | 793 V_DMA_RINGSZ(d->sbdma_maxdescr) |
816 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | 794 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
817 0); 795 0, d->sbdma_config0);
818#else 796#else
819 SBMAC_WRITECSR(d->sbdma_config1,0); 797 __raw_writeq(0, d->sbdma_config1);
820 SBMAC_WRITECSR(d->sbdma_config0, 798 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
821 V_DMA_RINGSZ(d->sbdma_maxdescr) | 799 0, d->sbdma_config0);
822 0);
823#endif 800#endif
824 801
825 SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys); 802 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
826 803
827 /* 804 /*
828 * Initialize ring pointers 805 * Initialize ring pointers
@@ -834,12 +811,12 @@ static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
834 811
835/********************************************************************** 812/**********************************************************************
836 * SBDMA_CHANNEL_STOP(d) 813 * SBDMA_CHANNEL_STOP(d)
837 * 814 *
838 * Initialize the hardware registers for a DMA channel. 815 * Initialize the hardware registers for a DMA channel.
839 * 816 *
840 * Input parameters: 817 * Input parameters:
841 * d - DMA channel to init (context must be previously init'd 818 * d - DMA channel to init (context must be previously init'd
842 * 819 *
843 * Return value: 820 * Return value:
844 * nothing 821 * nothing
845 ********************************************************************* */ 822 ********************************************************************* */
@@ -849,44 +826,44 @@ static void sbdma_channel_stop(sbmacdma_t *d)
849 /* 826 /*
850 * Turn off the DMA channel 827 * Turn off the DMA channel
851 */ 828 */
852 829
853 SBMAC_WRITECSR(d->sbdma_config1,0); 830 __raw_writeq(0, d->sbdma_config1);
854 831
855 SBMAC_WRITECSR(d->sbdma_dscrbase,0); 832 __raw_writeq(0, d->sbdma_dscrbase);
856 833
857 SBMAC_WRITECSR(d->sbdma_config0,0); 834 __raw_writeq(0, d->sbdma_config0);
858 835
859 /* 836 /*
860 * Zero ring pointers 837 * Zero ring pointers
861 */ 838 */
862 839
863 d->sbdma_addptr = 0; 840 d->sbdma_addptr = NULL;
864 d->sbdma_remptr = 0; 841 d->sbdma_remptr = NULL;
865} 842}
866 843
867static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset) 844static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
868{ 845{
869 unsigned long addr; 846 unsigned long addr;
870 unsigned long newaddr; 847 unsigned long newaddr;
871 848
872 addr = (unsigned long) skb->data; 849 addr = (unsigned long) skb->data;
873 850
874 newaddr = (addr + power2 - 1) & ~(power2 - 1); 851 newaddr = (addr + power2 - 1) & ~(power2 - 1);
875 852
876 skb_reserve(skb,newaddr-addr+offset); 853 skb_reserve(skb,newaddr-addr+offset);
877} 854}
878 855
879 856
880/********************************************************************** 857/**********************************************************************
881 * SBDMA_ADD_RCVBUFFER(d,sb) 858 * SBDMA_ADD_RCVBUFFER(d,sb)
882 * 859 *
883 * Add a buffer to the specified DMA channel. For receive channels, 860 * Add a buffer to the specified DMA channel. For receive channels,
884 * this queues a buffer for inbound packets. 861 * this queues a buffer for inbound packets.
885 * 862 *
886 * Input parameters: 863 * Input parameters:
887 * d - DMA channel descriptor 864 * d - DMA channel descriptor
888 * sb - sk_buff to add, or NULL if we should allocate one 865 * sb - sk_buff to add, or NULL if we should allocate one
889 * 866 *
890 * Return value: 867 * Return value:
891 * 0 if buffer could not be added (ring is full) 868 * 0 if buffer could not be added (ring is full)
892 * 1 if buffer added successfully 869 * 1 if buffer added successfully
@@ -899,24 +876,24 @@ static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
899 sbdmadscr_t *nextdsc; 876 sbdmadscr_t *nextdsc;
900 struct sk_buff *sb_new = NULL; 877 struct sk_buff *sb_new = NULL;
901 int pktsize = ENET_PACKET_SIZE; 878 int pktsize = ENET_PACKET_SIZE;
902 879
903 /* get pointer to our current place in the ring */ 880 /* get pointer to our current place in the ring */
904 881
905 dsc = d->sbdma_addptr; 882 dsc = d->sbdma_addptr;
906 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 883 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
907 884
908 /* 885 /*
909 * figure out if the ring is full - if the next descriptor 886 * figure out if the ring is full - if the next descriptor
910 * is the same as the one that we're going to remove from 887 * is the same as the one that we're going to remove from
911 * the ring, the ring is full 888 * the ring, the ring is full
912 */ 889 */
913 890
914 if (nextdsc == d->sbdma_remptr) { 891 if (nextdsc == d->sbdma_remptr) {
915 return -ENOSPC; 892 return -ENOSPC;
916 } 893 }
917 894
918 /* 895 /*
919 * Allocate a sk_buff if we don't already have one. 896 * Allocate a sk_buff if we don't already have one.
920 * If we do have an sk_buff, reset it so that it's empty. 897 * If we do have an sk_buff, reset it so that it's empty.
921 * 898 *
922 * Note: sk_buffs don't seem to be guaranteed to have any sort 899 * Note: sk_buffs don't seem to be guaranteed to have any sort
@@ -925,7 +902,7 @@ static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
925 * 902 *
926 * 1. the data does not start in the middle of a cache line. 903 * 1. the data does not start in the middle of a cache line.
927 * 2. The data does not end in the middle of a cache line 904 * 2. The data does not end in the middle of a cache line
928 * 3. The buffer can be aligned such that the IP addresses are 905 * 3. The buffer can be aligned such that the IP addresses are
929 * naturally aligned. 906 * naturally aligned.
930 * 907 *
931 * Remember, the SOCs MAC writes whole cache lines at a time, 908 * Remember, the SOCs MAC writes whole cache lines at a time,
@@ -933,7 +910,7 @@ static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
933 * data portion starts in the middle of a cache line, the SOC 910 * data portion starts in the middle of a cache line, the SOC
934 * DMA will trash the beginning (and ending) portions. 911 * DMA will trash the beginning (and ending) portions.
935 */ 912 */
936 913
937 if (sb == NULL) { 914 if (sb == NULL) {
938 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); 915 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
939 if (sb_new == NULL) { 916 if (sb_new == NULL) {
@@ -949,23 +926,22 @@ static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
949 } 926 }
950 else { 927 else {
951 sb_new = sb; 928 sb_new = sb;
952 /* 929 /*
953 * nothing special to reinit buffer, it's already aligned 930 * nothing special to reinit buffer, it's already aligned
954 * and sb->data already points to a good place. 931 * and sb->data already points to a good place.
955 */ 932 */
956 } 933 }
957 934
958 /* 935 /*
959 * fill in the descriptor 936 * fill in the descriptor
960 */ 937 */
961 938
962#ifdef CONFIG_SBMAC_COALESCE 939#ifdef CONFIG_SBMAC_COALESCE
963 /* 940 /*
964 * Do not interrupt per DMA transfer. 941 * Do not interrupt per DMA transfer.
965 */ 942 */
966 dsc->dscr_a = virt_to_phys(sb_new->data) | 943 dsc->dscr_a = virt_to_phys(sb_new->data) |
967 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 944 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
968 0;
969#else 945#else
970 dsc->dscr_a = virt_to_phys(sb_new->data) | 946 dsc->dscr_a = virt_to_phys(sb_new->data) |
971 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 947 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
@@ -974,38 +950,38 @@ static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
974 950
975 /* receiving: no options */ 951 /* receiving: no options */
976 dsc->dscr_b = 0; 952 dsc->dscr_b = 0;
977 953
978 /* 954 /*
979 * fill in the context 955 * fill in the context
980 */ 956 */
981 957
982 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; 958 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
983 959
984 /* 960 /*
985 * point at next packet 961 * point at next packet
986 */ 962 */
987 963
988 d->sbdma_addptr = nextdsc; 964 d->sbdma_addptr = nextdsc;
989 965
990 /* 966 /*
991 * Give the buffer to the DMA engine. 967 * Give the buffer to the DMA engine.
992 */ 968 */
993 969
994 SBMAC_WRITECSR(d->sbdma_dscrcnt,1); 970 __raw_writeq(1, d->sbdma_dscrcnt);
995 971
996 return 0; /* we did it */ 972 return 0; /* we did it */
997} 973}
998 974
999/********************************************************************** 975/**********************************************************************
1000 * SBDMA_ADD_TXBUFFER(d,sb) 976 * SBDMA_ADD_TXBUFFER(d,sb)
1001 * 977 *
1002 * Add a transmit buffer to the specified DMA channel, causing a 978 * Add a transmit buffer to the specified DMA channel, causing a
1003 * transmit to start. 979 * transmit to start.
1004 * 980 *
1005 * Input parameters: 981 * Input parameters:
1006 * d - DMA channel descriptor 982 * d - DMA channel descriptor
1007 * sb - sk_buff to add 983 * sb - sk_buff to add
1008 * 984 *
1009 * Return value: 985 * Return value:
1010 * 0 transmit queued successfully 986 * 0 transmit queued successfully
1011 * otherwise error code 987 * otherwise error code
@@ -1019,70 +995,70 @@ static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1019 uint64_t phys; 995 uint64_t phys;
1020 uint64_t ncb; 996 uint64_t ncb;
1021 int length; 997 int length;
1022 998
1023 /* get pointer to our current place in the ring */ 999 /* get pointer to our current place in the ring */
1024 1000
1025 dsc = d->sbdma_addptr; 1001 dsc = d->sbdma_addptr;
1026 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 1002 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1027 1003
1028 /* 1004 /*
1029 * figure out if the ring is full - if the next descriptor 1005 * figure out if the ring is full - if the next descriptor
1030 * is the same as the one that we're going to remove from 1006 * is the same as the one that we're going to remove from
1031 * the ring, the ring is full 1007 * the ring, the ring is full
1032 */ 1008 */
1033 1009
1034 if (nextdsc == d->sbdma_remptr) { 1010 if (nextdsc == d->sbdma_remptr) {
1035 return -ENOSPC; 1011 return -ENOSPC;
1036 } 1012 }
1037 1013
1038 /* 1014 /*
1039 * Under Linux, it's not necessary to copy/coalesce buffers 1015 * Under Linux, it's not necessary to copy/coalesce buffers
1040 * like it is on NetBSD. We think they're all contiguous, 1016 * like it is on NetBSD. We think they're all contiguous,
1041 * but that may not be true for GBE. 1017 * but that may not be true for GBE.
1042 */ 1018 */
1043 1019
1044 length = sb->len; 1020 length = sb->len;
1045 1021
1046 /* 1022 /*
1047 * fill in the descriptor. Note that the number of cache 1023 * fill in the descriptor. Note that the number of cache
1048 * blocks in the descriptor is the number of blocks 1024 * blocks in the descriptor is the number of blocks
1049 * *spanned*, so we need to add in the offset (if any) 1025 * *spanned*, so we need to add in the offset (if any)
1050 * while doing the calculation. 1026 * while doing the calculation.
1051 */ 1027 */
1052 1028
1053 phys = virt_to_phys(sb->data); 1029 phys = virt_to_phys(sb->data);
1054 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); 1030 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1055 1031
1056 dsc->dscr_a = phys | 1032 dsc->dscr_a = phys |
1057 V_DMA_DSCRA_A_SIZE(ncb) | 1033 V_DMA_DSCRA_A_SIZE(ncb) |
1058#ifndef CONFIG_SBMAC_COALESCE 1034#ifndef CONFIG_SBMAC_COALESCE
1059 M_DMA_DSCRA_INTERRUPT | 1035 M_DMA_DSCRA_INTERRUPT |
1060#endif 1036#endif
1061 M_DMA_ETHTX_SOP; 1037 M_DMA_ETHTX_SOP;
1062 1038
1063 /* transmitting: set outbound options and length */ 1039 /* transmitting: set outbound options and length */
1064 1040
1065 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 1041 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1066 V_DMA_DSCRB_PKT_SIZE(length); 1042 V_DMA_DSCRB_PKT_SIZE(length);
1067 1043
1068 /* 1044 /*
1069 * fill in the context 1045 * fill in the context
1070 */ 1046 */
1071 1047
1072 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; 1048 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1073 1049
1074 /* 1050 /*
1075 * point at next packet 1051 * point at next packet
1076 */ 1052 */
1077 1053
1078 d->sbdma_addptr = nextdsc; 1054 d->sbdma_addptr = nextdsc;
1079 1055
1080 /* 1056 /*
1081 * Give the buffer to the DMA engine. 1057 * Give the buffer to the DMA engine.
1082 */ 1058 */
1083 1059
1084 SBMAC_WRITECSR(d->sbdma_dscrcnt,1); 1060 __raw_writeq(1, d->sbdma_dscrcnt);
1085 1061
1086 return 0; /* we did it */ 1062 return 0; /* we did it */
1087} 1063}
1088 1064
@@ -1091,12 +1067,12 @@ static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1091 1067
1092/********************************************************************** 1068/**********************************************************************
1093 * SBDMA_EMPTYRING(d) 1069 * SBDMA_EMPTYRING(d)
1094 * 1070 *
1095 * Free all allocated sk_buffs on the specified DMA channel; 1071 * Free all allocated sk_buffs on the specified DMA channel;
1096 * 1072 *
1097 * Input parameters: 1073 * Input parameters:
1098 * d - DMA channel 1074 * d - DMA channel
1099 * 1075 *
1100 * Return value: 1076 * Return value:
1101 * nothing 1077 * nothing
1102 ********************************************************************* */ 1078 ********************************************************************* */
@@ -1105,7 +1081,7 @@ static void sbdma_emptyring(sbmacdma_t *d)
1105{ 1081{
1106 int idx; 1082 int idx;
1107 struct sk_buff *sb; 1083 struct sk_buff *sb;
1108 1084
1109 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 1085 for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1110 sb = d->sbdma_ctxtable[idx]; 1086 sb = d->sbdma_ctxtable[idx];
1111 if (sb) { 1087 if (sb) {
@@ -1118,13 +1094,13 @@ static void sbdma_emptyring(sbmacdma_t *d)
1118 1094
1119/********************************************************************** 1095/**********************************************************************
1120 * SBDMA_FILLRING(d) 1096 * SBDMA_FILLRING(d)
1121 * 1097 *
1122 * Fill the specified DMA channel (must be receive channel) 1098 * Fill the specified DMA channel (must be receive channel)
1123 * with sk_buffs 1099 * with sk_buffs
1124 * 1100 *
1125 * Input parameters: 1101 * Input parameters:
1126 * d - DMA channel 1102 * d - DMA channel
1127 * 1103 *
1128 * Return value: 1104 * Return value:
1129 * nothing 1105 * nothing
1130 ********************************************************************* */ 1106 ********************************************************************* */
@@ -1132,7 +1108,7 @@ static void sbdma_emptyring(sbmacdma_t *d)
1132static void sbdma_fillring(sbmacdma_t *d) 1108static void sbdma_fillring(sbmacdma_t *d)
1133{ 1109{
1134 int idx; 1110 int idx;
1135 1111
1136 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) { 1112 for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1137 if (sbdma_add_rcvbuffer(d,NULL) != 0) 1113 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1138 break; 1114 break;
@@ -1142,16 +1118,16 @@ static void sbdma_fillring(sbmacdma_t *d)
1142 1118
1143/********************************************************************** 1119/**********************************************************************
1144 * SBDMA_RX_PROCESS(sc,d) 1120 * SBDMA_RX_PROCESS(sc,d)
1145 * 1121 *
1146 * Process "completed" receive buffers on the specified DMA channel. 1122 * Process "completed" receive buffers on the specified DMA channel.
1147 * Note that this isn't really ideal for priority channels, since 1123 * Note that this isn't really ideal for priority channels, since
1148 * it processes all of the packets on a given channel before 1124 * it processes all of the packets on a given channel before
1149 * returning. 1125 * returning.
1150 * 1126 *
1151 * Input parameters: 1127 * Input parameters:
1152 * sc - softc structure 1128 * sc - softc structure
1153 * d - DMA channel context 1129 * d - DMA channel context
1154 * 1130 *
1155 * Return value: 1131 * Return value:
1156 * nothing 1132 * nothing
1157 ********************************************************************* */ 1133 ********************************************************************* */
@@ -1163,56 +1139,56 @@ static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1163 sbdmadscr_t *dsc; 1139 sbdmadscr_t *dsc;
1164 struct sk_buff *sb; 1140 struct sk_buff *sb;
1165 int len; 1141 int len;
1166 1142
1167 for (;;) { 1143 for (;;) {
1168 /* 1144 /*
1169 * figure out where we are (as an index) and where 1145 * figure out where we are (as an index) and where
1170 * the hardware is (also as an index) 1146 * the hardware is (also as an index)
1171 * 1147 *
1172 * This could be done faster if (for example) the 1148 * This could be done faster if (for example) the
1173 * descriptor table was page-aligned and contiguous in 1149 * descriptor table was page-aligned and contiguous in
1174 * both virtual and physical memory -- you could then 1150 * both virtual and physical memory -- you could then
1175 * just compare the low-order bits of the virtual address 1151 * just compare the low-order bits of the virtual address
1176 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1152 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1177 */ 1153 */
1178 1154
1179 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1155 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1180 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1156 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1181 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 1157 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1182 1158
1183 /* 1159 /*
1184 * If they're the same, that means we've processed all 1160 * If they're the same, that means we've processed all
1185 * of the descriptors up to (but not including) the one that 1161 * of the descriptors up to (but not including) the one that
1186 * the hardware is working on right now. 1162 * the hardware is working on right now.
1187 */ 1163 */
1188 1164
1189 if (curidx == hwidx) 1165 if (curidx == hwidx)
1190 break; 1166 break;
1191 1167
1192 /* 1168 /*
1193 * Otherwise, get the packet's sk_buff ptr back 1169 * Otherwise, get the packet's sk_buff ptr back
1194 */ 1170 */
1195 1171
1196 dsc = &(d->sbdma_dscrtable[curidx]); 1172 dsc = &(d->sbdma_dscrtable[curidx]);
1197 sb = d->sbdma_ctxtable[curidx]; 1173 sb = d->sbdma_ctxtable[curidx];
1198 d->sbdma_ctxtable[curidx] = NULL; 1174 d->sbdma_ctxtable[curidx] = NULL;
1199 1175
1200 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 1176 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1201 1177
1202 /* 1178 /*
1203 * Check packet status. If good, process it. 1179 * Check packet status. If good, process it.
1204 * If not, silently drop it and put it back on the 1180 * If not, silently drop it and put it back on the
1205 * receive ring. 1181 * receive ring.
1206 */ 1182 */
1207 1183
1208 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) { 1184 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1209 1185
1210 /* 1186 /*
1211 * Add a new buffer to replace the old one. If we fail 1187 * Add a new buffer to replace the old one. If we fail
1212 * to allocate a buffer, we're going to drop this 1188 * to allocate a buffer, we're going to drop this
1213 * packet and put it right back on the receive ring. 1189 * packet and put it right back on the receive ring.
1214 */ 1190 */
1215 1191
1216 if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) { 1192 if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1217 sc->sbm_stats.rx_dropped++; 1193 sc->sbm_stats.rx_dropped++;
1218 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */ 1194 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
@@ -1221,7 +1197,7 @@ static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1221 * Set length into the packet 1197 * Set length into the packet
1222 */ 1198 */
1223 skb_put(sb,len); 1199 skb_put(sb,len);
1224 1200
1225 /* 1201 /*
1226 * Buffer has been replaced on the 1202 * Buffer has been replaced on the
1227 * receive ring. Pass the buffer to 1203 * receive ring. Pass the buffer to
@@ -1240,7 +1216,7 @@ static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1240 sb->ip_summed = CHECKSUM_NONE; 1216 sb->ip_summed = CHECKSUM_NONE;
1241 } 1217 }
1242 } 1218 }
1243 1219
1244 netif_rx(sb); 1220 netif_rx(sb);
1245 } 1221 }
1246 } else { 1222 } else {
@@ -1251,14 +1227,14 @@ static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1251 sc->sbm_stats.rx_errors++; 1227 sc->sbm_stats.rx_errors++;
1252 sbdma_add_rcvbuffer(d,sb); 1228 sbdma_add_rcvbuffer(d,sb);
1253 } 1229 }
1254 1230
1255 1231
1256 /* 1232 /*
1257 * .. and advance to the next buffer. 1233 * .. and advance to the next buffer.
1258 */ 1234 */
1259 1235
1260 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1236 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1261 1237
1262 } 1238 }
1263} 1239}
1264 1240
@@ -1266,17 +1242,17 @@ static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1266 1242
1267/********************************************************************** 1243/**********************************************************************
1268 * SBDMA_TX_PROCESS(sc,d) 1244 * SBDMA_TX_PROCESS(sc,d)
1269 * 1245 *
1270 * Process "completed" transmit buffers on the specified DMA channel. 1246 * Process "completed" transmit buffers on the specified DMA channel.
1271 * This is normally called within the interrupt service routine. 1247 * This is normally called within the interrupt service routine.
1272 * Note that this isn't really ideal for priority channels, since 1248 * Note that this isn't really ideal for priority channels, since
1273 * it processes all of the packets on a given channel before 1249 * it processes all of the packets on a given channel before
1274 * returning. 1250 * returning.
1275 * 1251 *
1276 * Input parameters: 1252 * Input parameters:
1277 * sc - softc structure 1253 * sc - softc structure
1278 * d - DMA channel context 1254 * d - DMA channel context
1279 * 1255 *
1280 * Return value: 1256 * Return value:
1281 * nothing 1257 * nothing
1282 ********************************************************************* */ 1258 ********************************************************************* */
@@ -1290,21 +1266,21 @@ static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1290 unsigned long flags; 1266 unsigned long flags;
1291 1267
1292 spin_lock_irqsave(&(sc->sbm_lock), flags); 1268 spin_lock_irqsave(&(sc->sbm_lock), flags);
1293 1269
1294 for (;;) { 1270 for (;;) {
1295 /* 1271 /*
1296 * figure out where we are (as an index) and where 1272 * figure out where we are (as an index) and where
1297 * the hardware is (also as an index) 1273 * the hardware is (also as an index)
1298 * 1274 *
1299 * This could be done faster if (for example) the 1275 * This could be done faster if (for example) the
1300 * descriptor table was page-aligned and contiguous in 1276 * descriptor table was page-aligned and contiguous in
1301 * both virtual and physical memory -- you could then 1277 * both virtual and physical memory -- you could then
1302 * just compare the low-order bits of the virtual address 1278 * just compare the low-order bits of the virtual address
1303 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1279 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1304 */ 1280 */
1305 1281
1306 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1282 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1307 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1283 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1308 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t)); 1284 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1309 1285
1310 /* 1286 /*
@@ -1312,75 +1288,75 @@ static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1312 * of the descriptors up to (but not including) the one that 1288 * of the descriptors up to (but not including) the one that
1313 * the hardware is working on right now. 1289 * the hardware is working on right now.
1314 */ 1290 */
1315 1291
1316 if (curidx == hwidx) 1292 if (curidx == hwidx)
1317 break; 1293 break;
1318 1294
1319 /* 1295 /*
1320 * Otherwise, get the packet's sk_buff ptr back 1296 * Otherwise, get the packet's sk_buff ptr back
1321 */ 1297 */
1322 1298
1323 dsc = &(d->sbdma_dscrtable[curidx]); 1299 dsc = &(d->sbdma_dscrtable[curidx]);
1324 sb = d->sbdma_ctxtable[curidx]; 1300 sb = d->sbdma_ctxtable[curidx];
1325 d->sbdma_ctxtable[curidx] = NULL; 1301 d->sbdma_ctxtable[curidx] = NULL;
1326 1302
1327 /* 1303 /*
1328 * Stats 1304 * Stats
1329 */ 1305 */
1330 1306
1331 sc->sbm_stats.tx_bytes += sb->len; 1307 sc->sbm_stats.tx_bytes += sb->len;
1332 sc->sbm_stats.tx_packets++; 1308 sc->sbm_stats.tx_packets++;
1333 1309
1334 /* 1310 /*
1335 * for transmits, we just free buffers. 1311 * for transmits, we just free buffers.
1336 */ 1312 */
1337 1313
1338 dev_kfree_skb_irq(sb); 1314 dev_kfree_skb_irq(sb);
1339 1315
1340 /* 1316 /*
1341 * .. and advance to the next buffer. 1317 * .. and advance to the next buffer.
1342 */ 1318 */
1343 1319
1344 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1320 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1345 1321
1346 } 1322 }
1347 1323
1348 /* 1324 /*
1349 * Decide if we should wake up the protocol or not. 1325 * Decide if we should wake up the protocol or not.
1350 * Other drivers seem to do this when we reach a low 1326 * Other drivers seem to do this when we reach a low
1351 * watermark on the transmit queue. 1327 * watermark on the transmit queue.
1352 */ 1328 */
1353 1329
1354 netif_wake_queue(d->sbdma_eth->sbm_dev); 1330 netif_wake_queue(d->sbdma_eth->sbm_dev);
1355 1331
1356 spin_unlock_irqrestore(&(sc->sbm_lock), flags); 1332 spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1357 1333
1358} 1334}
1359 1335
1360 1336
1361 1337
1362/********************************************************************** 1338/**********************************************************************
1363 * SBMAC_INITCTX(s) 1339 * SBMAC_INITCTX(s)
1364 * 1340 *
1365 * Initialize an Ethernet context structure - this is called 1341 * Initialize an Ethernet context structure - this is called
1366 * once per MAC on the 1250. Memory is allocated here, so don't 1342 * once per MAC on the 1250. Memory is allocated here, so don't
1367 * call it again from inside the ioctl routines that bring the 1343 * call it again from inside the ioctl routines that bring the
1368 * interface up/down 1344 * interface up/down
1369 * 1345 *
1370 * Input parameters: 1346 * Input parameters:
1371 * s - sbmac context structure 1347 * s - sbmac context structure
1372 * 1348 *
1373 * Return value: 1349 * Return value:
1374 * 0 1350 * 0
1375 ********************************************************************* */ 1351 ********************************************************************* */
1376 1352
1377static int sbmac_initctx(struct sbmac_softc *s) 1353static int sbmac_initctx(struct sbmac_softc *s)
1378{ 1354{
1379 1355
1380 /* 1356 /*
1381 * figure out the addresses of some ports 1357 * figure out the addresses of some ports
1382 */ 1358 */
1383 1359
1384 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; 1360 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1385 s->sbm_maccfg = s->sbm_base + R_MAC_CFG; 1361 s->sbm_maccfg = s->sbm_base + R_MAC_CFG;
1386 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; 1362 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG;
@@ -1397,29 +1373,29 @@ static int sbmac_initctx(struct sbmac_softc *s)
1397 s->sbm_phy_oldanlpar = 0; 1373 s->sbm_phy_oldanlpar = 0;
1398 s->sbm_phy_oldk1stsr = 0; 1374 s->sbm_phy_oldk1stsr = 0;
1399 s->sbm_phy_oldlinkstat = 0; 1375 s->sbm_phy_oldlinkstat = 0;
1400 1376
1401 /* 1377 /*
1402 * Initialize the DMA channels. Right now, only one per MAC is used 1378 * Initialize the DMA channels. Right now, only one per MAC is used
1403 * Note: Only do this _once_, as it allocates memory from the kernel! 1379 * Note: Only do this _once_, as it allocates memory from the kernel!
1404 */ 1380 */
1405 1381
1406 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); 1382 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1407 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); 1383 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1408 1384
1409 /* 1385 /*
1410 * initial state is OFF 1386 * initial state is OFF
1411 */ 1387 */
1412 1388
1413 s->sbm_state = sbmac_state_off; 1389 s->sbm_state = sbmac_state_off;
1414 1390
1415 /* 1391 /*
1416 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC 1392 * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1417 */ 1393 */
1418 1394
1419 s->sbm_speed = sbmac_speed_10; 1395 s->sbm_speed = sbmac_speed_10;
1420 s->sbm_duplex = sbmac_duplex_half; 1396 s->sbm_duplex = sbmac_duplex_half;
1421 s->sbm_fc = sbmac_fc_disabled; 1397 s->sbm_fc = sbmac_fc_disabled;
1422 1398
1423 return 0; 1399 return 0;
1424} 1400}
1425 1401
@@ -1430,7 +1406,7 @@ static void sbdma_uninitctx(struct sbmacdma_s *d)
1430 kfree(d->sbdma_dscrtable); 1406 kfree(d->sbdma_dscrtable);
1431 d->sbdma_dscrtable = NULL; 1407 d->sbdma_dscrtable = NULL;
1432 } 1408 }
1433 1409
1434 if (d->sbdma_ctxtable) { 1410 if (d->sbdma_ctxtable) {
1435 kfree(d->sbdma_ctxtable); 1411 kfree(d->sbdma_ctxtable);
1436 d->sbdma_ctxtable = NULL; 1412 d->sbdma_ctxtable = NULL;
@@ -1447,12 +1423,12 @@ static void sbmac_uninitctx(struct sbmac_softc *sc)
1447 1423
1448/********************************************************************** 1424/**********************************************************************
1449 * SBMAC_CHANNEL_START(s) 1425 * SBMAC_CHANNEL_START(s)
1450 * 1426 *
1451 * Start packet processing on this MAC. 1427 * Start packet processing on this MAC.
1452 * 1428 *
1453 * Input parameters: 1429 * Input parameters:
1454 * s - sbmac structure 1430 * s - sbmac structure
1455 * 1431 *
1456 * Return value: 1432 * Return value:
1457 * nothing 1433 * nothing
1458 ********************************************************************* */ 1434 ********************************************************************* */
@@ -1460,49 +1436,49 @@ static void sbmac_uninitctx(struct sbmac_softc *sc)
1460static void sbmac_channel_start(struct sbmac_softc *s) 1436static void sbmac_channel_start(struct sbmac_softc *s)
1461{ 1437{
1462 uint64_t reg; 1438 uint64_t reg;
1463 sbmac_port_t port; 1439 volatile void __iomem *port;
1464 uint64_t cfg,fifo,framecfg; 1440 uint64_t cfg,fifo,framecfg;
1465 int idx, th_value; 1441 int idx, th_value;
1466 1442
1467 /* 1443 /*
1468 * Don't do this if running 1444 * Don't do this if running
1469 */ 1445 */
1470 1446
1471 if (s->sbm_state == sbmac_state_on) 1447 if (s->sbm_state == sbmac_state_on)
1472 return; 1448 return;
1473 1449
1474 /* 1450 /*
1475 * Bring the controller out of reset, but leave it off. 1451 * Bring the controller out of reset, but leave it off.
1476 */ 1452 */
1477 1453
1478 SBMAC_WRITECSR(s->sbm_macenable,0); 1454 __raw_writeq(0, s->sbm_macenable);
1479 1455
1480 /* 1456 /*
1481 * Ignore all received packets 1457 * Ignore all received packets
1482 */ 1458 */
1483 1459
1484 SBMAC_WRITECSR(s->sbm_rxfilter,0); 1460 __raw_writeq(0, s->sbm_rxfilter);
1485 1461
1486 /* 1462 /*
1487 * Calculate values for various control registers. 1463 * Calculate values for various control registers.
1488 */ 1464 */
1489 1465
1490 cfg = M_MAC_RETRY_EN | 1466 cfg = M_MAC_RETRY_EN |
1491 M_MAC_TX_HOLD_SOP_EN | 1467 M_MAC_TX_HOLD_SOP_EN |
1492 V_MAC_TX_PAUSE_CNT_16K | 1468 V_MAC_TX_PAUSE_CNT_16K |
1493 M_MAC_AP_STAT_EN | 1469 M_MAC_AP_STAT_EN |
1494 M_MAC_FAST_SYNC | 1470 M_MAC_FAST_SYNC |
1495 M_MAC_SS_EN | 1471 M_MAC_SS_EN |
1496 0; 1472 0;
1497 1473
1498 /* 1474 /*
1499 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars 1475 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1500 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above 1476 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1501 * Use a larger RD_THRSH for gigabit 1477 * Use a larger RD_THRSH for gigabit
1502 */ 1478 */
1503 if (periph_rev >= 2) 1479 if (periph_rev >= 2)
1504 th_value = 64; 1480 th_value = 64;
1505 else 1481 else
1506 th_value = 28; 1482 th_value = 28;
1507 1483
1508 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1484 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */
@@ -1520,51 +1496,51 @@ static void sbmac_channel_start(struct sbmac_softc *s)
1520 V_MAC_BACKOFF_SEL(1); 1496 V_MAC_BACKOFF_SEL(1);
1521 1497
1522 /* 1498 /*
1523 * Clear out the hash address map 1499 * Clear out the hash address map
1524 */ 1500 */
1525 1501
1526 port = s->sbm_base + R_MAC_HASH_BASE; 1502 port = s->sbm_base + R_MAC_HASH_BASE;
1527 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1503 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1528 SBMAC_WRITECSR(port,0); 1504 __raw_writeq(0, port);
1529 port += sizeof(uint64_t); 1505 port += sizeof(uint64_t);
1530 } 1506 }
1531 1507
1532 /* 1508 /*
1533 * Clear out the exact-match table 1509 * Clear out the exact-match table
1534 */ 1510 */
1535 1511
1536 port = s->sbm_base + R_MAC_ADDR_BASE; 1512 port = s->sbm_base + R_MAC_ADDR_BASE;
1537 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1513 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1538 SBMAC_WRITECSR(port,0); 1514 __raw_writeq(0, port);
1539 port += sizeof(uint64_t); 1515 port += sizeof(uint64_t);
1540 } 1516 }
1541 1517
1542 /* 1518 /*
1543 * Clear out the DMA Channel mapping table registers 1519 * Clear out the DMA Channel mapping table registers
1544 */ 1520 */
1545 1521
1546 port = s->sbm_base + R_MAC_CHUP0_BASE; 1522 port = s->sbm_base + R_MAC_CHUP0_BASE;
1547 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1523 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1548 SBMAC_WRITECSR(port,0); 1524 __raw_writeq(0, port);
1549 port += sizeof(uint64_t); 1525 port += sizeof(uint64_t);
1550 } 1526 }
1551 1527
1552 1528
1553 port = s->sbm_base + R_MAC_CHLO0_BASE; 1529 port = s->sbm_base + R_MAC_CHLO0_BASE;
1554 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1530 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1555 SBMAC_WRITECSR(port,0); 1531 __raw_writeq(0, port);
1556 port += sizeof(uint64_t); 1532 port += sizeof(uint64_t);
1557 } 1533 }
1558 1534
1559 /* 1535 /*
1560 * Program the hardware address. It goes into the hardware-address 1536 * Program the hardware address. It goes into the hardware-address
1561 * register as well as the first filter register. 1537 * register as well as the first filter register.
1562 */ 1538 */
1563 1539
1564 reg = sbmac_addr2reg(s->sbm_hwaddr); 1540 reg = sbmac_addr2reg(s->sbm_hwaddr);
1565 1541
1566 port = s->sbm_base + R_MAC_ADDR_BASE; 1542 port = s->sbm_base + R_MAC_ADDR_BASE;
1567 SBMAC_WRITECSR(port,reg); 1543 __raw_writeq(reg, port);
1568 port = s->sbm_base + R_MAC_ETHERNET_ADDR; 1544 port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1569 1545
1570#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 1546#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
@@ -1573,108 +1549,105 @@ static void sbmac_channel_start(struct sbmac_softc *s)
1573 * destination address in the R_MAC_ETHERNET_ADDR register. 1549 * destination address in the R_MAC_ETHERNET_ADDR register.
1574 * Set the value to zero. 1550 * Set the value to zero.
1575 */ 1551 */
1576 SBMAC_WRITECSR(port,0); 1552 __raw_writeq(0, port);
1577#else 1553#else
1578 SBMAC_WRITECSR(port,reg); 1554 __raw_writeq(reg, port);
1579#endif 1555#endif
1580 1556
1581 /* 1557 /*
1582 * Set the receive filter for no packets, and write values 1558 * Set the receive filter for no packets, and write values
1583 * to the various config registers 1559 * to the various config registers
1584 */ 1560 */
1585 1561
1586 SBMAC_WRITECSR(s->sbm_rxfilter,0); 1562 __raw_writeq(0, s->sbm_rxfilter);
1587 SBMAC_WRITECSR(s->sbm_imr,0); 1563 __raw_writeq(0, s->sbm_imr);
1588 SBMAC_WRITECSR(s->sbm_framecfg,framecfg); 1564 __raw_writeq(framecfg, s->sbm_framecfg);
1589 SBMAC_WRITECSR(s->sbm_fifocfg,fifo); 1565 __raw_writeq(fifo, s->sbm_fifocfg);
1590 SBMAC_WRITECSR(s->sbm_maccfg,cfg); 1566 __raw_writeq(cfg, s->sbm_maccfg);
1591 1567
1592 /* 1568 /*
1593 * Initialize DMA channels (rings should be ok now) 1569 * Initialize DMA channels (rings should be ok now)
1594 */ 1570 */
1595 1571
1596 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); 1572 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1597 sbdma_channel_start(&(s->sbm_txdma), DMA_TX); 1573 sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1598 1574
1599 /* 1575 /*
1600 * Configure the speed, duplex, and flow control 1576 * Configure the speed, duplex, and flow control
1601 */ 1577 */
1602 1578
1603 sbmac_set_speed(s,s->sbm_speed); 1579 sbmac_set_speed(s,s->sbm_speed);
1604 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); 1580 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1605 1581
1606 /* 1582 /*
1607 * Fill the receive ring 1583 * Fill the receive ring
1608 */ 1584 */
1609 1585
1610 sbdma_fillring(&(s->sbm_rxdma)); 1586 sbdma_fillring(&(s->sbm_rxdma));
1611 1587
1612 /* 1588 /*
1613 * Turn on the rest of the bits in the enable register 1589 * Turn on the rest of the bits in the enable register
1614 */ 1590 */
1615 1591
1616 SBMAC_WRITECSR(s->sbm_macenable, 1592 __raw_writeq(M_MAC_RXDMA_EN0 |
1617 M_MAC_RXDMA_EN0 |
1618 M_MAC_TXDMA_EN0 | 1593 M_MAC_TXDMA_EN0 |
1619 M_MAC_RX_ENABLE | 1594 M_MAC_RX_ENABLE |
1620 M_MAC_TX_ENABLE); 1595 M_MAC_TX_ENABLE, s->sbm_macenable);
1621 1596
1622 1597
1623 1598
1624 1599
1625#ifdef CONFIG_SBMAC_COALESCE 1600#ifdef CONFIG_SBMAC_COALESCE
1626 /* 1601 /*
1627 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0 1602 * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1628 */ 1603 */
1629 SBMAC_WRITECSR(s->sbm_imr, 1604 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1630 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | 1605 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1631 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
1632#else 1606#else
1633 /* 1607 /*
1634 * Accept any kind of interrupt on TX and RX DMA channel 0 1608 * Accept any kind of interrupt on TX and RX DMA channel 0
1635 */ 1609 */
1636 SBMAC_WRITECSR(s->sbm_imr, 1610 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1637 (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1611 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1638 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
1639#endif 1612#endif
1640 1613
1641 /* 1614 /*
1642 * Enable receiving unicasts and broadcasts 1615 * Enable receiving unicasts and broadcasts
1643 */ 1616 */
1644 1617
1645 SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN); 1618 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1646 1619
1647 /* 1620 /*
1648 * we're running now. 1621 * we're running now.
1649 */ 1622 */
1650 1623
1651 s->sbm_state = sbmac_state_on; 1624 s->sbm_state = sbmac_state_on;
1652 1625
1653 /* 1626 /*
1654 * Program multicast addresses 1627 * Program multicast addresses
1655 */ 1628 */
1656 1629
1657 sbmac_setmulti(s); 1630 sbmac_setmulti(s);
1658 1631
1659 /* 1632 /*
1660 * If channel was in promiscuous mode before, turn that on 1633 * If channel was in promiscuous mode before, turn that on
1661 */ 1634 */
1662 1635
1663 if (s->sbm_devflags & IFF_PROMISC) { 1636 if (s->sbm_devflags & IFF_PROMISC) {
1664 sbmac_promiscuous_mode(s,1); 1637 sbmac_promiscuous_mode(s,1);
1665 } 1638 }
1666 1639
1667} 1640}
1668 1641
1669 1642
1670/********************************************************************** 1643/**********************************************************************
1671 * SBMAC_CHANNEL_STOP(s) 1644 * SBMAC_CHANNEL_STOP(s)
1672 * 1645 *
1673 * Stop packet processing on this MAC. 1646 * Stop packet processing on this MAC.
1674 * 1647 *
1675 * Input parameters: 1648 * Input parameters:
1676 * s - sbmac structure 1649 * s - sbmac structure
1677 * 1650 *
1678 * Return value: 1651 * Return value:
1679 * nothing 1652 * nothing
1680 ********************************************************************* */ 1653 ********************************************************************* */
@@ -1682,49 +1655,49 @@ static void sbmac_channel_start(struct sbmac_softc *s)
1682static void sbmac_channel_stop(struct sbmac_softc *s) 1655static void sbmac_channel_stop(struct sbmac_softc *s)
1683{ 1656{
1684 /* don't do this if already stopped */ 1657 /* don't do this if already stopped */
1685 1658
1686 if (s->sbm_state == sbmac_state_off) 1659 if (s->sbm_state == sbmac_state_off)
1687 return; 1660 return;
1688 1661
1689 /* don't accept any packets, disable all interrupts */ 1662 /* don't accept any packets, disable all interrupts */
1690 1663
1691 SBMAC_WRITECSR(s->sbm_rxfilter,0); 1664 __raw_writeq(0, s->sbm_rxfilter);
1692 SBMAC_WRITECSR(s->sbm_imr,0); 1665 __raw_writeq(0, s->sbm_imr);
1693 1666
1694 /* Turn off ticker */ 1667 /* Turn off ticker */
1695 1668
1696 /* XXX */ 1669 /* XXX */
1697 1670
1698 /* turn off receiver and transmitter */ 1671 /* turn off receiver and transmitter */
1699 1672
1700 SBMAC_WRITECSR(s->sbm_macenable,0); 1673 __raw_writeq(0, s->sbm_macenable);
1701 1674
1702 /* We're stopped now. */ 1675 /* We're stopped now. */
1703 1676
1704 s->sbm_state = sbmac_state_off; 1677 s->sbm_state = sbmac_state_off;
1705 1678
1706 /* 1679 /*
1707 * Stop DMA channels (rings should be ok now) 1680 * Stop DMA channels (rings should be ok now)
1708 */ 1681 */
1709 1682
1710 sbdma_channel_stop(&(s->sbm_rxdma)); 1683 sbdma_channel_stop(&(s->sbm_rxdma));
1711 sbdma_channel_stop(&(s->sbm_txdma)); 1684 sbdma_channel_stop(&(s->sbm_txdma));
1712 1685
1713 /* Empty the receive and transmit rings */ 1686 /* Empty the receive and transmit rings */
1714 1687
1715 sbdma_emptyring(&(s->sbm_rxdma)); 1688 sbdma_emptyring(&(s->sbm_rxdma));
1716 sbdma_emptyring(&(s->sbm_txdma)); 1689 sbdma_emptyring(&(s->sbm_txdma));
1717 1690
1718} 1691}
1719 1692
1720/********************************************************************** 1693/**********************************************************************
1721 * SBMAC_SET_CHANNEL_STATE(state) 1694 * SBMAC_SET_CHANNEL_STATE(state)
1722 * 1695 *
1723 * Set the channel's state ON or OFF 1696 * Set the channel's state ON or OFF
1724 * 1697 *
1725 * Input parameters: 1698 * Input parameters:
1726 * state - new state 1699 * state - new state
1727 * 1700 *
1728 * Return value: 1701 * Return value:
1729 * old state 1702 * old state
1730 ********************************************************************* */ 1703 ********************************************************************* */
@@ -1732,43 +1705,43 @@ static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1732 sbmac_state_t state) 1705 sbmac_state_t state)
1733{ 1706{
1734 sbmac_state_t oldstate = sc->sbm_state; 1707 sbmac_state_t oldstate = sc->sbm_state;
1735 1708
1736 /* 1709 /*
1737 * If same as previous state, return 1710 * If same as previous state, return
1738 */ 1711 */
1739 1712
1740 if (state == oldstate) { 1713 if (state == oldstate) {
1741 return oldstate; 1714 return oldstate;
1742 } 1715 }
1743 1716
1744 /* 1717 /*
1745 * If new state is ON, turn channel on 1718 * If new state is ON, turn channel on
1746 */ 1719 */
1747 1720
1748 if (state == sbmac_state_on) { 1721 if (state == sbmac_state_on) {
1749 sbmac_channel_start(sc); 1722 sbmac_channel_start(sc);
1750 } 1723 }
1751 else { 1724 else {
1752 sbmac_channel_stop(sc); 1725 sbmac_channel_stop(sc);
1753 } 1726 }
1754 1727
1755 /* 1728 /*
1756 * Return previous state 1729 * Return previous state
1757 */ 1730 */
1758 1731
1759 return oldstate; 1732 return oldstate;
1760} 1733}
1761 1734
1762 1735
1763/********************************************************************** 1736/**********************************************************************
1764 * SBMAC_PROMISCUOUS_MODE(sc,onoff) 1737 * SBMAC_PROMISCUOUS_MODE(sc,onoff)
1765 * 1738 *
1766 * Turn on or off promiscuous mode 1739 * Turn on or off promiscuous mode
1767 * 1740 *
1768 * Input parameters: 1741 * Input parameters:
1769 * sc - softc 1742 * sc - softc
1770 * onoff - 1 to turn on, 0 to turn off 1743 * onoff - 1 to turn on, 0 to turn off
1771 * 1744 *
1772 * Return value: 1745 * Return value:
1773 * nothing 1746 * nothing
1774 ********************************************************************* */ 1747 ********************************************************************* */
@@ -1776,30 +1749,30 @@ static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1776static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) 1749static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1777{ 1750{
1778 uint64_t reg; 1751 uint64_t reg;
1779 1752
1780 if (sc->sbm_state != sbmac_state_on) 1753 if (sc->sbm_state != sbmac_state_on)
1781 return; 1754 return;
1782 1755
1783 if (onoff) { 1756 if (onoff) {
1784 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1757 reg = __raw_readq(sc->sbm_rxfilter);
1785 reg |= M_MAC_ALLPKT_EN; 1758 reg |= M_MAC_ALLPKT_EN;
1786 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 1759 __raw_writeq(reg, sc->sbm_rxfilter);
1787 } 1760 }
1788 else { 1761 else {
1789 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1762 reg = __raw_readq(sc->sbm_rxfilter);
1790 reg &= ~M_MAC_ALLPKT_EN; 1763 reg &= ~M_MAC_ALLPKT_EN;
1791 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 1764 __raw_writeq(reg, sc->sbm_rxfilter);
1792 } 1765 }
1793} 1766}
1794 1767
1795/********************************************************************** 1768/**********************************************************************
1796 * SBMAC_SETIPHDR_OFFSET(sc,onoff) 1769 * SBMAC_SETIPHDR_OFFSET(sc,onoff)
1797 * 1770 *
1798 * Set the iphdr offset as 15 assuming ethernet encapsulation 1771 * Set the iphdr offset as 15 assuming ethernet encapsulation
1799 * 1772 *
1800 * Input parameters: 1773 * Input parameters:
1801 * sc - softc 1774 * sc - softc
1802 * 1775 *
1803 * Return value: 1776 * Return value:
1804 * nothing 1777 * nothing
1805 ********************************************************************* */ 1778 ********************************************************************* */
@@ -1807,12 +1780,12 @@ static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1807static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) 1780static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1808{ 1781{
1809 uint64_t reg; 1782 uint64_t reg;
1810 1783
1811 /* Hard code the off set to 15 for now */ 1784 /* Hard code the off set to 15 for now */
1812 reg = SBMAC_READCSR(sc->sbm_rxfilter); 1785 reg = __raw_readq(sc->sbm_rxfilter);
1813 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); 1786 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1814 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 1787 __raw_writeq(reg, sc->sbm_rxfilter);
1815 1788
1816 /* read system identification to determine revision */ 1789 /* read system identification to determine revision */
1817 if (periph_rev >= 2) { 1790 if (periph_rev >= 2) {
1818 sc->rx_hw_checksum = ENABLE; 1791 sc->rx_hw_checksum = ENABLE;
@@ -1824,13 +1797,13 @@ static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1824 1797
1825/********************************************************************** 1798/**********************************************************************
1826 * SBMAC_ADDR2REG(ptr) 1799 * SBMAC_ADDR2REG(ptr)
1827 * 1800 *
1828 * Convert six bytes into the 64-bit register value that 1801 * Convert six bytes into the 64-bit register value that
1829 * we typically write into the SBMAC's address/mcast registers 1802 * we typically write into the SBMAC's address/mcast registers
1830 * 1803 *
1831 * Input parameters: 1804 * Input parameters:
1832 * ptr - pointer to 6 bytes 1805 * ptr - pointer to 6 bytes
1833 * 1806 *
1834 * Return value: 1807 * Return value:
1835 * register value 1808 * register value
1836 ********************************************************************* */ 1809 ********************************************************************* */
@@ -1838,35 +1811,35 @@ static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1838static uint64_t sbmac_addr2reg(unsigned char *ptr) 1811static uint64_t sbmac_addr2reg(unsigned char *ptr)
1839{ 1812{
1840 uint64_t reg = 0; 1813 uint64_t reg = 0;
1841 1814
1842 ptr += 6; 1815 ptr += 6;
1843 1816
1844 reg |= (uint64_t) *(--ptr); 1817 reg |= (uint64_t) *(--ptr);
1845 reg <<= 8; 1818 reg <<= 8;
1846 reg |= (uint64_t) *(--ptr); 1819 reg |= (uint64_t) *(--ptr);
1847 reg <<= 8; 1820 reg <<= 8;
1848 reg |= (uint64_t) *(--ptr); 1821 reg |= (uint64_t) *(--ptr);
1849 reg <<= 8; 1822 reg <<= 8;
1850 reg |= (uint64_t) *(--ptr); 1823 reg |= (uint64_t) *(--ptr);
1851 reg <<= 8; 1824 reg <<= 8;
1852 reg |= (uint64_t) *(--ptr); 1825 reg |= (uint64_t) *(--ptr);
1853 reg <<= 8; 1826 reg <<= 8;
1854 reg |= (uint64_t) *(--ptr); 1827 reg |= (uint64_t) *(--ptr);
1855 1828
1856 return reg; 1829 return reg;
1857} 1830}
1858 1831
1859 1832
1860/********************************************************************** 1833/**********************************************************************
1861 * SBMAC_SET_SPEED(s,speed) 1834 * SBMAC_SET_SPEED(s,speed)
1862 * 1835 *
1863 * Configure LAN speed for the specified MAC. 1836 * Configure LAN speed for the specified MAC.
1864 * Warning: must be called when MAC is off! 1837 * Warning: must be called when MAC is off!
1865 * 1838 *
1866 * Input parameters: 1839 * Input parameters:
1867 * s - sbmac structure 1840 * s - sbmac structure
1868 * speed - speed to set MAC to (see sbmac_speed_t enum) 1841 * speed - speed to set MAC to (see sbmac_speed_t enum)
1869 * 1842 *
1870 * Return value: 1843 * Return value:
1871 * 1 if successful 1844 * 1 if successful
1872 * 0 indicates invalid parameters 1845 * 0 indicates invalid parameters
@@ -1880,31 +1853,31 @@ static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1880 /* 1853 /*
1881 * Save new current values 1854 * Save new current values
1882 */ 1855 */
1883 1856
1884 s->sbm_speed = speed; 1857 s->sbm_speed = speed;
1885 1858
1886 if (s->sbm_state == sbmac_state_on) 1859 if (s->sbm_state == sbmac_state_on)
1887 return 0; /* save for next restart */ 1860 return 0; /* save for next restart */
1888 1861
1889 /* 1862 /*
1890 * Read current register values 1863 * Read current register values
1891 */ 1864 */
1892 1865
1893 cfg = SBMAC_READCSR(s->sbm_maccfg); 1866 cfg = __raw_readq(s->sbm_maccfg);
1894 framecfg = SBMAC_READCSR(s->sbm_framecfg); 1867 framecfg = __raw_readq(s->sbm_framecfg);
1895 1868
1896 /* 1869 /*
1897 * Mask out the stuff we want to change 1870 * Mask out the stuff we want to change
1898 */ 1871 */
1899 1872
1900 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1873 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1901 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1874 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1902 M_MAC_SLOT_SIZE); 1875 M_MAC_SLOT_SIZE);
1903 1876
1904 /* 1877 /*
1905 * Now add in the new bits 1878 * Now add in the new bits
1906 */ 1879 */
1907 1880
1908 switch (speed) { 1881 switch (speed) {
1909 case sbmac_speed_10: 1882 case sbmac_speed_10:
1910 framecfg |= V_MAC_IFG_RX_10 | 1883 framecfg |= V_MAC_IFG_RX_10 |
@@ -1913,7 +1886,7 @@ static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1913 V_MAC_SLOT_SIZE_10; 1886 V_MAC_SLOT_SIZE_10;
1914 cfg |= V_MAC_SPEED_SEL_10MBPS; 1887 cfg |= V_MAC_SPEED_SEL_10MBPS;
1915 break; 1888 break;
1916 1889
1917 case sbmac_speed_100: 1890 case sbmac_speed_100:
1918 framecfg |= V_MAC_IFG_RX_100 | 1891 framecfg |= V_MAC_IFG_RX_100 |
1919 V_MAC_IFG_TX_100 | 1892 V_MAC_IFG_TX_100 |
@@ -1921,7 +1894,7 @@ static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1921 V_MAC_SLOT_SIZE_100; 1894 V_MAC_SLOT_SIZE_100;
1922 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1895 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1923 break; 1896 break;
1924 1897
1925 case sbmac_speed_1000: 1898 case sbmac_speed_1000:
1926 framecfg |= V_MAC_IFG_RX_1000 | 1899 framecfg |= V_MAC_IFG_RX_1000 |
1927 V_MAC_IFG_TX_1000 | 1900 V_MAC_IFG_TX_1000 |
@@ -1929,34 +1902,34 @@ static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1929 V_MAC_SLOT_SIZE_1000; 1902 V_MAC_SLOT_SIZE_1000;
1930 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1903 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1931 break; 1904 break;
1932 1905
1933 case sbmac_speed_auto: /* XXX not implemented */ 1906 case sbmac_speed_auto: /* XXX not implemented */
1934 /* fall through */ 1907 /* fall through */
1935 default: 1908 default:
1936 return 0; 1909 return 0;
1937 } 1910 }
1938 1911
1939 /* 1912 /*
1940 * Send the bits back to the hardware 1913 * Send the bits back to the hardware
1941 */ 1914 */
1942 1915
1943 SBMAC_WRITECSR(s->sbm_framecfg,framecfg); 1916 __raw_writeq(framecfg, s->sbm_framecfg);
1944 SBMAC_WRITECSR(s->sbm_maccfg,cfg); 1917 __raw_writeq(cfg, s->sbm_maccfg);
1945 1918
1946 return 1; 1919 return 1;
1947} 1920}
1948 1921
1949/********************************************************************** 1922/**********************************************************************
1950 * SBMAC_SET_DUPLEX(s,duplex,fc) 1923 * SBMAC_SET_DUPLEX(s,duplex,fc)
1951 * 1924 *
1952 * Set Ethernet duplex and flow control options for this MAC 1925 * Set Ethernet duplex and flow control options for this MAC
1953 * Warning: must be called when MAC is off! 1926 * Warning: must be called when MAC is off!
1954 * 1927 *
1955 * Input parameters: 1928 * Input parameters:
1956 * s - sbmac structure 1929 * s - sbmac structure
1957 * duplex - duplex setting (see sbmac_duplex_t) 1930 * duplex - duplex setting (see sbmac_duplex_t)
1958 * fc - flow control setting (see sbmac_fc_t) 1931 * fc - flow control setting (see sbmac_fc_t)
1959 * 1932 *
1960 * Return value: 1933 * Return value:
1961 * 1 if ok 1934 * 1 if ok
1962 * 0 if an invalid parameter combination was specified 1935 * 0 if an invalid parameter combination was specified
@@ -1965,67 +1938,67 @@ static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1965static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc) 1938static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1966{ 1939{
1967 uint64_t cfg; 1940 uint64_t cfg;
1968 1941
1969 /* 1942 /*
1970 * Save new current values 1943 * Save new current values
1971 */ 1944 */
1972 1945
1973 s->sbm_duplex = duplex; 1946 s->sbm_duplex = duplex;
1974 s->sbm_fc = fc; 1947 s->sbm_fc = fc;
1975 1948
1976 if (s->sbm_state == sbmac_state_on) 1949 if (s->sbm_state == sbmac_state_on)
1977 return 0; /* save for next restart */ 1950 return 0; /* save for next restart */
1978 1951
1979 /* 1952 /*
1980 * Read current register values 1953 * Read current register values
1981 */ 1954 */
1982 1955
1983 cfg = SBMAC_READCSR(s->sbm_maccfg); 1956 cfg = __raw_readq(s->sbm_maccfg);
1984 1957
1985 /* 1958 /*
1986 * Mask off the stuff we're about to change 1959 * Mask off the stuff we're about to change
1987 */ 1960 */
1988 1961
1989 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1962 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1990 1963
1991 1964
1992 switch (duplex) { 1965 switch (duplex) {
1993 case sbmac_duplex_half: 1966 case sbmac_duplex_half:
1994 switch (fc) { 1967 switch (fc) {
1995 case sbmac_fc_disabled: 1968 case sbmac_fc_disabled:
1996 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1969 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1997 break; 1970 break;
1998 1971
1999 case sbmac_fc_collision: 1972 case sbmac_fc_collision:
2000 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1973 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2001 break; 1974 break;
2002 1975
2003 case sbmac_fc_carrier: 1976 case sbmac_fc_carrier:
2004 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1977 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2005 break; 1978 break;
2006 1979
2007 case sbmac_fc_auto: /* XXX not implemented */ 1980 case sbmac_fc_auto: /* XXX not implemented */
2008 /* fall through */ 1981 /* fall through */
2009 case sbmac_fc_frame: /* not valid in half duplex */ 1982 case sbmac_fc_frame: /* not valid in half duplex */
2010 default: /* invalid selection */ 1983 default: /* invalid selection */
2011 return 0; 1984 return 0;
2012 } 1985 }
2013 break; 1986 break;
2014 1987
2015 case sbmac_duplex_full: 1988 case sbmac_duplex_full:
2016 switch (fc) { 1989 switch (fc) {
2017 case sbmac_fc_disabled: 1990 case sbmac_fc_disabled:
2018 cfg |= V_MAC_FC_CMD_DISABLED; 1991 cfg |= V_MAC_FC_CMD_DISABLED;
2019 break; 1992 break;
2020 1993
2021 case sbmac_fc_frame: 1994 case sbmac_fc_frame:
2022 cfg |= V_MAC_FC_CMD_ENABLED; 1995 cfg |= V_MAC_FC_CMD_ENABLED;
2023 break; 1996 break;
2024 1997
2025 case sbmac_fc_collision: /* not valid in full duplex */ 1998 case sbmac_fc_collision: /* not valid in full duplex */
2026 case sbmac_fc_carrier: /* not valid in full duplex */ 1999 case sbmac_fc_carrier: /* not valid in full duplex */
2027 case sbmac_fc_auto: /* XXX not implemented */ 2000 case sbmac_fc_auto: /* XXX not implemented */
2028 /* fall through */ 2001 /* fall through */
2029 default: 2002 default:
2030 return 0; 2003 return 0;
2031 } 2004 }
@@ -2034,13 +2007,13 @@ static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc
2034 /* XXX not implemented */ 2007 /* XXX not implemented */
2035 break; 2008 break;
2036 } 2009 }
2037 2010
2038 /* 2011 /*
2039 * Send the bits back to the hardware 2012 * Send the bits back to the hardware
2040 */ 2013 */
2041 2014
2042 SBMAC_WRITECSR(s->sbm_maccfg,cfg); 2015 __raw_writeq(cfg, s->sbm_maccfg);
2043 2016
2044 return 1; 2017 return 1;
2045} 2018}
2046 2019
@@ -2049,12 +2022,12 @@ static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc
2049 2022
2050/********************************************************************** 2023/**********************************************************************
2051 * SBMAC_INTR() 2024 * SBMAC_INTR()
2052 * 2025 *
2053 * Interrupt handler for MAC interrupts 2026 * Interrupt handler for MAC interrupts
2054 * 2027 *
2055 * Input parameters: 2028 * Input parameters:
2056 * MAC structure 2029 * MAC structure
2057 * 2030 *
2058 * Return value: 2031 * Return value:
2059 * nothing 2032 * nothing
2060 ********************************************************************* */ 2033 ********************************************************************* */
@@ -2066,27 +2039,27 @@ static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2066 int handled = 0; 2039 int handled = 0;
2067 2040
2068 for (;;) { 2041 for (;;) {
2069 2042
2070 /* 2043 /*
2071 * Read the ISR (this clears the bits in the real 2044 * Read the ISR (this clears the bits in the real
2072 * register, except for counter addr) 2045 * register, except for counter addr)
2073 */ 2046 */
2074 2047
2075 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; 2048 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2076 2049
2077 if (isr == 0) 2050 if (isr == 0)
2078 break; 2051 break;
2079 2052
2080 handled = 1; 2053 handled = 1;
2081 2054
2082 /* 2055 /*
2083 * Transmits on channel 0 2056 * Transmits on channel 0
2084 */ 2057 */
2085 2058
2086 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) { 2059 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2087 sbdma_tx_process(sc,&(sc->sbm_txdma)); 2060 sbdma_tx_process(sc,&(sc->sbm_txdma));
2088 } 2061 }
2089 2062
2090 /* 2063 /*
2091 * Receives on channel 0 2064 * Receives on channel 0
2092 */ 2065 */
@@ -2106,8 +2079,8 @@ static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2106 * EOP_SEEN here takes care of this case. 2079 * EOP_SEEN here takes care of this case.
2107 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0) 2080 * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2108 */ 2081 */
2109 2082
2110 2083
2111 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { 2084 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2112 sbdma_rx_process(sc,&(sc->sbm_rxdma)); 2085 sbdma_rx_process(sc,&(sc->sbm_rxdma));
2113 } 2086 }
@@ -2118,29 +2091,29 @@ static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2118 2091
2119/********************************************************************** 2092/**********************************************************************
2120 * SBMAC_START_TX(skb,dev) 2093 * SBMAC_START_TX(skb,dev)
2121 * 2094 *
2122 * Start output on the specified interface. Basically, we 2095 * Start output on the specified interface. Basically, we
2123 * queue as many buffers as we can until the ring fills up, or 2096 * queue as many buffers as we can until the ring fills up, or
2124 * we run off the end of the queue, whichever comes first. 2097 * we run off the end of the queue, whichever comes first.
2125 * 2098 *
2126 * Input parameters: 2099 * Input parameters:
2127 * 2100 *
2128 * 2101 *
2129 * Return value: 2102 * Return value:
2130 * nothing 2103 * nothing
2131 ********************************************************************* */ 2104 ********************************************************************* */
2132static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) 2105static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2133{ 2106{
2134 struct sbmac_softc *sc = netdev_priv(dev); 2107 struct sbmac_softc *sc = netdev_priv(dev);
2135 2108
2136 /* lock eth irq */ 2109 /* lock eth irq */
2137 spin_lock_irq (&sc->sbm_lock); 2110 spin_lock_irq (&sc->sbm_lock);
2138 2111
2139 /* 2112 /*
2140 * Put the buffer on the transmit ring. If we 2113 * Put the buffer on the transmit ring. If we
2141 * don't have room, stop the queue. 2114 * don't have room, stop the queue.
2142 */ 2115 */
2143 2116
2144 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { 2117 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2145 /* XXX save skb that we could not send */ 2118 /* XXX save skb that we could not send */
2146 netif_stop_queue(dev); 2119 netif_stop_queue(dev);
@@ -2148,24 +2121,24 @@ static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2148 2121
2149 return 1; 2122 return 1;
2150 } 2123 }
2151 2124
2152 dev->trans_start = jiffies; 2125 dev->trans_start = jiffies;
2153 2126
2154 spin_unlock_irq (&sc->sbm_lock); 2127 spin_unlock_irq (&sc->sbm_lock);
2155 2128
2156 return 0; 2129 return 0;
2157} 2130}
2158 2131
2159/********************************************************************** 2132/**********************************************************************
2160 * SBMAC_SETMULTI(sc) 2133 * SBMAC_SETMULTI(sc)
2161 * 2134 *
2162 * Reprogram the multicast table into the hardware, given 2135 * Reprogram the multicast table into the hardware, given
2163 * the list of multicasts associated with the interface 2136 * the list of multicasts associated with the interface
2164 * structure. 2137 * structure.
2165 * 2138 *
2166 * Input parameters: 2139 * Input parameters:
2167 * sc - softc 2140 * sc - softc
2168 * 2141 *
2169 * Return value: 2142 * Return value:
2170 * nothing 2143 * nothing
2171 ********************************************************************* */ 2144 ********************************************************************* */
@@ -2173,75 +2146,75 @@ static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2173static void sbmac_setmulti(struct sbmac_softc *sc) 2146static void sbmac_setmulti(struct sbmac_softc *sc)
2174{ 2147{
2175 uint64_t reg; 2148 uint64_t reg;
2176 sbmac_port_t port; 2149 volatile void __iomem *port;
2177 int idx; 2150 int idx;
2178 struct dev_mc_list *mclist; 2151 struct dev_mc_list *mclist;
2179 struct net_device *dev = sc->sbm_dev; 2152 struct net_device *dev = sc->sbm_dev;
2180 2153
2181 /* 2154 /*
2182 * Clear out entire multicast table. We do this by nuking 2155 * Clear out entire multicast table. We do this by nuking
2183 * the entire hash table and all the direct matches except 2156 * the entire hash table and all the direct matches except
2184 * the first one, which is used for our station address 2157 * the first one, which is used for our station address
2185 */ 2158 */
2186 2159
2187 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 2160 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2188 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); 2161 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2189 SBMAC_WRITECSR(port,0); 2162 __raw_writeq(0, port);
2190 } 2163 }
2191 2164
2192 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 2165 for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2193 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); 2166 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2194 SBMAC_WRITECSR(port,0); 2167 __raw_writeq(0, port);
2195 } 2168 }
2196 2169
2197 /* 2170 /*
2198 * Clear the filter to say we don't want any multicasts. 2171 * Clear the filter to say we don't want any multicasts.
2199 */ 2172 */
2200 2173
2201 reg = SBMAC_READCSR(sc->sbm_rxfilter); 2174 reg = __raw_readq(sc->sbm_rxfilter);
2202 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2175 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2203 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 2176 __raw_writeq(reg, sc->sbm_rxfilter);
2204 2177
2205 if (dev->flags & IFF_ALLMULTI) { 2178 if (dev->flags & IFF_ALLMULTI) {
2206 /* 2179 /*
2207 * Enable ALL multicasts. Do this by inverting the 2180 * Enable ALL multicasts. Do this by inverting the
2208 * multicast enable bit. 2181 * multicast enable bit.
2209 */ 2182 */
2210 reg = SBMAC_READCSR(sc->sbm_rxfilter); 2183 reg = __raw_readq(sc->sbm_rxfilter);
2211 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2184 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2212 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 2185 __raw_writeq(reg, sc->sbm_rxfilter);
2213 return; 2186 return;
2214 } 2187 }
2215
2216 2188
2217 /* 2189
2190 /*
2218 * Progam new multicast entries. For now, only use the 2191 * Progam new multicast entries. For now, only use the
2219 * perfect filter. In the future we'll need to use the 2192 * perfect filter. In the future we'll need to use the
2220 * hash filter if the perfect filter overflows 2193 * hash filter if the perfect filter overflows
2221 */ 2194 */
2222 2195
2223 /* XXX only using perfect filter for now, need to use hash 2196 /* XXX only using perfect filter for now, need to use hash
2224 * XXX if the table overflows */ 2197 * XXX if the table overflows */
2225 2198
2226 idx = 1; /* skip station address */ 2199 idx = 1; /* skip station address */
2227 mclist = dev->mc_list; 2200 mclist = dev->mc_list;
2228 while (mclist && (idx < MAC_ADDR_COUNT)) { 2201 while (mclist && (idx < MAC_ADDR_COUNT)) {
2229 reg = sbmac_addr2reg(mclist->dmi_addr); 2202 reg = sbmac_addr2reg(mclist->dmi_addr);
2230 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); 2203 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2231 SBMAC_WRITECSR(port,reg); 2204 __raw_writeq(reg, port);
2232 idx++; 2205 idx++;
2233 mclist = mclist->next; 2206 mclist = mclist->next;
2234 } 2207 }
2235 2208
2236 /* 2209 /*
2237 * Enable the "accept multicast bits" if we programmed at least one 2210 * Enable the "accept multicast bits" if we programmed at least one
2238 * multicast. 2211 * multicast.
2239 */ 2212 */
2240 2213
2241 if (idx > 1) { 2214 if (idx > 1) {
2242 reg = SBMAC_READCSR(sc->sbm_rxfilter); 2215 reg = __raw_readq(sc->sbm_rxfilter);
2243 reg |= M_MAC_MCAST_EN; 2216 reg |= M_MAC_MCAST_EN;
2244 SBMAC_WRITECSR(sc->sbm_rxfilter,reg); 2217 __raw_writeq(reg, sc->sbm_rxfilter);
2245 } 2218 }
2246} 2219}
2247 2220
@@ -2250,12 +2223,12 @@ static void sbmac_setmulti(struct sbmac_softc *sc)
2250#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) 2223#if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2251/********************************************************************** 2224/**********************************************************************
2252 * SBMAC_PARSE_XDIGIT(str) 2225 * SBMAC_PARSE_XDIGIT(str)
2253 * 2226 *
2254 * Parse a hex digit, returning its value 2227 * Parse a hex digit, returning its value
2255 * 2228 *
2256 * Input parameters: 2229 * Input parameters:
2257 * str - character 2230 * str - character
2258 * 2231 *
2259 * Return value: 2232 * Return value:
2260 * hex value, or -1 if invalid 2233 * hex value, or -1 if invalid
2261 ********************************************************************* */ 2234 ********************************************************************* */
@@ -2263,7 +2236,7 @@ static void sbmac_setmulti(struct sbmac_softc *sc)
2263static int sbmac_parse_xdigit(char str) 2236static int sbmac_parse_xdigit(char str)
2264{ 2237{
2265 int digit; 2238 int digit;
2266 2239
2267 if ((str >= '0') && (str <= '9')) 2240 if ((str >= '0') && (str <= '9'))
2268 digit = str - '0'; 2241 digit = str - '0';
2269 else if ((str >= 'a') && (str <= 'f')) 2242 else if ((str >= 'a') && (str <= 'f'))
@@ -2272,20 +2245,20 @@ static int sbmac_parse_xdigit(char str)
2272 digit = str - 'A' + 10; 2245 digit = str - 'A' + 10;
2273 else 2246 else
2274 return -1; 2247 return -1;
2275 2248
2276 return digit; 2249 return digit;
2277} 2250}
2278 2251
2279/********************************************************************** 2252/**********************************************************************
2280 * SBMAC_PARSE_HWADDR(str,hwaddr) 2253 * SBMAC_PARSE_HWADDR(str,hwaddr)
2281 * 2254 *
2282 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte 2255 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2283 * Ethernet address. 2256 * Ethernet address.
2284 * 2257 *
2285 * Input parameters: 2258 * Input parameters:
2286 * str - string 2259 * str - string
2287 * hwaddr - pointer to hardware address 2260 * hwaddr - pointer to hardware address
2288 * 2261 *
2289 * Return value: 2262 * Return value:
2290 * 0 if ok, else -1 2263 * 0 if ok, else -1
2291 ********************************************************************* */ 2264 ********************************************************************* */
@@ -2294,7 +2267,7 @@ static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2294{ 2267{
2295 int digit1,digit2; 2268 int digit1,digit2;
2296 int idx = 6; 2269 int idx = 6;
2297 2270
2298 while (*str && (idx > 0)) { 2271 while (*str && (idx > 0)) {
2299 digit1 = sbmac_parse_xdigit(*str); 2272 digit1 = sbmac_parse_xdigit(*str);
2300 if (digit1 < 0) 2273 if (digit1 < 0)
@@ -2302,7 +2275,7 @@ static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2302 str++; 2275 str++;
2303 if (!*str) 2276 if (!*str)
2304 return -1; 2277 return -1;
2305 2278
2306 if ((*str == ':') || (*str == '-')) { 2279 if ((*str == ':') || (*str == '-')) {
2307 digit2 = digit1; 2280 digit2 = digit1;
2308 digit1 = 0; 2281 digit1 = 0;
@@ -2313,10 +2286,10 @@ static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2313 return -1; 2286 return -1;
2314 str++; 2287 str++;
2315 } 2288 }
2316 2289
2317 *hwaddr++ = (digit1 << 4) | digit2; 2290 *hwaddr++ = (digit1 << 4) | digit2;
2318 idx--; 2291 idx--;
2319 2292
2320 if (*str == '-') 2293 if (*str == '-')
2321 str++; 2294 str++;
2322 if (*str == ':') 2295 if (*str == ':')
@@ -2337,12 +2310,12 @@ static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2337 2310
2338/********************************************************************** 2311/**********************************************************************
2339 * SBMAC_INIT(dev) 2312 * SBMAC_INIT(dev)
2340 * 2313 *
2341 * Attach routine - init hardware and hook ourselves into linux 2314 * Attach routine - init hardware and hook ourselves into linux
2342 * 2315 *
2343 * Input parameters: 2316 * Input parameters:
2344 * dev - net_device structure 2317 * dev - net_device structure
2345 * 2318 *
2346 * Return value: 2319 * Return value:
2347 * status 2320 * status
2348 ********************************************************************* */ 2321 ********************************************************************* */
@@ -2354,53 +2327,53 @@ static int sbmac_init(struct net_device *dev, int idx)
2354 uint64_t ea_reg; 2327 uint64_t ea_reg;
2355 int i; 2328 int i;
2356 int err; 2329 int err;
2357 2330
2358 sc = netdev_priv(dev); 2331 sc = netdev_priv(dev);
2359 2332
2360 /* Determine controller base address */ 2333 /* Determine controller base address */
2361 2334
2362 sc->sbm_base = IOADDR(dev->base_addr); 2335 sc->sbm_base = IOADDR(dev->base_addr);
2363 sc->sbm_dev = dev; 2336 sc->sbm_dev = dev;
2364 sc->sbe_idx = idx; 2337 sc->sbe_idx = idx;
2365 2338
2366 eaddr = sc->sbm_hwaddr; 2339 eaddr = sc->sbm_hwaddr;
2367 2340
2368 /* 2341 /*
2369 * Read the ethernet address. The firwmare left this programmed 2342 * Read the ethernet address. The firwmare left this programmed
2370 * for us in the ethernet address register for each mac. 2343 * for us in the ethernet address register for each mac.
2371 */ 2344 */
2372 2345
2373 ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR); 2346 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2374 SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0); 2347 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2375 for (i = 0; i < 6; i++) { 2348 for (i = 0; i < 6; i++) {
2376 eaddr[i] = (uint8_t) (ea_reg & 0xFF); 2349 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2377 ea_reg >>= 8; 2350 ea_reg >>= 8;
2378 } 2351 }
2379 2352
2380 for (i = 0; i < 6; i++) { 2353 for (i = 0; i < 6; i++) {
2381 dev->dev_addr[i] = eaddr[i]; 2354 dev->dev_addr[i] = eaddr[i];
2382 } 2355 }
2383 2356
2384 2357
2385 /* 2358 /*
2386 * Init packet size 2359 * Init packet size
2387 */ 2360 */
2388 2361
2389 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN; 2362 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2390 2363
2391 /* 2364 /*
2392 * Initialize context (get pointers to registers and stuff), then 2365 * Initialize context (get pointers to registers and stuff), then
2393 * allocate the memory for the descriptor tables. 2366 * allocate the memory for the descriptor tables.
2394 */ 2367 */
2395 2368
2396 sbmac_initctx(sc); 2369 sbmac_initctx(sc);
2397 2370
2398 /* 2371 /*
2399 * Set up Linux device callins 2372 * Set up Linux device callins
2400 */ 2373 */
2401 2374
2402 spin_lock_init(&(sc->sbm_lock)); 2375 spin_lock_init(&(sc->sbm_lock));
2403 2376
2404 dev->open = sbmac_open; 2377 dev->open = sbmac_open;
2405 dev->hard_start_xmit = sbmac_start_tx; 2378 dev->hard_start_xmit = sbmac_start_tx;
2406 dev->stop = sbmac_close; 2379 dev->stop = sbmac_close;
@@ -2419,7 +2392,7 @@ static int sbmac_init(struct net_device *dev, int idx)
2419 if (err) 2392 if (err)
2420 goto out_uninit; 2393 goto out_uninit;
2421 2394
2422 if (periph_rev >= 2) { 2395 if (sc->rx_hw_checksum == ENABLE) {
2423 printk(KERN_INFO "%s: enabling TCP rcv checksum\n", 2396 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2424 sc->sbm_dev->name); 2397 sc->sbm_dev->name);
2425 } 2398 }
@@ -2430,10 +2403,10 @@ static int sbmac_init(struct net_device *dev, int idx)
2430 * was being displayed) 2403 * was being displayed)
2431 */ 2404 */
2432 printk(KERN_INFO 2405 printk(KERN_INFO
2433 "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n", 2406 "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2434 dev->name, dev->base_addr, 2407 dev->name, dev->base_addr,
2435 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]); 2408 eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2436 2409
2437 2410
2438 return 0; 2411 return 0;
2439 2412
@@ -2447,54 +2420,86 @@ out_uninit:
2447static int sbmac_open(struct net_device *dev) 2420static int sbmac_open(struct net_device *dev)
2448{ 2421{
2449 struct sbmac_softc *sc = netdev_priv(dev); 2422 struct sbmac_softc *sc = netdev_priv(dev);
2450 2423
2451 if (debug > 1) { 2424 if (debug > 1) {
2452 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq); 2425 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2453 } 2426 }
2454 2427
2455 /* 2428 /*
2456 * map/route interrupt (clear status first, in case something 2429 * map/route interrupt (clear status first, in case something
2457 * weird is pending; we haven't initialized the mac registers 2430 * weird is pending; we haven't initialized the mac registers
2458 * yet) 2431 * yet)
2459 */ 2432 */
2460 2433
2461 SBMAC_READCSR(sc->sbm_isr); 2434 __raw_readq(sc->sbm_isr);
2462 if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev)) 2435 if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev))
2463 return -EBUSY; 2436 return -EBUSY;
2464 2437
2465 /* 2438 /*
2466 * Configure default speed 2439 * Probe phy address
2440 */
2441
2442 if(sbmac_mii_probe(dev) == -1) {
2443 printk("%s: failed to probe PHY.\n", dev->name);
2444 return -EINVAL;
2445 }
2446
2447 /*
2448 * Configure default speed
2467 */ 2449 */
2468 2450
2469 sbmac_mii_poll(sc,noisy_mii); 2451 sbmac_mii_poll(sc,noisy_mii);
2470 2452
2471 /* 2453 /*
2472 * Turn on the channel 2454 * Turn on the channel
2473 */ 2455 */
2474 2456
2475 sbmac_set_channel_state(sc,sbmac_state_on); 2457 sbmac_set_channel_state(sc,sbmac_state_on);
2476 2458
2477 /* 2459 /*
2478 * XXX Station address is in dev->dev_addr 2460 * XXX Station address is in dev->dev_addr
2479 */ 2461 */
2480 2462
2481 if (dev->if_port == 0) 2463 if (dev->if_port == 0)
2482 dev->if_port = 0; 2464 dev->if_port = 0;
2483 2465
2484 netif_start_queue(dev); 2466 netif_start_queue(dev);
2485 2467
2486 sbmac_set_rx_mode(dev); 2468 sbmac_set_rx_mode(dev);
2487 2469
2488 /* Set the timer to check for link beat. */ 2470 /* Set the timer to check for link beat. */
2489 init_timer(&sc->sbm_timer); 2471 init_timer(&sc->sbm_timer);
2490 sc->sbm_timer.expires = jiffies + 2 * HZ/100; 2472 sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2491 sc->sbm_timer.data = (unsigned long)dev; 2473 sc->sbm_timer.data = (unsigned long)dev;
2492 sc->sbm_timer.function = &sbmac_timer; 2474 sc->sbm_timer.function = &sbmac_timer;
2493 add_timer(&sc->sbm_timer); 2475 add_timer(&sc->sbm_timer);
2494 2476
2495 return 0; 2477 return 0;
2496} 2478}
2497 2479
2480static int sbmac_mii_probe(struct net_device *dev)
2481{
2482 int i;
2483 struct sbmac_softc *s = netdev_priv(dev);
2484 u16 bmsr, id1, id2;
2485 u32 vendor, device;
2486
2487 for (i=1; i<31; i++) {
2488 bmsr = sbmac_mii_read(s, i, MII_BMSR);
2489 if (bmsr != 0) {
2490 s->sbm_phys[0] = i;
2491 id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2492 id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2493 vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2494 device = (id2 >> 4) & 0x3f;
2495
2496 printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2497 dev->name, i, vendor, device);
2498 return i;
2499 }
2500 }
2501 return -1;
2502}
2498 2503
2499 2504
2500static int sbmac_mii_poll(struct sbmac_softc *s,int noisy) 2505static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
@@ -2609,20 +2614,20 @@ static void sbmac_timer(unsigned long data)
2609 int mii_status; 2614 int mii_status;
2610 2615
2611 spin_lock_irq (&sc->sbm_lock); 2616 spin_lock_irq (&sc->sbm_lock);
2612 2617
2613 /* make IFF_RUNNING follow the MII status bit "Link established" */ 2618 /* make IFF_RUNNING follow the MII status bit "Link established" */
2614 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR); 2619 mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2615 2620
2616 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) { 2621 if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2617 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT; 2622 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2618 if (mii_status & BMSR_LINKSTAT) { 2623 if (mii_status & BMSR_LINKSTAT) {
2619 netif_carrier_on(dev); 2624 netif_carrier_on(dev);
2620 } 2625 }
2621 else { 2626 else {
2622 netif_carrier_off(dev); 2627 netif_carrier_off(dev);
2623 } 2628 }
2624 } 2629 }
2625 2630
2626 /* 2631 /*
2627 * Poll the PHY to see what speed we should be running at 2632 * Poll the PHY to see what speed we should be running at
2628 */ 2633 */
@@ -2640,9 +2645,9 @@ static void sbmac_timer(unsigned long data)
2640 sbmac_channel_start(sc); 2645 sbmac_channel_start(sc);
2641 } 2646 }
2642 } 2647 }
2643 2648
2644 spin_unlock_irq (&sc->sbm_lock); 2649 spin_unlock_irq (&sc->sbm_lock);
2645 2650
2646 sc->sbm_timer.expires = jiffies + next_tick; 2651 sc->sbm_timer.expires = jiffies + next_tick;
2647 add_timer(&sc->sbm_timer); 2652 add_timer(&sc->sbm_timer);
2648} 2653}
@@ -2651,13 +2656,13 @@ static void sbmac_timer(unsigned long data)
2651static void sbmac_tx_timeout (struct net_device *dev) 2656static void sbmac_tx_timeout (struct net_device *dev)
2652{ 2657{
2653 struct sbmac_softc *sc = netdev_priv(dev); 2658 struct sbmac_softc *sc = netdev_priv(dev);
2654 2659
2655 spin_lock_irq (&sc->sbm_lock); 2660 spin_lock_irq (&sc->sbm_lock);
2656 2661
2657 2662
2658 dev->trans_start = jiffies; 2663 dev->trans_start = jiffies;
2659 sc->sbm_stats.tx_errors++; 2664 sc->sbm_stats.tx_errors++;
2660 2665
2661 spin_unlock_irq (&sc->sbm_lock); 2666 spin_unlock_irq (&sc->sbm_lock);
2662 2667
2663 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); 2668 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
@@ -2670,13 +2675,13 @@ static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2670{ 2675{
2671 struct sbmac_softc *sc = netdev_priv(dev); 2676 struct sbmac_softc *sc = netdev_priv(dev);
2672 unsigned long flags; 2677 unsigned long flags;
2673 2678
2674 spin_lock_irqsave(&sc->sbm_lock, flags); 2679 spin_lock_irqsave(&sc->sbm_lock, flags);
2675 2680
2676 /* XXX update other stats here */ 2681 /* XXX update other stats here */
2677 2682
2678 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2683 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2679 2684
2680 return &sc->sbm_stats; 2685 return &sc->sbm_stats;
2681} 2686}
2682 2687
@@ -2693,8 +2698,8 @@ static void sbmac_set_rx_mode(struct net_device *dev)
2693 /* 2698 /*
2694 * Promiscuous changed. 2699 * Promiscuous changed.
2695 */ 2700 */
2696 2701
2697 if (dev->flags & IFF_PROMISC) { 2702 if (dev->flags & IFF_PROMISC) {
2698 /* Unconditionally log net taps. */ 2703 /* Unconditionally log net taps. */
2699 msg_flag = 1; 2704 msg_flag = 1;
2700 sbmac_promiscuous_mode(sc,1); 2705 sbmac_promiscuous_mode(sc,1);
@@ -2705,18 +2710,18 @@ static void sbmac_set_rx_mode(struct net_device *dev)
2705 } 2710 }
2706 } 2711 }
2707 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2712 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2708 2713
2709 if (msg_flag) { 2714 if (msg_flag) {
2710 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n", 2715 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2711 dev->name,(msg_flag==1)?"en":"dis"); 2716 dev->name,(msg_flag==1)?"en":"dis");
2712 } 2717 }
2713 2718
2714 /* 2719 /*
2715 * Program the multicasts. Do this every time. 2720 * Program the multicasts. Do this every time.
2716 */ 2721 */
2717 2722
2718 sbmac_setmulti(sc); 2723 sbmac_setmulti(sc);
2719 2724
2720} 2725}
2721 2726
2722static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2727static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
@@ -2725,10 +2730,10 @@ static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2725 u16 *data = (u16 *)&rq->ifr_ifru; 2730 u16 *data = (u16 *)&rq->ifr_ifru;
2726 unsigned long flags; 2731 unsigned long flags;
2727 int retval; 2732 int retval;
2728 2733
2729 spin_lock_irqsave(&sc->sbm_lock, flags); 2734 spin_lock_irqsave(&sc->sbm_lock, flags);
2730 retval = 0; 2735 retval = 0;
2731 2736
2732 switch(cmd) { 2737 switch(cmd) {
2733 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ 2738 case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */
2734 data[0] = sc->sbm_phys[0] & 0x1f; 2739 data[0] = sc->sbm_phys[0] & 0x1f;
@@ -2750,7 +2755,7 @@ static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2750 default: 2755 default:
2751 retval = -EOPNOTSUPP; 2756 retval = -EOPNOTSUPP;
2752 } 2757 }
2753 2758
2754 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2759 spin_unlock_irqrestore(&sc->sbm_lock, flags);
2755 return retval; 2760 return retval;
2756} 2761}
@@ -2781,7 +2786,7 @@ static int sbmac_close(struct net_device *dev)
2781 2786
2782 sbdma_emptyring(&(sc->sbm_txdma)); 2787 sbdma_emptyring(&(sc->sbm_txdma));
2783 sbdma_emptyring(&(sc->sbm_rxdma)); 2788 sbdma_emptyring(&(sc->sbm_rxdma));
2784 2789
2785 return 0; 2790 return 0;
2786} 2791}
2787 2792
@@ -2793,13 +2798,13 @@ sbmac_setup_hwaddr(int chan,char *addr)
2793{ 2798{
2794 uint8_t eaddr[6]; 2799 uint8_t eaddr[6];
2795 uint64_t val; 2800 uint64_t val;
2796 sbmac_port_t port; 2801 unsigned long port;
2797 2802
2798 port = A_MAC_CHANNEL_BASE(chan); 2803 port = A_MAC_CHANNEL_BASE(chan);
2799 sbmac_parse_hwaddr(addr,eaddr); 2804 sbmac_parse_hwaddr(addr,eaddr);
2800 val = sbmac_addr2reg(eaddr); 2805 val = sbmac_addr2reg(eaddr);
2801 SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR),val); 2806 __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2802 val = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR)); 2807 val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2803} 2808}
2804#endif 2809#endif
2805 2810
@@ -2810,9 +2815,9 @@ sbmac_init_module(void)
2810{ 2815{
2811 int idx; 2816 int idx;
2812 struct net_device *dev; 2817 struct net_device *dev;
2813 sbmac_port_t port; 2818 unsigned long port;
2814 int chip_max_units; 2819 int chip_max_units;
2815 2820
2816 /* 2821 /*
2817 * For bringup when not using the firmware, we can pre-fill 2822 * For bringup when not using the firmware, we can pre-fill
2818 * the MAC addresses using the environment variables 2823 * the MAC addresses using the environment variables
@@ -2858,13 +2863,13 @@ sbmac_init_module(void)
2858 2863
2859 port = A_MAC_CHANNEL_BASE(idx); 2864 port = A_MAC_CHANNEL_BASE(idx);
2860 2865
2861 /* 2866 /*
2862 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero 2867 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2863 * value for us by the firmware if we're going to use this MAC. 2868 * value for us by the firmware if we're going to use this MAC.
2864 * If we find a zero, skip this MAC. 2869 * If we find a zero, skip this MAC.
2865 */ 2870 */
2866 2871
2867 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR)); 2872 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2868 if (sbmac_orig_hwaddr[idx] == 0) { 2873 if (sbmac_orig_hwaddr[idx] == 0) {
2869 printk(KERN_DEBUG "sbmac: not configuring MAC at " 2874 printk(KERN_DEBUG "sbmac: not configuring MAC at "
2870 "%lx\n", port); 2875 "%lx\n", port);
@@ -2876,7 +2881,7 @@ sbmac_init_module(void)
2876 */ 2881 */
2877 2882
2878 dev = alloc_etherdev(sizeof(struct sbmac_softc)); 2883 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2879 if (!dev) 2884 if (!dev)
2880 return -ENOMEM; /* return ENOMEM */ 2885 return -ENOMEM; /* return ENOMEM */
2881 2886
2882 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port); 2887 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
@@ -2886,8 +2891,7 @@ sbmac_init_module(void)
2886 dev->mem_end = 0; 2891 dev->mem_end = 0;
2887 if (sbmac_init(dev, idx)) { 2892 if (sbmac_init(dev, idx)) {
2888 port = A_MAC_CHANNEL_BASE(idx); 2893 port = A_MAC_CHANNEL_BASE(idx);
2889 SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR), 2894 __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2890 sbmac_orig_hwaddr[idx]);
2891 free_netdev(dev); 2895 free_netdev(dev);
2892 continue; 2896 continue;
2893 } 2897 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 08:30:49 -0500