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authorAnanda Raju <Ananda.Raju@neterion.com>2006-04-21 19:18:03 -0400
committerJeff Garzik <jeff@garzik.org>2006-05-02 15:16:36 -0400
commitc92ca04b2a21852fbc6842e8a7c6fff3ae255b30 (patch)
tree9c161719d811a693d1ee3b202494e5a6d446c42e /drivers/net/s2io.h
parent9dc737a77353920a67337aa627f7d9dae8dade05 (diff)
[PATCH] s2io: fixes
Hi, This patch contains some of the bug fixes done for S2io driver. Following are the brief description of changes 1. Continuing with initialization if we get minimum required MSI-X vectors 2. fix for ethtool online link test fails 3. make wait_for_cmd_complete generic for all command status registers 4. Print "Device is on PCI-E bus" for Xframe-E card 5. CX4 requires additional delay after sw_reset, and requires higher value for igp 6. Fixed panic due to non-TCP and/or LLC/SNAP traffic in case of lro 7. remove legacy code for old transponder 8. SPECIAL_REG_WRITE made to use 32-bit writes irrespective of system type 9. handle link interrupt as per user guide for Xframe II 10. Wait till all interrupts hndled Signed-off-by: Ananda Raju <ananda.raju@neterion.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/s2io.h')
-rw-r--r--drivers/net/s2io.h30
1 files changed, 18 insertions, 12 deletions
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index a83a1d85f72e..fb46a4fed334 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -661,8 +661,8 @@ typedef struct {
661/* Default Tunable parameters of the NIC. */ 661/* Default Tunable parameters of the NIC. */
662#define DEFAULT_FIFO_0_LEN 4096 662#define DEFAULT_FIFO_0_LEN 4096
663#define DEFAULT_FIFO_1_7_LEN 512 663#define DEFAULT_FIFO_1_7_LEN 512
664#define SMALL_BLK_CNT 30 664#define SMALL_BLK_CNT 30
665#define LARGE_BLK_CNT 100 665#define LARGE_BLK_CNT 100
666 666
667/* 667/*
668 * Structure to keep track of the MSI-X vectors and the corresponding 668 * Structure to keep track of the MSI-X vectors and the corresponding
@@ -733,7 +733,7 @@ struct s2io_nic {
733 int device_close_flag; 733 int device_close_flag;
734 int device_enabled_once; 734 int device_enabled_once;
735 735
736 char name[50]; 736 char name[60];
737 struct tasklet_struct task; 737 struct tasklet_struct task;
738 volatile unsigned long tasklet_status; 738 volatile unsigned long tasklet_status;
739 739
@@ -804,6 +804,8 @@ struct s2io_nic {
804 char desc1[35]; 804 char desc1[35];
805 char desc2[35]; 805 char desc2[35];
806 806
807 int avail_msix_vectors; /* No. of MSI-X vectors granted by system */
808
807 struct msix_info_st msix_info[0x3f]; 809 struct msix_info_st msix_info[0x3f];
808 810
809#define XFRAME_I_DEVICE 1 811#define XFRAME_I_DEVICE 1
@@ -851,28 +853,32 @@ static inline void writeq(u64 val, void __iomem *addr)
851 writel((u32) (val), addr); 853 writel((u32) (val), addr);
852 writel((u32) (val >> 32), (addr + 4)); 854 writel((u32) (val >> 32), (addr + 4));
853} 855}
856#endif
854 857
855/* In 32 bit modes, some registers have to be written in a 858/*
856 * particular order to expect correct hardware operation. The 859 * Some registers have to be written in a particular order to
857 * macro SPECIAL_REG_WRITE is used to perform such ordered 860 * expect correct hardware operation. The macro SPECIAL_REG_WRITE
858 * writes. Defines UF (Upper First) and LF (Lower First) will 861 * is used to perform such ordered writes. Defines UF (Upper First)
859 * be used to specify the required write order. 862 * and LF (Lower First) will be used to specify the required write order.
860 */ 863 */
861#define UF 1 864#define UF 1
862#define LF 2 865#define LF 2
863static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) 866static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
864{ 867{
868 u32 ret;
869
865 if (order == LF) { 870 if (order == LF) {
866 writel((u32) (val), addr); 871 writel((u32) (val), addr);
872 ret = readl(addr);
867 writel((u32) (val >> 32), (addr + 4)); 873 writel((u32) (val >> 32), (addr + 4));
874 ret = readl(addr + 4);
868 } else { 875 } else {
869 writel((u32) (val >> 32), (addr + 4)); 876 writel((u32) (val >> 32), (addr + 4));
877 ret = readl(addr + 4);
870 writel((u32) (val), addr); 878 writel((u32) (val), addr);
879 ret = readl(addr);
871 } 880 }
872} 881}
873#else
874#define SPECIAL_REG_WRITE(val, addr, dummy) writeq(val, addr)
875#endif
876 882
877/* Interrupt related values of Xena */ 883/* Interrupt related values of Xena */
878 884
@@ -968,7 +974,7 @@ static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag);
968static struct ethtool_ops netdev_ethtool_ops; 974static struct ethtool_ops netdev_ethtool_ops;
969static void s2io_set_link(unsigned long data); 975static void s2io_set_link(unsigned long data);
970static int s2io_set_swapper(nic_t * sp); 976static int s2io_set_swapper(nic_t * sp);
971static void s2io_card_down(nic_t *nic); 977static void s2io_card_down(nic_t *nic, int flag);
972static int s2io_card_up(nic_t *nic); 978static int s2io_card_up(nic_t *nic);
973static int get_xena_rev_id(struct pci_dev *pdev); 979static int get_xena_rev_id(struct pci_dev *pdev);
974static void restore_xmsi_data(nic_t *nic); 980static void restore_xmsi_data(nic_t *nic);