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authorJiri Slaby <jirislaby@gmail.com>2007-10-19 02:40:29 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-19 14:53:42 -0400
commitb7b5a1282c37e1acf6c10391664ef9d6ad58e933 (patch)
tree789633b7d7d9434b99110fc25102a997b523859b /drivers/net/s2io.h
parented11399da5ac7a07dc470d9dee9a7846917ec4aa (diff)
s2io, rename BIT macro
s2io, rename BIT macro BIT macro will be global definiton of (1<<x) Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Cc: Ramkrishna Vepa <ram.vepa@neterion.com> Cc: Rastapur Santosh <santosh.rastapur@neterion.com> Cc: Sivakumar Subramani <sivakumar.subramani@neterion.com> Cc: Sreenivasa Honnur <sreenivasa.honnur@neterion.com> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/net/s2io.h')
-rw-r--r--drivers/net/s2io.h84
1 files changed, 42 insertions, 42 deletions
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index f6b45565304f..cc1797a071aa 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -14,7 +14,7 @@
14#define _S2IO_H 14#define _S2IO_H
15 15
16#define TBD 0 16#define TBD 0
17#define BIT(loc) (0x8000000000000000ULL >> (loc)) 17#define s2BIT(loc) (0x8000000000000000ULL >> (loc))
18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) 18#define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz))
19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) 19#define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff)
20 20
@@ -473,42 +473,42 @@ struct TxFIFO_element {
473 473
474 u64 List_Control; 474 u64 List_Control;
475#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) 475#define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8)
476#define TX_FIFO_FIRST_LIST BIT(14) 476#define TX_FIFO_FIRST_LIST s2BIT(14)
477#define TX_FIFO_LAST_LIST BIT(15) 477#define TX_FIFO_LAST_LIST s2BIT(15)
478#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) 478#define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2)
479#define TX_FIFO_SPECIAL_FUNC BIT(23) 479#define TX_FIFO_SPECIAL_FUNC s2BIT(23)
480#define TX_FIFO_DS_NO_SNOOP BIT(31) 480#define TX_FIFO_DS_NO_SNOOP s2BIT(31)
481#define TX_FIFO_BUFF_NO_SNOOP BIT(30) 481#define TX_FIFO_BUFF_NO_SNOOP s2BIT(30)
482}; 482};
483 483
484/* Tx descriptor structure */ 484/* Tx descriptor structure */
485struct TxD { 485struct TxD {
486 u64 Control_1; 486 u64 Control_1;
487/* bit mask */ 487/* bit mask */
488#define TXD_LIST_OWN_XENA BIT(7) 488#define TXD_LIST_OWN_XENA s2BIT(7)
489#define TXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 489#define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
490#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) 490#define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE))
491#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12) 491#define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12)
492#define TXD_GATHER_CODE (BIT(22) | BIT(23)) 492#define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23))
493#define TXD_GATHER_CODE_FIRST BIT(22) 493#define TXD_GATHER_CODE_FIRST s2BIT(22)
494#define TXD_GATHER_CODE_LAST BIT(23) 494#define TXD_GATHER_CODE_LAST s2BIT(23)
495#define TXD_TCP_LSO_EN BIT(30) 495#define TXD_TCP_LSO_EN s2BIT(30)
496#define TXD_UDP_COF_EN BIT(31) 496#define TXD_UDP_COF_EN s2BIT(31)
497#define TXD_UFO_EN BIT(31) | BIT(30) 497#define TXD_UFO_EN s2BIT(31) | s2BIT(30)
498#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14) 498#define TXD_TCP_LSO_MSS(val) vBIT(val,34,14)
499#define TXD_UFO_MSS(val) vBIT(val,34,14) 499#define TXD_UFO_MSS(val) vBIT(val,34,14)
500#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16) 500#define TXD_BUFFER0_SIZE(val) vBIT(val,48,16)
501 501
502 u64 Control_2; 502 u64 Control_2;
503#define TXD_TX_CKO_CONTROL (BIT(5)|BIT(6)|BIT(7)) 503#define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7))
504#define TXD_TX_CKO_IPV4_EN BIT(5) 504#define TXD_TX_CKO_IPV4_EN s2BIT(5)
505#define TXD_TX_CKO_TCP_EN BIT(6) 505#define TXD_TX_CKO_TCP_EN s2BIT(6)
506#define TXD_TX_CKO_UDP_EN BIT(7) 506#define TXD_TX_CKO_UDP_EN s2BIT(7)
507#define TXD_VLAN_ENABLE BIT(15) 507#define TXD_VLAN_ENABLE s2BIT(15)
508#define TXD_VLAN_TAG(val) vBIT(val,16,16) 508#define TXD_VLAN_TAG(val) vBIT(val,16,16)
509#define TXD_INT_NUMBER(val) vBIT(val,34,6) 509#define TXD_INT_NUMBER(val) vBIT(val,34,6)
510#define TXD_INT_TYPE_PER_LIST BIT(47) 510#define TXD_INT_TYPE_PER_LIST s2BIT(47)
511#define TXD_INT_TYPE_UTILZ BIT(46) 511#define TXD_INT_TYPE_UTILZ s2BIT(46)
512#define TXD_SET_MARKER vBIT(0x6,0,4) 512#define TXD_SET_MARKER vBIT(0x6,0,4)
513 513
514 u64 Buffer_Pointer; 514 u64 Buffer_Pointer;
@@ -525,14 +525,14 @@ struct list_info_hold {
525struct RxD_t { 525struct RxD_t {
526 u64 Host_Control; /* reserved for host */ 526 u64 Host_Control; /* reserved for host */
527 u64 Control_1; 527 u64 Control_1;
528#define RXD_OWN_XENA BIT(7) 528#define RXD_OWN_XENA s2BIT(7)
529#define RXD_T_CODE (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 529#define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15))
530#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8) 530#define RXD_FRAME_PROTO vBIT(0xFFFF,24,8)
531#define RXD_FRAME_PROTO_IPV4 BIT(27) 531#define RXD_FRAME_PROTO_IPV4 s2BIT(27)
532#define RXD_FRAME_PROTO_IPV6 BIT(28) 532#define RXD_FRAME_PROTO_IPV6 s2BIT(28)
533#define RXD_FRAME_IP_FRAG BIT(29) 533#define RXD_FRAME_IP_FRAG s2BIT(29)
534#define RXD_FRAME_PROTO_TCP BIT(30) 534#define RXD_FRAME_PROTO_TCP s2BIT(30)
535#define RXD_FRAME_PROTO_UDP BIT(31) 535#define RXD_FRAME_PROTO_UDP s2BIT(31)
536#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) 536#define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP)
537#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF) 537#define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF)
538#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) 538#define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF)
@@ -998,26 +998,26 @@ static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order)
998/* Interrupt masks for the general interrupt mask register */ 998/* Interrupt masks for the general interrupt mask register */
999#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL 999#define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL
1000 1000
1001#define TXPIC_INT_M BIT(0) 1001#define TXPIC_INT_M s2BIT(0)
1002#define TXDMA_INT_M BIT(1) 1002#define TXDMA_INT_M s2BIT(1)
1003#define TXMAC_INT_M BIT(2) 1003#define TXMAC_INT_M s2BIT(2)
1004#define TXXGXS_INT_M BIT(3) 1004#define TXXGXS_INT_M s2BIT(3)
1005#define TXTRAFFIC_INT_M BIT(8) 1005#define TXTRAFFIC_INT_M s2BIT(8)
1006#define PIC_RX_INT_M BIT(32) 1006#define PIC_RX_INT_M s2BIT(32)
1007#define RXDMA_INT_M BIT(33) 1007#define RXDMA_INT_M s2BIT(33)
1008#define RXMAC_INT_M BIT(34) 1008#define RXMAC_INT_M s2BIT(34)
1009#define MC_INT_M BIT(35) 1009#define MC_INT_M s2BIT(35)
1010#define RXXGXS_INT_M BIT(36) 1010#define RXXGXS_INT_M s2BIT(36)
1011#define RXTRAFFIC_INT_M BIT(40) 1011#define RXTRAFFIC_INT_M s2BIT(40)
1012 1012
1013/* PIC level Interrupts TODO*/ 1013/* PIC level Interrupts TODO*/
1014 1014
1015/* DMA level Inressupts */ 1015/* DMA level Inressupts */
1016#define TXDMA_PFC_INT_M BIT(0) 1016#define TXDMA_PFC_INT_M s2BIT(0)
1017#define TXDMA_PCC_INT_M BIT(2) 1017#define TXDMA_PCC_INT_M s2BIT(2)
1018 1018
1019/* PFC block interrupts */ 1019/* PFC block interrupts */
1020#define PFC_MISC_ERR_1 BIT(0) /* Interrupt to indicate FIFO full */ 1020#define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */
1021 1021
1022/* PCC block interrupts. */ 1022/* PCC block interrupts. */
1023#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate 1023#define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate