diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-07 22:21:56 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-07 22:21:56 -0500 |
commit | 7677ced48e2bbbb8d847d34f37e5d96d2b0e41e4 (patch) | |
tree | 0a859f403c02eb854d9ffa11bd17f77056891d07 /drivers/net/s2io.h | |
parent | 21d37bbc65e39a26856de6b14be371ff24e0d03f (diff) | |
parent | ac38dfc39e7684f55174742e5f0d6c5a0093bbf6 (diff) |
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (116 commits)
sk98lin: planned removal
AT91: MACB support
sky2: version 1.12
sky2: add new chip ids
sky2: Yukon Extreme support
sky2: safer transmit timeout
sky2: TSO support for EC_U
sky2: use dev_err for error reports
sky2: add Wake On Lan support
fix unaligned exception in /drivers/net/wireless/orinoco.c
Remove unused kernel config option DLCI_COUNT
z85230: spinlock logic
mips: declance: Driver model for the PMAD-A
Spidernet: Rework RX linked list
NET: turn local_save_flags() + local_irq_disable() into local_irq_save()
NET-3c59x: turn local_save_flags() + local_irq_disable() into local_irq_save()
hp100: convert pci_module_init() to pci_register_driver()
NetXen: Added ethtool support for user level tools.
NetXen: Firmware crb init changes.
maintainers: add atl1 maintainers
...
Diffstat (limited to 'drivers/net/s2io.h')
-rw-r--r-- | drivers/net/s2io.h | 223 |
1 files changed, 115 insertions, 108 deletions
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h index 3b0bafd273c8..a5e1a513deb5 100644 --- a/drivers/net/s2io.h +++ b/drivers/net/s2io.h | |||
@@ -30,6 +30,8 @@ | |||
30 | #undef SUCCESS | 30 | #undef SUCCESS |
31 | #define SUCCESS 0 | 31 | #define SUCCESS 0 |
32 | #define FAILURE -1 | 32 | #define FAILURE -1 |
33 | #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL | ||
34 | #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 | ||
33 | 35 | ||
34 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) | 36 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) |
35 | 37 | ||
@@ -37,7 +39,7 @@ | |||
37 | #define MAX_FLICKER_TIME 60000 /* 60 Secs */ | 39 | #define MAX_FLICKER_TIME 60000 /* 60 Secs */ |
38 | 40 | ||
39 | /* Maximum outstanding splits to be configured into xena. */ | 41 | /* Maximum outstanding splits to be configured into xena. */ |
40 | typedef enum xena_max_outstanding_splits { | 42 | enum { |
41 | XENA_ONE_SPLIT_TRANSACTION = 0, | 43 | XENA_ONE_SPLIT_TRANSACTION = 0, |
42 | XENA_TWO_SPLIT_TRANSACTION = 1, | 44 | XENA_TWO_SPLIT_TRANSACTION = 1, |
43 | XENA_THREE_SPLIT_TRANSACTION = 2, | 45 | XENA_THREE_SPLIT_TRANSACTION = 2, |
@@ -46,7 +48,7 @@ typedef enum xena_max_outstanding_splits { | |||
46 | XENA_TWELVE_SPLIT_TRANSACTION = 5, | 48 | XENA_TWELVE_SPLIT_TRANSACTION = 5, |
47 | XENA_SIXTEEN_SPLIT_TRANSACTION = 6, | 49 | XENA_SIXTEEN_SPLIT_TRANSACTION = 6, |
48 | XENA_THIRTYTWO_SPLIT_TRANSACTION = 7 | 50 | XENA_THIRTYTWO_SPLIT_TRANSACTION = 7 |
49 | } xena_max_outstanding_splits; | 51 | }; |
50 | #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) | 52 | #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) |
51 | 53 | ||
52 | /* OS concerned variables and constants */ | 54 | /* OS concerned variables and constants */ |
@@ -77,7 +79,7 @@ static int debug_level = ERR_DBG; | |||
77 | #define S2IO_JUMBO_SIZE 9600 | 79 | #define S2IO_JUMBO_SIZE 9600 |
78 | 80 | ||
79 | /* Driver statistics maintained by driver */ | 81 | /* Driver statistics maintained by driver */ |
80 | typedef struct { | 82 | struct swStat { |
81 | unsigned long long single_ecc_errs; | 83 | unsigned long long single_ecc_errs; |
82 | unsigned long long double_ecc_errs; | 84 | unsigned long long double_ecc_errs; |
83 | unsigned long long parity_err_cnt; | 85 | unsigned long long parity_err_cnt; |
@@ -92,10 +94,10 @@ typedef struct { | |||
92 | unsigned long long flush_max_pkts; | 94 | unsigned long long flush_max_pkts; |
93 | unsigned long long sum_avg_pkts_aggregated; | 95 | unsigned long long sum_avg_pkts_aggregated; |
94 | unsigned long long num_aggregations; | 96 | unsigned long long num_aggregations; |
95 | } swStat_t; | 97 | }; |
96 | 98 | ||
97 | /* Xpak releated alarm and warnings */ | 99 | /* Xpak releated alarm and warnings */ |
98 | typedef struct { | 100 | struct xpakStat { |
99 | u64 alarm_transceiver_temp_high; | 101 | u64 alarm_transceiver_temp_high; |
100 | u64 alarm_transceiver_temp_low; | 102 | u64 alarm_transceiver_temp_low; |
101 | u64 alarm_laser_bias_current_high; | 103 | u64 alarm_laser_bias_current_high; |
@@ -110,11 +112,11 @@ typedef struct { | |||
110 | u64 warn_laser_output_power_low; | 112 | u64 warn_laser_output_power_low; |
111 | u64 xpak_regs_stat; | 113 | u64 xpak_regs_stat; |
112 | u32 xpak_timer_count; | 114 | u32 xpak_timer_count; |
113 | } xpakStat_t; | 115 | }; |
114 | 116 | ||
115 | 117 | ||
116 | /* The statistics block of Xena */ | 118 | /* The statistics block of Xena */ |
117 | typedef struct stat_block { | 119 | struct stat_block { |
118 | /* Tx MAC statistics counters. */ | 120 | /* Tx MAC statistics counters. */ |
119 | __le32 tmac_data_octets; | 121 | __le32 tmac_data_octets; |
120 | __le32 tmac_frms; | 122 | __le32 tmac_frms; |
@@ -290,9 +292,9 @@ typedef struct stat_block { | |||
290 | __le32 reserved_14; | 292 | __le32 reserved_14; |
291 | __le32 link_fault_cnt; | 293 | __le32 link_fault_cnt; |
292 | u8 buffer[20]; | 294 | u8 buffer[20]; |
293 | swStat_t sw_stat; | 295 | struct swStat sw_stat; |
294 | xpakStat_t xpak_stat; | 296 | struct xpakStat xpak_stat; |
295 | } StatInfo_t; | 297 | }; |
296 | 298 | ||
297 | /* | 299 | /* |
298 | * Structures representing different init time configuration | 300 | * Structures representing different init time configuration |
@@ -315,7 +317,7 @@ static int fifo_map[][MAX_TX_FIFOS] = { | |||
315 | }; | 317 | }; |
316 | 318 | ||
317 | /* Maintains Per FIFO related information. */ | 319 | /* Maintains Per FIFO related information. */ |
318 | typedef struct tx_fifo_config { | 320 | struct tx_fifo_config { |
319 | #define MAX_AVAILABLE_TXDS 8192 | 321 | #define MAX_AVAILABLE_TXDS 8192 |
320 | u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ | 322 | u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ |
321 | /* Priority definition */ | 323 | /* Priority definition */ |
@@ -332,11 +334,11 @@ typedef struct tx_fifo_config { | |||
332 | u8 f_no_snoop; | 334 | u8 f_no_snoop; |
333 | #define NO_SNOOP_TXD 0x01 | 335 | #define NO_SNOOP_TXD 0x01 |
334 | #define NO_SNOOP_TXD_BUFFER 0x02 | 336 | #define NO_SNOOP_TXD_BUFFER 0x02 |
335 | } tx_fifo_config_t; | 337 | }; |
336 | 338 | ||
337 | 339 | ||
338 | /* Maintains per Ring related information */ | 340 | /* Maintains per Ring related information */ |
339 | typedef struct rx_ring_config { | 341 | struct rx_ring_config { |
340 | u32 num_rxd; /*No of RxDs per Rx Ring */ | 342 | u32 num_rxd; /*No of RxDs per Rx Ring */ |
341 | #define RX_RING_PRI_0 0 /* highest */ | 343 | #define RX_RING_PRI_0 0 /* highest */ |
342 | #define RX_RING_PRI_1 1 | 344 | #define RX_RING_PRI_1 1 |
@@ -357,7 +359,7 @@ typedef struct rx_ring_config { | |||
357 | u8 f_no_snoop; | 359 | u8 f_no_snoop; |
358 | #define NO_SNOOP_RXD 0x01 | 360 | #define NO_SNOOP_RXD 0x01 |
359 | #define NO_SNOOP_RXD_BUFFER 0x02 | 361 | #define NO_SNOOP_RXD_BUFFER 0x02 |
360 | } rx_ring_config_t; | 362 | }; |
361 | 363 | ||
362 | /* This structure provides contains values of the tunable parameters | 364 | /* This structure provides contains values of the tunable parameters |
363 | * of the H/W | 365 | * of the H/W |
@@ -367,7 +369,7 @@ struct config_param { | |||
367 | u32 tx_fifo_num; /*Number of Tx FIFOs */ | 369 | u32 tx_fifo_num; /*Number of Tx FIFOs */ |
368 | 370 | ||
369 | u8 fifo_mapping[MAX_TX_FIFOS]; | 371 | u8 fifo_mapping[MAX_TX_FIFOS]; |
370 | tx_fifo_config_t tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ | 372 | struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ |
371 | u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ | 373 | u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ |
372 | u64 tx_intr_type; | 374 | u64 tx_intr_type; |
373 | /* Specifies if Tx Intr is UTILZ or PER_LIST type. */ | 375 | /* Specifies if Tx Intr is UTILZ or PER_LIST type. */ |
@@ -376,7 +378,7 @@ struct config_param { | |||
376 | u32 rx_ring_num; /*Number of receive rings */ | 378 | u32 rx_ring_num; /*Number of receive rings */ |
377 | #define MAX_RX_BLOCKS_PER_RING 150 | 379 | #define MAX_RX_BLOCKS_PER_RING 150 |
378 | 380 | ||
379 | rx_ring_config_t rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ | 381 | struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ |
380 | u8 bimodal; /*Flag for setting bimodal interrupts*/ | 382 | u8 bimodal; /*Flag for setting bimodal interrupts*/ |
381 | 383 | ||
382 | #define HEADER_ETHERNET_II_802_3_SIZE 14 | 384 | #define HEADER_ETHERNET_II_802_3_SIZE 14 |
@@ -395,14 +397,14 @@ struct config_param { | |||
395 | }; | 397 | }; |
396 | 398 | ||
397 | /* Structure representing MAC Addrs */ | 399 | /* Structure representing MAC Addrs */ |
398 | typedef struct mac_addr { | 400 | struct mac_addr { |
399 | u8 mac_addr[ETH_ALEN]; | 401 | u8 mac_addr[ETH_ALEN]; |
400 | } macaddr_t; | 402 | }; |
401 | 403 | ||
402 | /* Structure that represent every FIFO element in the BAR1 | 404 | /* Structure that represent every FIFO element in the BAR1 |
403 | * Address location. | 405 | * Address location. |
404 | */ | 406 | */ |
405 | typedef struct _TxFIFO_element { | 407 | struct TxFIFO_element { |
406 | u64 TxDL_Pointer; | 408 | u64 TxDL_Pointer; |
407 | 409 | ||
408 | u64 List_Control; | 410 | u64 List_Control; |
@@ -413,10 +415,10 @@ typedef struct _TxFIFO_element { | |||
413 | #define TX_FIFO_SPECIAL_FUNC BIT(23) | 415 | #define TX_FIFO_SPECIAL_FUNC BIT(23) |
414 | #define TX_FIFO_DS_NO_SNOOP BIT(31) | 416 | #define TX_FIFO_DS_NO_SNOOP BIT(31) |
415 | #define TX_FIFO_BUFF_NO_SNOOP BIT(30) | 417 | #define TX_FIFO_BUFF_NO_SNOOP BIT(30) |
416 | } TxFIFO_element_t; | 418 | }; |
417 | 419 | ||
418 | /* Tx descriptor structure */ | 420 | /* Tx descriptor structure */ |
419 | typedef struct _TxD { | 421 | struct TxD { |
420 | u64 Control_1; | 422 | u64 Control_1; |
421 | /* bit mask */ | 423 | /* bit mask */ |
422 | #define TXD_LIST_OWN_XENA BIT(7) | 424 | #define TXD_LIST_OWN_XENA BIT(7) |
@@ -447,16 +449,16 @@ typedef struct _TxD { | |||
447 | 449 | ||
448 | u64 Buffer_Pointer; | 450 | u64 Buffer_Pointer; |
449 | u64 Host_Control; /* reserved for host */ | 451 | u64 Host_Control; /* reserved for host */ |
450 | } TxD_t; | 452 | }; |
451 | 453 | ||
452 | /* Structure to hold the phy and virt addr of every TxDL. */ | 454 | /* Structure to hold the phy and virt addr of every TxDL. */ |
453 | typedef struct list_info_hold { | 455 | struct list_info_hold { |
454 | dma_addr_t list_phy_addr; | 456 | dma_addr_t list_phy_addr; |
455 | void *list_virt_addr; | 457 | void *list_virt_addr; |
456 | } list_info_hold_t; | 458 | }; |
457 | 459 | ||
458 | /* Rx descriptor structure for 1 buffer mode */ | 460 | /* Rx descriptor structure for 1 buffer mode */ |
459 | typedef struct _RxD_t { | 461 | struct RxD_t { |
460 | u64 Host_Control; /* reserved for host */ | 462 | u64 Host_Control; /* reserved for host */ |
461 | u64 Control_1; | 463 | u64 Control_1; |
462 | #define RXD_OWN_XENA BIT(7) | 464 | #define RXD_OWN_XENA BIT(7) |
@@ -481,21 +483,21 @@ typedef struct _RxD_t { | |||
481 | #define SET_NUM_TAG(val) vBIT(val,16,32) | 483 | #define SET_NUM_TAG(val) vBIT(val,16,32) |
482 | 484 | ||
483 | 485 | ||
484 | } RxD_t; | 486 | }; |
485 | /* Rx descriptor structure for 1 buffer mode */ | 487 | /* Rx descriptor structure for 1 buffer mode */ |
486 | typedef struct _RxD1_t { | 488 | struct RxD1 { |
487 | struct _RxD_t h; | 489 | struct RxD_t h; |
488 | 490 | ||
489 | #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) | 491 | #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) |
490 | #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) | 492 | #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) |
491 | #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \ | 493 | #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \ |
492 | (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) | 494 | (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) |
493 | u64 Buffer0_ptr; | 495 | u64 Buffer0_ptr; |
494 | } RxD1_t; | 496 | }; |
495 | /* Rx descriptor structure for 3 or 2 buffer mode */ | 497 | /* Rx descriptor structure for 3 or 2 buffer mode */ |
496 | 498 | ||
497 | typedef struct _RxD3_t { | 499 | struct RxD3 { |
498 | struct _RxD_t h; | 500 | struct RxD_t h; |
499 | 501 | ||
500 | #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) | 502 | #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) |
501 | #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) | 503 | #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) |
@@ -515,15 +517,15 @@ typedef struct _RxD3_t { | |||
515 | u64 Buffer0_ptr; | 517 | u64 Buffer0_ptr; |
516 | u64 Buffer1_ptr; | 518 | u64 Buffer1_ptr; |
517 | u64 Buffer2_ptr; | 519 | u64 Buffer2_ptr; |
518 | } RxD3_t; | 520 | }; |
519 | 521 | ||
520 | 522 | ||
521 | /* Structure that represents the Rx descriptor block which contains | 523 | /* Structure that represents the Rx descriptor block which contains |
522 | * 128 Rx descriptors. | 524 | * 128 Rx descriptors. |
523 | */ | 525 | */ |
524 | typedef struct _RxD_block { | 526 | struct RxD_block { |
525 | #define MAX_RXDS_PER_BLOCK_1 127 | 527 | #define MAX_RXDS_PER_BLOCK_1 127 |
526 | RxD1_t rxd[MAX_RXDS_PER_BLOCK_1]; | 528 | struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1]; |
527 | 529 | ||
528 | u64 reserved_0; | 530 | u64 reserved_0; |
529 | #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL | 531 | #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL |
@@ -533,22 +535,22 @@ typedef struct _RxD_block { | |||
533 | u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch | 535 | u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch |
534 | * the upper 32 bits should | 536 | * the upper 32 bits should |
535 | * be 0 */ | 537 | * be 0 */ |
536 | } RxD_block_t; | 538 | }; |
537 | 539 | ||
538 | #define SIZE_OF_BLOCK 4096 | 540 | #define SIZE_OF_BLOCK 4096 |
539 | 541 | ||
540 | #define RXD_MODE_1 0 | 542 | #define RXD_MODE_1 0 /* One Buffer mode */ |
541 | #define RXD_MODE_3A 1 | 543 | #define RXD_MODE_3A 1 /* Three Buffer mode */ |
542 | #define RXD_MODE_3B 2 | 544 | #define RXD_MODE_3B 2 /* Two Buffer mode */ |
543 | 545 | ||
544 | /* Structure to hold virtual addresses of Buf0 and Buf1 in | 546 | /* Structure to hold virtual addresses of Buf0 and Buf1 in |
545 | * 2buf mode. */ | 547 | * 2buf mode. */ |
546 | typedef struct bufAdd { | 548 | struct buffAdd { |
547 | void *ba_0_org; | 549 | void *ba_0_org; |
548 | void *ba_1_org; | 550 | void *ba_1_org; |
549 | void *ba_0; | 551 | void *ba_0; |
550 | void *ba_1; | 552 | void *ba_1; |
551 | } buffAdd_t; | 553 | }; |
552 | 554 | ||
553 | /* Structure which stores all the MAC control parameters */ | 555 | /* Structure which stores all the MAC control parameters */ |
554 | 556 | ||
@@ -556,43 +558,46 @@ typedef struct bufAdd { | |||
556 | * from which the Rx Interrupt processor can start picking | 558 | * from which the Rx Interrupt processor can start picking |
557 | * up the RxDs for processing. | 559 | * up the RxDs for processing. |
558 | */ | 560 | */ |
559 | typedef struct _rx_curr_get_info_t { | 561 | struct rx_curr_get_info { |
560 | u32 block_index; | 562 | u32 block_index; |
561 | u32 offset; | 563 | u32 offset; |
562 | u32 ring_len; | 564 | u32 ring_len; |
563 | } rx_curr_get_info_t; | 565 | }; |
564 | 566 | ||
565 | typedef rx_curr_get_info_t rx_curr_put_info_t; | 567 | struct rx_curr_put_info { |
568 | u32 block_index; | ||
569 | u32 offset; | ||
570 | u32 ring_len; | ||
571 | }; | ||
566 | 572 | ||
567 | /* This structure stores the offset of the TxDl in the FIFO | 573 | /* This structure stores the offset of the TxDl in the FIFO |
568 | * from which the Tx Interrupt processor can start picking | 574 | * from which the Tx Interrupt processor can start picking |
569 | * up the TxDLs for send complete interrupt processing. | 575 | * up the TxDLs for send complete interrupt processing. |
570 | */ | 576 | */ |
571 | typedef struct { | 577 | struct tx_curr_get_info { |
572 | u32 offset; | 578 | u32 offset; |
573 | u32 fifo_len; | 579 | u32 fifo_len; |
574 | } tx_curr_get_info_t; | 580 | }; |
575 | |||
576 | typedef tx_curr_get_info_t tx_curr_put_info_t; | ||
577 | 581 | ||
582 | struct tx_curr_put_info { | ||
583 | u32 offset; | ||
584 | u32 fifo_len; | ||
585 | }; | ||
578 | 586 | ||
579 | typedef struct rxd_info { | 587 | struct rxd_info { |
580 | void *virt_addr; | 588 | void *virt_addr; |
581 | dma_addr_t dma_addr; | 589 | dma_addr_t dma_addr; |
582 | }rxd_info_t; | 590 | }; |
583 | 591 | ||
584 | /* Structure that holds the Phy and virt addresses of the Blocks */ | 592 | /* Structure that holds the Phy and virt addresses of the Blocks */ |
585 | typedef struct rx_block_info { | 593 | struct rx_block_info { |
586 | void *block_virt_addr; | 594 | void *block_virt_addr; |
587 | dma_addr_t block_dma_addr; | 595 | dma_addr_t block_dma_addr; |
588 | rxd_info_t *rxds; | 596 | struct rxd_info *rxds; |
589 | } rx_block_info_t; | 597 | }; |
590 | |||
591 | /* pre declaration of the nic structure */ | ||
592 | typedef struct s2io_nic nic_t; | ||
593 | 598 | ||
594 | /* Ring specific structure */ | 599 | /* Ring specific structure */ |
595 | typedef struct ring_info { | 600 | struct ring_info { |
596 | /* The ring number */ | 601 | /* The ring number */ |
597 | int ring_no; | 602 | int ring_no; |
598 | 603 | ||
@@ -600,7 +605,7 @@ typedef struct ring_info { | |||
600 | * Place holders for the virtual and physical addresses of | 605 | * Place holders for the virtual and physical addresses of |
601 | * all the Rx Blocks | 606 | * all the Rx Blocks |
602 | */ | 607 | */ |
603 | rx_block_info_t rx_blocks[MAX_RX_BLOCKS_PER_RING]; | 608 | struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING]; |
604 | int block_count; | 609 | int block_count; |
605 | int pkt_cnt; | 610 | int pkt_cnt; |
606 | 611 | ||
@@ -608,26 +613,24 @@ typedef struct ring_info { | |||
608 | * Put pointer info which indictes which RxD has to be replenished | 613 | * Put pointer info which indictes which RxD has to be replenished |
609 | * with a new buffer. | 614 | * with a new buffer. |
610 | */ | 615 | */ |
611 | rx_curr_put_info_t rx_curr_put_info; | 616 | struct rx_curr_put_info rx_curr_put_info; |
612 | 617 | ||
613 | /* | 618 | /* |
614 | * Get pointer info which indictes which is the last RxD that was | 619 | * Get pointer info which indictes which is the last RxD that was |
615 | * processed by the driver. | 620 | * processed by the driver. |
616 | */ | 621 | */ |
617 | rx_curr_get_info_t rx_curr_get_info; | 622 | struct rx_curr_get_info rx_curr_get_info; |
618 | 623 | ||
619 | #ifndef CONFIG_S2IO_NAPI | ||
620 | /* Index to the absolute position of the put pointer of Rx ring */ | 624 | /* Index to the absolute position of the put pointer of Rx ring */ |
621 | int put_pos; | 625 | int put_pos; |
622 | #endif | ||
623 | 626 | ||
624 | /* Buffer Address store. */ | 627 | /* Buffer Address store. */ |
625 | buffAdd_t **ba; | 628 | struct buffAdd **ba; |
626 | nic_t *nic; | 629 | struct s2io_nic *nic; |
627 | } ring_info_t; | 630 | }; |
628 | 631 | ||
629 | /* Fifo specific structure */ | 632 | /* Fifo specific structure */ |
630 | typedef struct fifo_info { | 633 | struct fifo_info { |
631 | /* FIFO number */ | 634 | /* FIFO number */ |
632 | int fifo_no; | 635 | int fifo_no; |
633 | 636 | ||
@@ -635,40 +638,40 @@ typedef struct fifo_info { | |||
635 | int max_txds; | 638 | int max_txds; |
636 | 639 | ||
637 | /* Place holder of all the TX List's Phy and Virt addresses. */ | 640 | /* Place holder of all the TX List's Phy and Virt addresses. */ |
638 | list_info_hold_t *list_info; | 641 | struct list_info_hold *list_info; |
639 | 642 | ||
640 | /* | 643 | /* |
641 | * Current offset within the tx FIFO where driver would write | 644 | * Current offset within the tx FIFO where driver would write |
642 | * new Tx frame | 645 | * new Tx frame |
643 | */ | 646 | */ |
644 | tx_curr_put_info_t tx_curr_put_info; | 647 | struct tx_curr_put_info tx_curr_put_info; |
645 | 648 | ||
646 | /* | 649 | /* |
647 | * Current offset within tx FIFO from where the driver would start freeing | 650 | * Current offset within tx FIFO from where the driver would start freeing |
648 | * the buffers | 651 | * the buffers |
649 | */ | 652 | */ |
650 | tx_curr_get_info_t tx_curr_get_info; | 653 | struct tx_curr_get_info tx_curr_get_info; |
651 | 654 | ||
652 | nic_t *nic; | 655 | struct s2io_nic *nic; |
653 | }fifo_info_t; | 656 | }; |
654 | 657 | ||
655 | /* Information related to the Tx and Rx FIFOs and Rings of Xena | 658 | /* Information related to the Tx and Rx FIFOs and Rings of Xena |
656 | * is maintained in this structure. | 659 | * is maintained in this structure. |
657 | */ | 660 | */ |
658 | typedef struct mac_info { | 661 | struct mac_info { |
659 | /* tx side stuff */ | 662 | /* tx side stuff */ |
660 | /* logical pointer of start of each Tx FIFO */ | 663 | /* logical pointer of start of each Tx FIFO */ |
661 | TxFIFO_element_t __iomem *tx_FIFO_start[MAX_TX_FIFOS]; | 664 | struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS]; |
662 | 665 | ||
663 | /* Fifo specific structure */ | 666 | /* Fifo specific structure */ |
664 | fifo_info_t fifos[MAX_TX_FIFOS]; | 667 | struct fifo_info fifos[MAX_TX_FIFOS]; |
665 | 668 | ||
666 | /* Save virtual address of TxD page with zero DMA addr(if any) */ | 669 | /* Save virtual address of TxD page with zero DMA addr(if any) */ |
667 | void *zerodma_virt_addr; | 670 | void *zerodma_virt_addr; |
668 | 671 | ||
669 | /* rx side stuff */ | 672 | /* rx side stuff */ |
670 | /* Ring specific structure */ | 673 | /* Ring specific structure */ |
671 | ring_info_t rings[MAX_RX_RINGS]; | 674 | struct ring_info rings[MAX_RX_RINGS]; |
672 | 675 | ||
673 | u16 rmac_pause_time; | 676 | u16 rmac_pause_time; |
674 | u16 mc_pause_threshold_q0q3; | 677 | u16 mc_pause_threshold_q0q3; |
@@ -677,14 +680,14 @@ typedef struct mac_info { | |||
677 | void *stats_mem; /* orignal pointer to allocated mem */ | 680 | void *stats_mem; /* orignal pointer to allocated mem */ |
678 | dma_addr_t stats_mem_phy; /* Physical address of the stat block */ | 681 | dma_addr_t stats_mem_phy; /* Physical address of the stat block */ |
679 | u32 stats_mem_sz; | 682 | u32 stats_mem_sz; |
680 | StatInfo_t *stats_info; /* Logical address of the stat block */ | 683 | struct stat_block *stats_info; /* Logical address of the stat block */ |
681 | } mac_info_t; | 684 | }; |
682 | 685 | ||
683 | /* structure representing the user defined MAC addresses */ | 686 | /* structure representing the user defined MAC addresses */ |
684 | typedef struct { | 687 | struct usr_addr { |
685 | char addr[ETH_ALEN]; | 688 | char addr[ETH_ALEN]; |
686 | int usage_cnt; | 689 | int usage_cnt; |
687 | } usr_addr_t; | 690 | }; |
688 | 691 | ||
689 | /* Default Tunable parameters of the NIC. */ | 692 | /* Default Tunable parameters of the NIC. */ |
690 | #define DEFAULT_FIFO_0_LEN 4096 | 693 | #define DEFAULT_FIFO_0_LEN 4096 |
@@ -717,7 +720,7 @@ struct msix_info_st { | |||
717 | }; | 720 | }; |
718 | 721 | ||
719 | /* Data structure to represent a LRO session */ | 722 | /* Data structure to represent a LRO session */ |
720 | typedef struct lro { | 723 | struct lro { |
721 | struct sk_buff *parent; | 724 | struct sk_buff *parent; |
722 | struct sk_buff *last_frag; | 725 | struct sk_buff *last_frag; |
723 | u8 *l2h; | 726 | u8 *l2h; |
@@ -733,20 +736,18 @@ typedef struct lro { | |||
733 | u32 cur_tsval; | 736 | u32 cur_tsval; |
734 | u32 cur_tsecr; | 737 | u32 cur_tsecr; |
735 | u8 saw_ts; | 738 | u8 saw_ts; |
736 | }lro_t; | 739 | }; |
737 | 740 | ||
738 | /* Structure representing one instance of the NIC */ | 741 | /* Structure representing one instance of the NIC */ |
739 | struct s2io_nic { | 742 | struct s2io_nic { |
740 | int rxd_mode; | 743 | int rxd_mode; |
741 | #ifdef CONFIG_S2IO_NAPI | ||
742 | /* | 744 | /* |
743 | * Count of packets to be processed in a given iteration, it will be indicated | 745 | * Count of packets to be processed in a given iteration, it will be indicated |
744 | * by the quota field of the device structure when NAPI is enabled. | 746 | * by the quota field of the device structure when NAPI is enabled. |
745 | */ | 747 | */ |
746 | int pkts_to_process; | 748 | int pkts_to_process; |
747 | #endif | ||
748 | struct net_device *dev; | 749 | struct net_device *dev; |
749 | mac_info_t mac_control; | 750 | struct mac_info mac_control; |
750 | struct config_param config; | 751 | struct config_param config; |
751 | struct pci_dev *pdev; | 752 | struct pci_dev *pdev; |
752 | void __iomem *bar0; | 753 | void __iomem *bar0; |
@@ -754,8 +755,8 @@ struct s2io_nic { | |||
754 | #define MAX_MAC_SUPPORTED 16 | 755 | #define MAX_MAC_SUPPORTED 16 |
755 | #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED | 756 | #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED |
756 | 757 | ||
757 | macaddr_t def_mac_addr[MAX_MAC_SUPPORTED]; | 758 | struct mac_addr def_mac_addr[MAX_MAC_SUPPORTED]; |
758 | macaddr_t pre_mac_addr[MAX_MAC_SUPPORTED]; | 759 | struct mac_addr pre_mac_addr[MAX_MAC_SUPPORTED]; |
759 | 760 | ||
760 | struct net_device_stats stats; | 761 | struct net_device_stats stats; |
761 | int high_dma_flag; | 762 | int high_dma_flag; |
@@ -775,9 +776,7 @@ struct s2io_nic { | |||
775 | atomic_t rx_bufs_left[MAX_RX_RINGS]; | 776 | atomic_t rx_bufs_left[MAX_RX_RINGS]; |
776 | 777 | ||
777 | spinlock_t tx_lock; | 778 | spinlock_t tx_lock; |
778 | #ifndef CONFIG_S2IO_NAPI | ||
779 | spinlock_t put_lock; | 779 | spinlock_t put_lock; |
780 | #endif | ||
781 | 780 | ||
782 | #define PROMISC 1 | 781 | #define PROMISC 1 |
783 | #define ALL_MULTI 2 | 782 | #define ALL_MULTI 2 |
@@ -785,7 +784,7 @@ struct s2io_nic { | |||
785 | #define MAX_ADDRS_SUPPORTED 64 | 784 | #define MAX_ADDRS_SUPPORTED 64 |
786 | u16 usr_addr_count; | 785 | u16 usr_addr_count; |
787 | u16 mc_addr_count; | 786 | u16 mc_addr_count; |
788 | usr_addr_t usr_addrs[MAX_ADDRS_SUPPORTED]; | 787 | struct usr_addr usr_addrs[MAX_ADDRS_SUPPORTED]; |
789 | 788 | ||
790 | u16 m_cast_flg; | 789 | u16 m_cast_flg; |
791 | u16 all_multi_pos; | 790 | u16 all_multi_pos; |
@@ -841,7 +840,7 @@ struct s2io_nic { | |||
841 | u8 device_type; | 840 | u8 device_type; |
842 | 841 | ||
843 | #define MAX_LRO_SESSIONS 32 | 842 | #define MAX_LRO_SESSIONS 32 |
844 | lro_t lro0_n[MAX_LRO_SESSIONS]; | 843 | struct lro lro0_n[MAX_LRO_SESSIONS]; |
845 | unsigned long clubbed_frms_cnt; | 844 | unsigned long clubbed_frms_cnt; |
846 | unsigned long sending_both; | 845 | unsigned long sending_both; |
847 | u8 lro; | 846 | u8 lro; |
@@ -855,8 +854,9 @@ struct s2io_nic { | |||
855 | spinlock_t rx_lock; | 854 | spinlock_t rx_lock; |
856 | atomic_t isr_cnt; | 855 | atomic_t isr_cnt; |
857 | u64 *ufo_in_band_v; | 856 | u64 *ufo_in_band_v; |
858 | #define VPD_PRODUCT_NAME_LEN 50 | 857 | #define VPD_STRING_LEN 80 |
859 | u8 product_name[VPD_PRODUCT_NAME_LEN]; | 858 | u8 product_name[VPD_STRING_LEN]; |
859 | u8 serial_num[VPD_STRING_LEN]; | ||
860 | }; | 860 | }; |
861 | 861 | ||
862 | #define RESET_ERROR 1; | 862 | #define RESET_ERROR 1; |
@@ -975,43 +975,50 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev); | |||
975 | static int init_shared_mem(struct s2io_nic *sp); | 975 | static int init_shared_mem(struct s2io_nic *sp); |
976 | static void free_shared_mem(struct s2io_nic *sp); | 976 | static void free_shared_mem(struct s2io_nic *sp); |
977 | static int init_nic(struct s2io_nic *nic); | 977 | static int init_nic(struct s2io_nic *nic); |
978 | static void rx_intr_handler(ring_info_t *ring_data); | 978 | static void rx_intr_handler(struct ring_info *ring_data); |
979 | static void tx_intr_handler(fifo_info_t *fifo_data); | 979 | static void tx_intr_handler(struct fifo_info *fifo_data); |
980 | static void alarm_intr_handler(struct s2io_nic *sp); | 980 | static void alarm_intr_handler(struct s2io_nic *sp); |
981 | 981 | ||
982 | static int s2io_starter(void); | 982 | static int s2io_starter(void); |
983 | static void s2io_closer(void); | ||
983 | static void s2io_tx_watchdog(struct net_device *dev); | 984 | static void s2io_tx_watchdog(struct net_device *dev); |
984 | static void s2io_tasklet(unsigned long dev_addr); | 985 | static void s2io_tasklet(unsigned long dev_addr); |
985 | static void s2io_set_multicast(struct net_device *dev); | 986 | static void s2io_set_multicast(struct net_device *dev); |
986 | static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp); | 987 | static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp); |
987 | static void s2io_link(nic_t * sp, int link); | 988 | static void s2io_link(struct s2io_nic * sp, int link); |
988 | #if defined(CONFIG_S2IO_NAPI) | 989 | static void s2io_reset(struct s2io_nic * sp); |
989 | static int s2io_poll(struct net_device *dev, int *budget); | 990 | static int s2io_poll(struct net_device *dev, int *budget); |
990 | #endif | 991 | static void s2io_init_pci(struct s2io_nic * sp); |
991 | static void s2io_init_pci(nic_t * sp); | ||
992 | static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); | 992 | static int s2io_set_mac_addr(struct net_device *dev, u8 * addr); |
993 | static void s2io_alarm_handle(unsigned long data); | 993 | static void s2io_alarm_handle(unsigned long data); |
994 | static int s2io_enable_msi(nic_t *nic); | 994 | static int s2io_enable_msi(struct s2io_nic *nic); |
995 | static irqreturn_t s2io_msi_handle(int irq, void *dev_id); | 995 | static irqreturn_t s2io_msi_handle(int irq, void *dev_id); |
996 | static irqreturn_t | 996 | static irqreturn_t |
997 | s2io_msix_ring_handle(int irq, void *dev_id); | 997 | s2io_msix_ring_handle(int irq, void *dev_id); |
998 | static irqreturn_t | 998 | static irqreturn_t |
999 | s2io_msix_fifo_handle(int irq, void *dev_id); | 999 | s2io_msix_fifo_handle(int irq, void *dev_id); |
1000 | static irqreturn_t s2io_isr(int irq, void *dev_id); | 1000 | static irqreturn_t s2io_isr(int irq, void *dev_id); |
1001 | static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag); | 1001 | static int verify_xena_quiescence(struct s2io_nic *sp); |
1002 | static const struct ethtool_ops netdev_ethtool_ops; | 1002 | static const struct ethtool_ops netdev_ethtool_ops; |
1003 | static void s2io_set_link(struct work_struct *work); | 1003 | static void s2io_set_link(struct work_struct *work); |
1004 | static int s2io_set_swapper(nic_t * sp); | 1004 | static int s2io_set_swapper(struct s2io_nic * sp); |
1005 | static void s2io_card_down(nic_t *nic); | 1005 | static void s2io_card_down(struct s2io_nic *nic); |
1006 | static int s2io_card_up(nic_t *nic); | 1006 | static int s2io_card_up(struct s2io_nic *nic); |
1007 | static int get_xena_rev_id(struct pci_dev *pdev); | 1007 | static int get_xena_rev_id(struct pci_dev *pdev); |
1008 | static void restore_xmsi_data(nic_t *nic); | 1008 | static int wait_for_cmd_complete(void *addr, u64 busy_bit); |
1009 | static int s2io_add_isr(struct s2io_nic * sp); | ||
1010 | static void s2io_rem_isr(struct s2io_nic * sp); | ||
1011 | |||
1012 | static void restore_xmsi_data(struct s2io_nic *nic); | ||
1009 | 1013 | ||
1010 | static int s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro, RxD_t *rxdp, nic_t *sp); | 1014 | static int |
1011 | static void clear_lro_session(lro_t *lro); | 1015 | s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro, |
1016 | struct RxD_t *rxdp, struct s2io_nic *sp); | ||
1017 | static void clear_lro_session(struct lro *lro); | ||
1012 | static void queue_rx_frame(struct sk_buff *skb); | 1018 | static void queue_rx_frame(struct sk_buff *skb); |
1013 | static void update_L3L4_header(nic_t *sp, lro_t *lro); | 1019 | static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); |
1014 | static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb, u32 tcp_len); | 1020 | static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, |
1021 | struct sk_buff *skb, u32 tcp_len); | ||
1015 | 1022 | ||
1016 | #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size | 1023 | #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size |
1017 | #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size | 1024 | #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size |