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authorAnanda Raju <Ananda.Raju@neterion.com>2006-04-21 19:03:13 -0400
committerJeff Garzik <jeff@garzik.org>2006-05-02 15:16:35 -0400
commit863c11a91e4507c3ff44783a75a5433c8cf7700e (patch)
treef1a3e065ed6787c693b8b56418c571dc950bdb88 /drivers/net/s2io-regs.h
parent1fb5fef9b80d9a3b5368e22031627afd1585487b (diff)
[PATCH] s2io: performance improvements
hi, This patch contains all the changes that were done to improve performance of s2io driver. one line description of the changes are 1. For Non NAPI case the rx interrupt handler is being called unconditionally 2. code optimization and adding prefetch skb->data 3. Remove modulo operations in fast path 4. Enable Group Reads and set backoff interval to 0x1000 5. correct PIC_CNTL_SHARED_SPLITS macro definition, and reduce pause parameter 6. Corrected logic of identifying rx buffer level in rx_buffer_level() 7. fix DMA map and unmap done with different sizes in 1-buf mode 8. Removed forcible disabling of ERO 9. Send up the packets with transfer code = 0x5 Signed-off-by: Ananda Raju <ananda.raju@neterion.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/s2io-regs.h')
-rw-r--r--drivers/net/s2io-regs.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
index 00179bc3437f..542ae1574801 100644
--- a/drivers/net/s2io-regs.h
+++ b/drivers/net/s2io-regs.h
@@ -187,7 +187,7 @@ typedef struct _XENA_dev_config {
187/* PIC Control registers */ 187/* PIC Control registers */
188 u64 pic_control; 188 u64 pic_control;
189#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0) 189#define PIC_CNTL_RX_ALARM_MAP_1 BIT(0)
190#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,4) 190#define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5)
191 191
192 u64 swapper_ctrl; 192 u64 swapper_ctrl;
193#define SWAPPER_CTRL_PIF_R_FE BIT(0) 193#define SWAPPER_CTRL_PIF_R_FE BIT(0)
@@ -284,9 +284,13 @@ typedef struct _XENA_dev_config {
284 u64 gpio_control; 284 u64 gpio_control;
285#define GPIO_CTRL_GPIO_0 BIT(8) 285#define GPIO_CTRL_GPIO_0 BIT(8)
286 u64 misc_control; 286 u64 misc_control;
287#define EXT_REQ_EN BIT(1)
287#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) 288#define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3)
288 289
289 u8 unused7_1[0x240 - 0x208]; 290 u8 unused7_1[0x230 - 0x208];
291
292 u64 pic_control2;
293 u64 ini_dperr_ctrl;
290 294
291 u64 wreq_split_mask; 295 u64 wreq_split_mask;
292#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) 296#define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12)
@@ -493,6 +497,7 @@ typedef struct _XENA_dev_config {
493#define PRC_CTRL_NO_SNOOP_DESC BIT(22) 497#define PRC_CTRL_NO_SNOOP_DESC BIT(22)
494#define PRC_CTRL_NO_SNOOP_BUFF BIT(23) 498#define PRC_CTRL_NO_SNOOP_BUFF BIT(23)
495#define PRC_CTRL_BIMODAL_INTERRUPT BIT(37) 499#define PRC_CTRL_BIMODAL_INTERRUPT BIT(37)
500#define PRC_CTRL_GROUP_READS BIT(38)
496#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 501#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24)
497 502
498 u64 prc_alarm_action; 503 u64 prc_alarm_action;