[PATCH] S2io: Hardware fixes

Hi,
Below patch addresses few h/w specific issues.
1. Check for additional ownership bit on Rx path before
   starting Rx processing.
2. Enable only 4 PCCs(Per Context Controller) for Xframe I
   revisions less than 4.
3. Program Rx and Tx round robin registers depending on
   no. of rings/FIFOs.
4. Tx continous interrupts is now a loadable parameter.
5. Reset the card if we get double-bit ECC errors.
6. A soft reset of XGXS being done to force a link state change has been
   eliminated.
7. After a reset, clear "parity error detected" bit,
   PCI-X ECC status register, and PCI_STATUS bit in
   tx_pic_int register.
8. The error in the disabling allmulticast implementation has been
   rectified.
9. Leave the PCI-X parameters MMRBC, OST etc. at their
   BIOS/system defaults.

Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com>
Signed-off-by: Raghavendra Koushik <raghavendra.koushik@neterion.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h
index 8746740e6efd..826deb0eb03a 100644
--- a/drivers/net/s2io-regs.h
+++ b/drivers/net/s2io-regs.h
@@ -62,6 +62,7 @@ typedef struct _XENA_dev_config {
 #define ADAPTER_STATUS_RMAC_REMOTE_FAULT   BIT(6)
 #define ADAPTER_STATUS_RMAC_LOCAL_FAULT    BIT(7)
 #define ADAPTER_STATUS_RMAC_PCC_IDLE       vBIT(0xFF,8,8)
+#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE  vBIT(0x0F,8,8)
 #define ADAPTER_STATUS_RC_PRC_QUIESCENT    vBIT(0xFF,16,8)
 #define ADAPTER_STATUS_MC_DRAM_READY       BIT(24)
 #define ADAPTER_STATUS_MC_QUEUES_READY     BIT(25)
@@ -245,6 +246,7 @@ typedef struct _XENA_dev_config {
 #define STAT_TRSF_PER(n)           TBD
 #define PER_SEC                                    0x208d5
 #define SET_UPDT_PERIOD(n)                 vBIT((PER_SEC*n),32,32)
+#define SET_UPDT_CLICKS(val)               vBIT(val, 32, 32)
 
         u64 stat_addr;
 
@@ -289,6 +291,7 @@ typedef struct _XENA_dev_config {
 
         u64 pcc_err_reg;
 #define PCC_FB_ECC_DB_ERR               vBIT(0xFF, 16, 8)
+#define PCC_ENABLE_FOUR                 vBIT(0x0F,0,8)
 
         u64 pcc_err_mask;
         u64 pcc_err_alarm;
@@ -690,6 +693,10 @@ typedef struct _XENA_dev_config {
 #define MC_ERR_REG_MIRI_CRI_ERR_0          BIT(22)
 #define MC_ERR_REG_MIRI_CRI_ERR_1          BIT(23)
 #define MC_ERR_REG_SM_ERR                  BIT(31)
+#define MC_ERR_REG_ECC_ALL_SNG             (BIT(6) | \
+                                        BIT(7) | BIT(17) | BIT(19))
+#define MC_ERR_REG_ECC_ALL_DBL             (BIT(14) | \
+                                        BIT(15) | BIT(18) | BIT(20))
         u64 mc_err_mask;
         u64 mc_err_alarm;