diff options
| author | Jiri Slaby <jirislaby@gmail.com> | 2007-10-19 02:40:29 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-19 14:53:42 -0400 |
| commit | b7b5a1282c37e1acf6c10391664ef9d6ad58e933 (patch) | |
| tree | 789633b7d7d9434b99110fc25102a997b523859b /drivers/net/s2io-regs.h | |
| parent | ed11399da5ac7a07dc470d9dee9a7846917ec4aa (diff) | |
s2io, rename BIT macro
s2io, rename BIT macro
BIT macro will be global definiton of (1<<x)
Signed-off-by: Jiri Slaby <jirislaby@gmail.com>
Cc: Ramkrishna Vepa <ram.vepa@neterion.com>
Cc: Rastapur Santosh <santosh.rastapur@neterion.com>
Cc: Sivakumar Subramani <sivakumar.subramani@neterion.com>
Cc: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
Cc: Jeff Garzik <jeff@garzik.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'drivers/net/s2io-regs.h')
| -rw-r--r-- | drivers/net/s2io-regs.h | 632 |
1 files changed, 316 insertions, 316 deletions
diff --git a/drivers/net/s2io-regs.h b/drivers/net/s2io-regs.h index aef66e2d98d2..01f08d726ace 100644 --- a/drivers/net/s2io-regs.h +++ b/drivers/net/s2io-regs.h | |||
| @@ -20,17 +20,17 @@ struct XENA_dev_config { | |||
| 20 | 20 | ||
| 21 | /* General Control-Status Registers */ | 21 | /* General Control-Status Registers */ |
| 22 | u64 general_int_status; | 22 | u64 general_int_status; |
| 23 | #define GEN_INTR_TXPIC BIT(0) | 23 | #define GEN_INTR_TXPIC s2BIT(0) |
| 24 | #define GEN_INTR_TXDMA BIT(1) | 24 | #define GEN_INTR_TXDMA s2BIT(1) |
| 25 | #define GEN_INTR_TXMAC BIT(2) | 25 | #define GEN_INTR_TXMAC s2BIT(2) |
| 26 | #define GEN_INTR_TXXGXS BIT(3) | 26 | #define GEN_INTR_TXXGXS s2BIT(3) |
| 27 | #define GEN_INTR_TXTRAFFIC BIT(8) | 27 | #define GEN_INTR_TXTRAFFIC s2BIT(8) |
| 28 | #define GEN_INTR_RXPIC BIT(32) | 28 | #define GEN_INTR_RXPIC s2BIT(32) |
| 29 | #define GEN_INTR_RXDMA BIT(33) | 29 | #define GEN_INTR_RXDMA s2BIT(33) |
| 30 | #define GEN_INTR_RXMAC BIT(34) | 30 | #define GEN_INTR_RXMAC s2BIT(34) |
| 31 | #define GEN_INTR_MC BIT(35) | 31 | #define GEN_INTR_MC s2BIT(35) |
| 32 | #define GEN_INTR_RXXGXS BIT(36) | 32 | #define GEN_INTR_RXXGXS s2BIT(36) |
| 33 | #define GEN_INTR_RXTRAFFIC BIT(40) | 33 | #define GEN_INTR_RXTRAFFIC s2BIT(40) |
| 34 | #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \ | 34 | #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \ |
| 35 | GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ | 35 | GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ |
| 36 | GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ | 36 | GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ |
| @@ -54,36 +54,36 @@ struct XENA_dev_config { | |||
| 54 | 54 | ||
| 55 | 55 | ||
| 56 | u64 adapter_status; | 56 | u64 adapter_status; |
| 57 | #define ADAPTER_STATUS_TDMA_READY BIT(0) | 57 | #define ADAPTER_STATUS_TDMA_READY s2BIT(0) |
| 58 | #define ADAPTER_STATUS_RDMA_READY BIT(1) | 58 | #define ADAPTER_STATUS_RDMA_READY s2BIT(1) |
| 59 | #define ADAPTER_STATUS_PFC_READY BIT(2) | 59 | #define ADAPTER_STATUS_PFC_READY s2BIT(2) |
| 60 | #define ADAPTER_STATUS_TMAC_BUF_EMPTY BIT(3) | 60 | #define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3) |
| 61 | #define ADAPTER_STATUS_PIC_QUIESCENT BIT(5) | 61 | #define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5) |
| 62 | #define ADAPTER_STATUS_RMAC_REMOTE_FAULT BIT(6) | 62 | #define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6) |
| 63 | #define ADAPTER_STATUS_RMAC_LOCAL_FAULT BIT(7) | 63 | #define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7) |
| 64 | #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) | 64 | #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) |
| 65 | #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8) | 65 | #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8) |
| 66 | #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) | 66 | #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) |
| 67 | #define ADAPTER_STATUS_MC_DRAM_READY BIT(24) | 67 | #define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24) |
| 68 | #define ADAPTER_STATUS_MC_QUEUES_READY BIT(25) | 68 | #define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25) |
| 69 | #define ADAPTER_STATUS_M_PLL_LOCK BIT(30) | 69 | #define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30) |
| 70 | #define ADAPTER_STATUS_P_PLL_LOCK BIT(31) | 70 | #define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31) |
| 71 | 71 | ||
| 72 | u64 adapter_control; | 72 | u64 adapter_control; |
| 73 | #define ADAPTER_CNTL_EN BIT(7) | 73 | #define ADAPTER_CNTL_EN s2BIT(7) |
| 74 | #define ADAPTER_EOI_TX_ON BIT(15) | 74 | #define ADAPTER_EOI_TX_ON s2BIT(15) |
| 75 | #define ADAPTER_LED_ON BIT(23) | 75 | #define ADAPTER_LED_ON s2BIT(23) |
| 76 | #define ADAPTER_UDPI(val) vBIT(val,36,4) | 76 | #define ADAPTER_UDPI(val) vBIT(val,36,4) |
| 77 | #define ADAPTER_WAIT_INT BIT(48) | 77 | #define ADAPTER_WAIT_INT s2BIT(48) |
| 78 | #define ADAPTER_ECC_EN BIT(55) | 78 | #define ADAPTER_ECC_EN s2BIT(55) |
| 79 | 79 | ||
| 80 | u64 serr_source; | 80 | u64 serr_source; |
| 81 | #define SERR_SOURCE_PIC BIT(0) | 81 | #define SERR_SOURCE_PIC s2BIT(0) |
| 82 | #define SERR_SOURCE_TXDMA BIT(1) | 82 | #define SERR_SOURCE_TXDMA s2BIT(1) |
| 83 | #define SERR_SOURCE_RXDMA BIT(2) | 83 | #define SERR_SOURCE_RXDMA s2BIT(2) |
| 84 | #define SERR_SOURCE_MAC BIT(3) | 84 | #define SERR_SOURCE_MAC s2BIT(3) |
| 85 | #define SERR_SOURCE_MC BIT(4) | 85 | #define SERR_SOURCE_MC s2BIT(4) |
| 86 | #define SERR_SOURCE_XGXS BIT(5) | 86 | #define SERR_SOURCE_XGXS s2BIT(5) |
| 87 | #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ | 87 | #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ |
| 88 | SERR_SOURCE_TXDMA | \ | 88 | SERR_SOURCE_TXDMA | \ |
| 89 | SERR_SOURCE_RXDMA | \ | 89 | SERR_SOURCE_RXDMA | \ |
| @@ -101,41 +101,41 @@ struct XENA_dev_config { | |||
| 101 | #define PCI_MODE_PCIX_M2_66 0x5 | 101 | #define PCI_MODE_PCIX_M2_66 0x5 |
| 102 | #define PCI_MODE_PCIX_M2_100 0x6 | 102 | #define PCI_MODE_PCIX_M2_100 0x6 |
| 103 | #define PCI_MODE_PCIX_M2_133 0x7 | 103 | #define PCI_MODE_PCIX_M2_133 0x7 |
| 104 | #define PCI_MODE_UNSUPPORTED BIT(0) | 104 | #define PCI_MODE_UNSUPPORTED s2BIT(0) |
| 105 | #define PCI_MODE_32_BITS BIT(8) | 105 | #define PCI_MODE_32_BITS s2BIT(8) |
| 106 | #define PCI_MODE_UNKNOWN_MODE BIT(9) | 106 | #define PCI_MODE_UNKNOWN_MODE s2BIT(9) |
| 107 | 107 | ||
| 108 | u8 unused_0[0x800 - 0x128]; | 108 | u8 unused_0[0x800 - 0x128]; |
| 109 | 109 | ||
| 110 | /* PCI-X Controller registers */ | 110 | /* PCI-X Controller registers */ |
| 111 | u64 pic_int_status; | 111 | u64 pic_int_status; |
| 112 | u64 pic_int_mask; | 112 | u64 pic_int_mask; |
| 113 | #define PIC_INT_TX BIT(0) | 113 | #define PIC_INT_TX s2BIT(0) |
| 114 | #define PIC_INT_FLSH BIT(1) | 114 | #define PIC_INT_FLSH s2BIT(1) |
| 115 | #define PIC_INT_MDIO BIT(2) | 115 | #define PIC_INT_MDIO s2BIT(2) |
| 116 | #define PIC_INT_IIC BIT(3) | 116 | #define PIC_INT_IIC s2BIT(3) |
| 117 | #define PIC_INT_GPIO BIT(4) | 117 | #define PIC_INT_GPIO s2BIT(4) |
| 118 | #define PIC_INT_RX BIT(32) | 118 | #define PIC_INT_RX s2BIT(32) |
| 119 | 119 | ||
| 120 | u64 txpic_int_reg; | 120 | u64 txpic_int_reg; |
| 121 | u64 txpic_int_mask; | 121 | u64 txpic_int_mask; |
| 122 | #define PCIX_INT_REG_ECC_SG_ERR BIT(0) | 122 | #define PCIX_INT_REG_ECC_SG_ERR s2BIT(0) |
| 123 | #define PCIX_INT_REG_ECC_DB_ERR BIT(1) | 123 | #define PCIX_INT_REG_ECC_DB_ERR s2BIT(1) |
| 124 | #define PCIX_INT_REG_FLASHR_R_FSM_ERR BIT(8) | 124 | #define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8) |
| 125 | #define PCIX_INT_REG_FLASHR_W_FSM_ERR BIT(9) | 125 | #define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9) |
| 126 | #define PCIX_INT_REG_INI_TX_FSM_SERR BIT(10) | 126 | #define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10) |
| 127 | #define PCIX_INT_REG_INI_TXO_FSM_ERR BIT(11) | 127 | #define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11) |
| 128 | #define PCIX_INT_REG_TRT_FSM_SERR BIT(13) | 128 | #define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13) |
| 129 | #define PCIX_INT_REG_SRT_FSM_SERR BIT(14) | 129 | #define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14) |
| 130 | #define PCIX_INT_REG_PIFR_FSM_SERR BIT(15) | 130 | #define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15) |
| 131 | #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR BIT(21) | 131 | #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21) |
| 132 | #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR BIT(23) | 132 | #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23) |
| 133 | #define PCIX_INT_REG_INI_RX_FSM_SERR BIT(48) | 133 | #define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48) |
| 134 | #define PCIX_INT_REG_RA_RX_FSM_SERR BIT(50) | 134 | #define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50) |
| 135 | /* | 135 | /* |
| 136 | #define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR BIT(52) | 136 | #define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52) |
| 137 | #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR BIT(54) | 137 | #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54) |
| 138 | #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR BIT(58) | 138 | #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58) |
| 139 | */ | 139 | */ |
| 140 | u64 txpic_alarms; | 140 | u64 txpic_alarms; |
| 141 | u64 rxpic_int_reg; | 141 | u64 rxpic_int_reg; |
| @@ -144,92 +144,92 @@ struct XENA_dev_config { | |||
| 144 | 144 | ||
| 145 | u64 flsh_int_reg; | 145 | u64 flsh_int_reg; |
| 146 | u64 flsh_int_mask; | 146 | u64 flsh_int_mask; |
| 147 | #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR BIT(63) | 147 | #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63) |
| 148 | #define PIC_FLSH_INT_REG_ERR BIT(62) | 148 | #define PIC_FLSH_INT_REG_ERR s2BIT(62) |
| 149 | u64 flash_alarms; | 149 | u64 flash_alarms; |
| 150 | 150 | ||
| 151 | u64 mdio_int_reg; | 151 | u64 mdio_int_reg; |
| 152 | u64 mdio_int_mask; | 152 | u64 mdio_int_mask; |
| 153 | #define MDIO_INT_REG_MDIO_BUS_ERR BIT(0) | 153 | #define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0) |
| 154 | #define MDIO_INT_REG_DTX_BUS_ERR BIT(8) | 154 | #define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8) |
| 155 | #define MDIO_INT_REG_LASI BIT(39) | 155 | #define MDIO_INT_REG_LASI s2BIT(39) |
| 156 | u64 mdio_alarms; | 156 | u64 mdio_alarms; |
| 157 | 157 | ||
| 158 | u64 iic_int_reg; | 158 | u64 iic_int_reg; |
| 159 | u64 iic_int_mask; | 159 | u64 iic_int_mask; |
| 160 | #define IIC_INT_REG_BUS_FSM_ERR BIT(4) | 160 | #define IIC_INT_REG_BUS_FSM_ERR s2BIT(4) |
| 161 | #define IIC_INT_REG_BIT_FSM_ERR BIT(5) | 161 | #define IIC_INT_REG_BIT_FSM_ERR s2BIT(5) |
| 162 | #define IIC_INT_REG_CYCLE_FSM_ERR BIT(6) | 162 | #define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6) |
| 163 | #define IIC_INT_REG_REQ_FSM_ERR BIT(7) | 163 | #define IIC_INT_REG_REQ_FSM_ERR s2BIT(7) |
| 164 | #define IIC_INT_REG_ACK_ERR BIT(8) | 164 | #define IIC_INT_REG_ACK_ERR s2BIT(8) |
| 165 | u64 iic_alarms; | 165 | u64 iic_alarms; |
| 166 | 166 | ||
| 167 | u8 unused4[0x08]; | 167 | u8 unused4[0x08]; |
| 168 | 168 | ||
| 169 | u64 gpio_int_reg; | 169 | u64 gpio_int_reg; |
| 170 | #define GPIO_INT_REG_DP_ERR_INT BIT(0) | 170 | #define GPIO_INT_REG_DP_ERR_INT s2BIT(0) |
| 171 | #define GPIO_INT_REG_LINK_DOWN BIT(1) | 171 | #define GPIO_INT_REG_LINK_DOWN s2BIT(1) |
| 172 | #define GPIO_INT_REG_LINK_UP BIT(2) | 172 | #define GPIO_INT_REG_LINK_UP s2BIT(2) |
| 173 | u64 gpio_int_mask; | 173 | u64 gpio_int_mask; |
| 174 | #define GPIO_INT_MASK_LINK_DOWN BIT(1) | 174 | #define GPIO_INT_MASK_LINK_DOWN s2BIT(1) |
| 175 | #define GPIO_INT_MASK_LINK_UP BIT(2) | 175 | #define GPIO_INT_MASK_LINK_UP s2BIT(2) |
| 176 | u64 gpio_alarms; | 176 | u64 gpio_alarms; |
| 177 | 177 | ||
| 178 | u8 unused5[0x38]; | 178 | u8 unused5[0x38]; |
| 179 | 179 | ||
| 180 | u64 tx_traffic_int; | 180 | u64 tx_traffic_int; |
| 181 | #define TX_TRAFFIC_INT_n(n) BIT(n) | 181 | #define TX_TRAFFIC_INT_n(n) s2BIT(n) |
| 182 | u64 tx_traffic_mask; | 182 | u64 tx_traffic_mask; |
| 183 | 183 | ||
| 184 | u64 rx_traffic_int; | 184 | u64 rx_traffic_int; |
| 185 | #define RX_TRAFFIC_INT_n(n) BIT(n) | 185 | #define RX_TRAFFIC_INT_n(n) s2BIT(n) |
| 186 | u64 rx_traffic_mask; | 186 | u64 rx_traffic_mask; |
| 187 | 187 | ||
| 188 | /* PIC Control registers */ | 188 | /* PIC Control registers */ |
| 189 | u64 pic_control; | 189 | u64 pic_control; |
| 190 | #define PIC_CNTL_RX_ALARM_MAP_1 BIT(0) | 190 | #define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0) |
| 191 | #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5) | 191 | #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5) |
| 192 | 192 | ||
| 193 | u64 swapper_ctrl; | 193 | u64 swapper_ctrl; |
| 194 | #define SWAPPER_CTRL_PIF_R_FE BIT(0) | 194 | #define SWAPPER_CTRL_PIF_R_FE s2BIT(0) |
| 195 | #define SWAPPER_CTRL_PIF_R_SE BIT(1) | 195 | #define SWAPPER_CTRL_PIF_R_SE s2BIT(1) |
| 196 | #define SWAPPER_CTRL_PIF_W_FE BIT(8) | 196 | #define SWAPPER_CTRL_PIF_W_FE s2BIT(8) |
| 197 | #define SWAPPER_CTRL_PIF_W_SE BIT(9) | 197 | #define SWAPPER_CTRL_PIF_W_SE s2BIT(9) |
| 198 | #define SWAPPER_CTRL_TXP_FE BIT(16) | 198 | #define SWAPPER_CTRL_TXP_FE s2BIT(16) |
| 199 | #define SWAPPER_CTRL_TXP_SE BIT(17) | 199 | #define SWAPPER_CTRL_TXP_SE s2BIT(17) |
| 200 | #define SWAPPER_CTRL_TXD_R_FE BIT(18) | 200 | #define SWAPPER_CTRL_TXD_R_FE s2BIT(18) |
| 201 | #define SWAPPER_CTRL_TXD_R_SE BIT(19) | 201 | #define SWAPPER_CTRL_TXD_R_SE s2BIT(19) |
| 202 | #define SWAPPER_CTRL_TXD_W_FE BIT(20) | 202 | #define SWAPPER_CTRL_TXD_W_FE s2BIT(20) |
| 203 | #define SWAPPER_CTRL_TXD_W_SE BIT(21) | 203 | #define SWAPPER_CTRL_TXD_W_SE s2BIT(21) |
| 204 | #define SWAPPER_CTRL_TXF_R_FE BIT(22) | 204 | #define SWAPPER_CTRL_TXF_R_FE s2BIT(22) |
| 205 | #define SWAPPER_CTRL_TXF_R_SE BIT(23) | 205 | #define SWAPPER_CTRL_TXF_R_SE s2BIT(23) |
| 206 | #define SWAPPER_CTRL_RXD_R_FE BIT(32) | 206 | #define SWAPPER_CTRL_RXD_R_FE s2BIT(32) |
| 207 | #define SWAPPER_CTRL_RXD_R_SE BIT(33) | 207 | #define SWAPPER_CTRL_RXD_R_SE s2BIT(33) |
| 208 | #define SWAPPER_CTRL_RXD_W_FE BIT(34) | 208 | #define SWAPPER_CTRL_RXD_W_FE s2BIT(34) |
| 209 | #define SWAPPER_CTRL_RXD_W_SE BIT(35) | 209 | #define SWAPPER_CTRL_RXD_W_SE s2BIT(35) |
| 210 | #define SWAPPER_CTRL_RXF_W_FE BIT(36) | 210 | #define SWAPPER_CTRL_RXF_W_FE s2BIT(36) |
| 211 | #define SWAPPER_CTRL_RXF_W_SE BIT(37) | 211 | #define SWAPPER_CTRL_RXF_W_SE s2BIT(37) |
| 212 | #define SWAPPER_CTRL_XMSI_FE BIT(40) | 212 | #define SWAPPER_CTRL_XMSI_FE s2BIT(40) |
| 213 | #define SWAPPER_CTRL_XMSI_SE BIT(41) | 213 | #define SWAPPER_CTRL_XMSI_SE s2BIT(41) |
| 214 | #define SWAPPER_CTRL_STATS_FE BIT(48) | 214 | #define SWAPPER_CTRL_STATS_FE s2BIT(48) |
| 215 | #define SWAPPER_CTRL_STATS_SE BIT(49) | 215 | #define SWAPPER_CTRL_STATS_SE s2BIT(49) |
| 216 | 216 | ||
| 217 | u64 pif_rd_swapper_fb; | 217 | u64 pif_rd_swapper_fb; |
| 218 | #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF | 218 | #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF |
| 219 | 219 | ||
| 220 | u64 scheduled_int_ctrl; | 220 | u64 scheduled_int_ctrl; |
| 221 | #define SCHED_INT_CTRL_TIMER_EN BIT(0) | 221 | #define SCHED_INT_CTRL_TIMER_EN s2BIT(0) |
| 222 | #define SCHED_INT_CTRL_ONE_SHOT BIT(1) | 222 | #define SCHED_INT_CTRL_ONE_SHOT s2BIT(1) |
| 223 | #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) | 223 | #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) |
| 224 | #define SCHED_INT_PERIOD TBD | 224 | #define SCHED_INT_PERIOD TBD |
| 225 | 225 | ||
| 226 | u64 txreqtimeout; | 226 | u64 txreqtimeout; |
| 227 | #define TXREQTO_VAL(val) vBIT(val,0,32) | 227 | #define TXREQTO_VAL(val) vBIT(val,0,32) |
| 228 | #define TXREQTO_EN BIT(63) | 228 | #define TXREQTO_EN s2BIT(63) |
| 229 | 229 | ||
| 230 | u64 statsreqtimeout; | 230 | u64 statsreqtimeout; |
| 231 | #define STATREQTO_VAL(n) TBD | 231 | #define STATREQTO_VAL(n) TBD |
| 232 | #define STATREQTO_EN BIT(63) | 232 | #define STATREQTO_EN s2BIT(63) |
| 233 | 233 | ||
| 234 | u64 read_retry_delay; | 234 | u64 read_retry_delay; |
| 235 | u64 read_retry_acceleration; | 235 | u64 read_retry_acceleration; |
| @@ -255,10 +255,10 @@ struct XENA_dev_config { | |||
| 255 | 255 | ||
| 256 | /* Automated statistics collection */ | 256 | /* Automated statistics collection */ |
| 257 | u64 stat_cfg; | 257 | u64 stat_cfg; |
| 258 | #define STAT_CFG_STAT_EN BIT(0) | 258 | #define STAT_CFG_STAT_EN s2BIT(0) |
| 259 | #define STAT_CFG_ONE_SHOT_EN BIT(1) | 259 | #define STAT_CFG_ONE_SHOT_EN s2BIT(1) |
| 260 | #define STAT_CFG_STAT_NS_EN BIT(8) | 260 | #define STAT_CFG_STAT_NS_EN s2BIT(8) |
| 261 | #define STAT_CFG_STAT_RO BIT(9) | 261 | #define STAT_CFG_STAT_RO s2BIT(9) |
| 262 | #define STAT_TRSF_PER(n) TBD | 262 | #define STAT_TRSF_PER(n) TBD |
| 263 | #define PER_SEC 0x208d5 | 263 | #define PER_SEC 0x208d5 |
| 264 | #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32) | 264 | #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32) |
| @@ -290,18 +290,18 @@ struct XENA_dev_config { | |||
| 290 | #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) | 290 | #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) |
| 291 | #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) | 291 | #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) |
| 292 | #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) | 292 | #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) |
| 293 | #define I2C_CONTROL_READ BIT(24) | 293 | #define I2C_CONTROL_READ s2BIT(24) |
| 294 | #define I2C_CONTROL_NACK BIT(25) | 294 | #define I2C_CONTROL_NACK s2BIT(25) |
| 295 | #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4) | 295 | #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4) |
| 296 | #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) | 296 | #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) |
| 297 | #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) | 297 | #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) |
| 298 | #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) | 298 | #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) |
| 299 | 299 | ||
| 300 | u64 gpio_control; | 300 | u64 gpio_control; |
| 301 | #define GPIO_CTRL_GPIO_0 BIT(8) | 301 | #define GPIO_CTRL_GPIO_0 s2BIT(8) |
| 302 | u64 misc_control; | 302 | u64 misc_control; |
| 303 | #define FAULT_BEHAVIOUR BIT(0) | 303 | #define FAULT_BEHAVIOUR s2BIT(0) |
| 304 | #define EXT_REQ_EN BIT(1) | 304 | #define EXT_REQ_EN s2BIT(1) |
| 305 | #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) | 305 | #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) |
| 306 | 306 | ||
| 307 | u8 unused7_1[0x230 - 0x208]; | 307 | u8 unused7_1[0x230 - 0x208]; |
| @@ -317,29 +317,29 @@ struct XENA_dev_config { | |||
| 317 | /* TxDMA registers */ | 317 | /* TxDMA registers */ |
| 318 | u64 txdma_int_status; | 318 | u64 txdma_int_status; |
| 319 | u64 txdma_int_mask; | 319 | u64 txdma_int_mask; |
| 320 | #define TXDMA_PFC_INT BIT(0) | 320 | #define TXDMA_PFC_INT s2BIT(0) |
| 321 | #define TXDMA_TDA_INT BIT(1) | 321 | #define TXDMA_TDA_INT s2BIT(1) |
| 322 | #define TXDMA_PCC_INT BIT(2) | 322 | #define TXDMA_PCC_INT s2BIT(2) |
| 323 | #define TXDMA_TTI_INT BIT(3) | 323 | #define TXDMA_TTI_INT s2BIT(3) |
| 324 | #define TXDMA_LSO_INT BIT(4) | 324 | #define TXDMA_LSO_INT s2BIT(4) |
| 325 | #define TXDMA_TPA_INT BIT(5) | 325 | #define TXDMA_TPA_INT s2BIT(5) |
| 326 | #define TXDMA_SM_INT BIT(6) | 326 | #define TXDMA_SM_INT s2BIT(6) |
| 327 | u64 pfc_err_reg; | 327 | u64 pfc_err_reg; |
| 328 | #define PFC_ECC_SG_ERR BIT(7) | 328 | #define PFC_ECC_SG_ERR s2BIT(7) |
| 329 | #define PFC_ECC_DB_ERR BIT(15) | 329 | #define PFC_ECC_DB_ERR s2BIT(15) |
| 330 | #define PFC_SM_ERR_ALARM BIT(23) | 330 | #define PFC_SM_ERR_ALARM s2BIT(23) |
| 331 | #define PFC_MISC_0_ERR BIT(31) | 331 | #define PFC_MISC_0_ERR s2BIT(31) |
| 332 | #define PFC_MISC_1_ERR BIT(32) | 332 | #define PFC_MISC_1_ERR s2BIT(32) |
| 333 | #define PFC_PCIX_ERR BIT(39) | 333 | #define PFC_PCIX_ERR s2BIT(39) |
| 334 | u64 pfc_err_mask; | 334 | u64 pfc_err_mask; |
| 335 | u64 pfc_err_alarm; | 335 | u64 pfc_err_alarm; |
| 336 | 336 | ||
| 337 | u64 tda_err_reg; | 337 | u64 tda_err_reg; |
| 338 | #define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) | 338 | #define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) |
| 339 | #define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) | 339 | #define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) |
| 340 | #define TDA_SM0_ERR_ALARM BIT(22) | 340 | #define TDA_SM0_ERR_ALARM s2BIT(22) |
| 341 | #define TDA_SM1_ERR_ALARM BIT(23) | 341 | #define TDA_SM1_ERR_ALARM s2BIT(23) |
| 342 | #define TDA_PCIX_ERR BIT(39) | 342 | #define TDA_PCIX_ERR s2BIT(39) |
| 343 | u64 tda_err_mask; | 343 | u64 tda_err_mask; |
| 344 | u64 tda_err_alarm; | 344 | u64 tda_err_alarm; |
| 345 | 345 | ||
| @@ -351,40 +351,40 @@ struct XENA_dev_config { | |||
| 351 | #define PCC_SM_ERR_ALARM vBIT(0xff,32,8) | 351 | #define PCC_SM_ERR_ALARM vBIT(0xff,32,8) |
| 352 | #define PCC_WR_ERR_ALARM vBIT(0xff,40,8) | 352 | #define PCC_WR_ERR_ALARM vBIT(0xff,40,8) |
| 353 | #define PCC_N_SERR vBIT(0xff,48,8) | 353 | #define PCC_N_SERR vBIT(0xff,48,8) |
| 354 | #define PCC_6_COF_OV_ERR BIT(56) | 354 | #define PCC_6_COF_OV_ERR s2BIT(56) |
| 355 | #define PCC_7_COF_OV_ERR BIT(57) | 355 | #define PCC_7_COF_OV_ERR s2BIT(57) |
| 356 | #define PCC_6_LSO_OV_ERR BIT(58) | 356 | #define PCC_6_LSO_OV_ERR s2BIT(58) |
| 357 | #define PCC_7_LSO_OV_ERR BIT(59) | 357 | #define PCC_7_LSO_OV_ERR s2BIT(59) |
| 358 | #define PCC_ENABLE_FOUR vBIT(0x0F,0,8) | 358 | #define PCC_ENABLE_FOUR vBIT(0x0F,0,8) |
| 359 | u64 pcc_err_mask; | 359 | u64 pcc_err_mask; |
| 360 | u64 pcc_err_alarm; | 360 | u64 pcc_err_alarm; |
| 361 | 361 | ||
| 362 | u64 tti_err_reg; | 362 | u64 tti_err_reg; |
| 363 | #define TTI_ECC_SG_ERR BIT(7) | 363 | #define TTI_ECC_SG_ERR s2BIT(7) |
| 364 | #define TTI_ECC_DB_ERR BIT(15) | 364 | #define TTI_ECC_DB_ERR s2BIT(15) |
| 365 | #define TTI_SM_ERR_ALARM BIT(23) | 365 | #define TTI_SM_ERR_ALARM s2BIT(23) |
| 366 | u64 tti_err_mask; | 366 | u64 tti_err_mask; |
| 367 | u64 tti_err_alarm; | 367 | u64 tti_err_alarm; |
| 368 | 368 | ||
| 369 | u64 lso_err_reg; | 369 | u64 lso_err_reg; |
| 370 | #define LSO6_SEND_OFLOW BIT(12) | 370 | #define LSO6_SEND_OFLOW s2BIT(12) |
| 371 | #define LSO7_SEND_OFLOW BIT(13) | 371 | #define LSO7_SEND_OFLOW s2BIT(13) |
| 372 | #define LSO6_ABORT BIT(14) | 372 | #define LSO6_ABORT s2BIT(14) |
| 373 | #define LSO7_ABORT BIT(15) | 373 | #define LSO7_ABORT s2BIT(15) |
| 374 | #define LSO6_SM_ERR_ALARM BIT(22) | 374 | #define LSO6_SM_ERR_ALARM s2BIT(22) |
| 375 | #define LSO7_SM_ERR_ALARM BIT(23) | 375 | #define LSO7_SM_ERR_ALARM s2BIT(23) |
| 376 | u64 lso_err_mask; | 376 | u64 lso_err_mask; |
| 377 | u64 lso_err_alarm; | 377 | u64 lso_err_alarm; |
| 378 | 378 | ||
| 379 | u64 tpa_err_reg; | 379 | u64 tpa_err_reg; |
| 380 | #define TPA_TX_FRM_DROP BIT(7) | 380 | #define TPA_TX_FRM_DROP s2BIT(7) |
| 381 | #define TPA_SM_ERR_ALARM BIT(23) | 381 | #define TPA_SM_ERR_ALARM s2BIT(23) |
| 382 | 382 | ||
| 383 | u64 tpa_err_mask; | 383 | u64 tpa_err_mask; |
| 384 | u64 tpa_err_alarm; | 384 | u64 tpa_err_alarm; |
| 385 | 385 | ||
| 386 | u64 sm_err_reg; | 386 | u64 sm_err_reg; |
| 387 | #define SM_SM_ERR_ALARM BIT(15) | 387 | #define SM_SM_ERR_ALARM s2BIT(15) |
| 388 | u64 sm_err_mask; | 388 | u64 sm_err_mask; |
| 389 | u64 sm_err_alarm; | 389 | u64 sm_err_alarm; |
| 390 | 390 | ||
| @@ -397,7 +397,7 @@ struct XENA_dev_config { | |||
| 397 | #define X_MAX_FIFOS 8 | 397 | #define X_MAX_FIFOS 8 |
| 398 | #define X_FIFO_MAX_LEN 0x1FFF /*8191 */ | 398 | #define X_FIFO_MAX_LEN 0x1FFF /*8191 */ |
| 399 | u64 tx_fifo_partition_0; | 399 | u64 tx_fifo_partition_0; |
| 400 | #define TX_FIFO_PARTITION_EN BIT(0) | 400 | #define TX_FIFO_PARTITION_EN s2BIT(0) |
| 401 | #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) | 401 | #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) |
| 402 | #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) | 402 | #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) |
| 403 | #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) | 403 | #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) |
| @@ -437,16 +437,16 @@ struct XENA_dev_config { | |||
| 437 | u64 tx_w_round_robin_4; | 437 | u64 tx_w_round_robin_4; |
| 438 | 438 | ||
| 439 | u64 tti_command_mem; | 439 | u64 tti_command_mem; |
| 440 | #define TTI_CMD_MEM_WE BIT(7) | 440 | #define TTI_CMD_MEM_WE s2BIT(7) |
| 441 | #define TTI_CMD_MEM_STROBE_NEW_CMD BIT(15) | 441 | #define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15) |
| 442 | #define TTI_CMD_MEM_STROBE_BEING_EXECUTED BIT(15) | 442 | #define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15) |
| 443 | #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) | 443 | #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) |
| 444 | 444 | ||
| 445 | u64 tti_data1_mem; | 445 | u64 tti_data1_mem; |
| 446 | #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) | 446 | #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) |
| 447 | #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) | 447 | #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) |
| 448 | #define TTI_DATA1_MEM_TX_TIMER_AC_EN BIT(38) | 448 | #define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38) |
| 449 | #define TTI_DATA1_MEM_TX_TIMER_CI_EN BIT(39) | 449 | #define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39) |
| 450 | #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) | 450 | #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) |
| 451 | #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) | 451 | #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) |
| 452 | #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) | 452 | #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) |
| @@ -459,11 +459,11 @@ struct XENA_dev_config { | |||
| 459 | 459 | ||
| 460 | /* Tx Protocol assist */ | 460 | /* Tx Protocol assist */ |
| 461 | u64 tx_pa_cfg; | 461 | u64 tx_pa_cfg; |
| 462 | #define TX_PA_CFG_IGNORE_FRM_ERR BIT(1) | 462 | #define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1) |
| 463 | #define TX_PA_CFG_IGNORE_SNAP_OUI BIT(2) | 463 | #define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2) |
| 464 | #define TX_PA_CFG_IGNORE_LLC_CTRL BIT(3) | 464 | #define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3) |
| 465 | #define TX_PA_CFG_IGNORE_L2_ERR BIT(6) | 465 | #define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6) |
| 466 | #define RX_PA_CFG_STRIP_VLAN_TAG BIT(15) | 466 | #define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15) |
| 467 | 467 | ||
| 468 | /* Recent add, used only debug purposes. */ | 468 | /* Recent add, used only debug purposes. */ |
| 469 | u64 pcc_enable; | 469 | u64 pcc_enable; |
| @@ -477,31 +477,31 @@ struct XENA_dev_config { | |||
| 477 | /* RxDMA Registers */ | 477 | /* RxDMA Registers */ |
| 478 | u64 rxdma_int_status; | 478 | u64 rxdma_int_status; |
| 479 | u64 rxdma_int_mask; | 479 | u64 rxdma_int_mask; |
| 480 | #define RXDMA_INT_RC_INT_M BIT(0) | 480 | #define RXDMA_INT_RC_INT_M s2BIT(0) |
| 481 | #define RXDMA_INT_RPA_INT_M BIT(1) | 481 | #define RXDMA_INT_RPA_INT_M s2BIT(1) |
| 482 | #define RXDMA_INT_RDA_INT_M BIT(2) | 482 | #define RXDMA_INT_RDA_INT_M s2BIT(2) |
| 483 | #define RXDMA_INT_RTI_INT_M BIT(3) | 483 | #define RXDMA_INT_RTI_INT_M s2BIT(3) |
| 484 | 484 | ||
| 485 | u64 rda_err_reg; | 485 | u64 rda_err_reg; |
| 486 | #define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) | 486 | #define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) |
| 487 | #define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) | 487 | #define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) |
| 488 | #define RDA_FRM_ECC_SG_ERR BIT(23) | 488 | #define RDA_FRM_ECC_SG_ERR s2BIT(23) |
| 489 | #define RDA_FRM_ECC_DB_N_AERR BIT(31) | 489 | #define RDA_FRM_ECC_DB_N_AERR s2BIT(31) |
| 490 | #define RDA_SM1_ERR_ALARM BIT(38) | 490 | #define RDA_SM1_ERR_ALARM s2BIT(38) |
| 491 | #define RDA_SM0_ERR_ALARM BIT(39) | 491 | #define RDA_SM0_ERR_ALARM s2BIT(39) |
| 492 | #define RDA_MISC_ERR BIT(47) | 492 | #define RDA_MISC_ERR s2BIT(47) |
| 493 | #define RDA_PCIX_ERR BIT(55) | 493 | #define RDA_PCIX_ERR s2BIT(55) |
| 494 | #define RDA_RXD_ECC_DB_SERR BIT(63) | 494 | #define RDA_RXD_ECC_DB_SERR s2BIT(63) |
| 495 | u64 rda_err_mask; | 495 | u64 rda_err_mask; |
| 496 | u64 rda_err_alarm; | 496 | u64 rda_err_alarm; |
| 497 | 497 | ||
| 498 | u64 rc_err_reg; | 498 | u64 rc_err_reg; |
| 499 | #define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) | 499 | #define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) |
| 500 | #define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) | 500 | #define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) |
| 501 | #define RC_FTC_ECC_SG_ERR BIT(23) | 501 | #define RC_FTC_ECC_SG_ERR s2BIT(23) |
| 502 | #define RC_FTC_ECC_DB_ERR BIT(31) | 502 | #define RC_FTC_ECC_DB_ERR s2BIT(31) |
| 503 | #define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) | 503 | #define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) |
| 504 | #define RC_FTC_SM_ERR_ALARM BIT(47) | 504 | #define RC_FTC_SM_ERR_ALARM s2BIT(47) |
| 505 | #define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) | 505 | #define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) |
| 506 | u64 rc_err_mask; | 506 | u64 rc_err_mask; |
| 507 | u64 rc_err_alarm; | 507 | u64 rc_err_alarm; |
| @@ -517,18 +517,18 @@ struct XENA_dev_config { | |||
| 517 | u64 prc_pcix_err_alarm; | 517 | u64 prc_pcix_err_alarm; |
| 518 | 518 | ||
| 519 | u64 rpa_err_reg; | 519 | u64 rpa_err_reg; |
| 520 | #define RPA_ECC_SG_ERR BIT(7) | 520 | #define RPA_ECC_SG_ERR s2BIT(7) |
| 521 | #define RPA_ECC_DB_ERR BIT(15) | 521 | #define RPA_ECC_DB_ERR s2BIT(15) |
| 522 | #define RPA_FLUSH_REQUEST BIT(22) | 522 | #define RPA_FLUSH_REQUEST s2BIT(22) |
| 523 | #define RPA_SM_ERR_ALARM BIT(23) | 523 | #define RPA_SM_ERR_ALARM s2BIT(23) |
| 524 | #define RPA_CREDIT_ERR BIT(31) | 524 | #define RPA_CREDIT_ERR s2BIT(31) |
| 525 | u64 rpa_err_mask; | 525 | u64 rpa_err_mask; |
| 526 | u64 rpa_err_alarm; | 526 | u64 rpa_err_alarm; |
| 527 | 527 | ||
| 528 | u64 rti_err_reg; | 528 | u64 rti_err_reg; |
| 529 | #define RTI_ECC_SG_ERR BIT(7) | 529 | #define RTI_ECC_SG_ERR s2BIT(7) |
| 530 | #define RTI_ECC_DB_ERR BIT(15) | 530 | #define RTI_ECC_DB_ERR s2BIT(15) |
| 531 | #define RTI_SM_ERR_ALARM BIT(23) | 531 | #define RTI_SM_ERR_ALARM s2BIT(23) |
| 532 | u64 rti_err_mask; | 532 | u64 rti_err_mask; |
| 533 | u64 rti_err_alarm; | 533 | u64 rti_err_alarm; |
| 534 | 534 | ||
| @@ -568,49 +568,49 @@ struct XENA_dev_config { | |||
| 568 | #endif | 568 | #endif |
| 569 | u64 prc_rxd0_n[RX_MAX_RINGS]; | 569 | u64 prc_rxd0_n[RX_MAX_RINGS]; |
| 570 | u64 prc_ctrl_n[RX_MAX_RINGS]; | 570 | u64 prc_ctrl_n[RX_MAX_RINGS]; |
| 571 | #define PRC_CTRL_RC_ENABLED BIT(7) | 571 | #define PRC_CTRL_RC_ENABLED s2BIT(7) |
| 572 | #define PRC_CTRL_RING_MODE (BIT(14)|BIT(15)) | 572 | #define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15)) |
| 573 | #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2) | 573 | #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2) |
| 574 | #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2) | 574 | #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2) |
| 575 | #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2) | 575 | #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2) |
| 576 | #define PRC_CTRL_RING_MODE_x vBIT(3,14,2) | 576 | #define PRC_CTRL_RING_MODE_x vBIT(3,14,2) |
| 577 | #define PRC_CTRL_NO_SNOOP (BIT(22)|BIT(23)) | 577 | #define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23)) |
| 578 | #define PRC_CTRL_NO_SNOOP_DESC BIT(22) | 578 | #define PRC_CTRL_NO_SNOOP_DESC s2BIT(22) |
| 579 | #define PRC_CTRL_NO_SNOOP_BUFF BIT(23) | 579 | #define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23) |
| 580 | #define PRC_CTRL_BIMODAL_INTERRUPT BIT(37) | 580 | #define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37) |
| 581 | #define PRC_CTRL_GROUP_READS BIT(38) | 581 | #define PRC_CTRL_GROUP_READS s2BIT(38) |
| 582 | #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) | 582 | #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) |
| 583 | 583 | ||
| 584 | u64 prc_alarm_action; | 584 | u64 prc_alarm_action; |
| 585 | #define PRC_ALARM_ACTION_RR_R0_STOP BIT(3) | 585 | #define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3) |
| 586 | #define PRC_ALARM_ACTION_RW_R0_STOP BIT(7) | 586 | #define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7) |
| 587 | #define PRC_ALARM_ACTION_RR_R1_STOP BIT(11) | 587 | #define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11) |
| 588 | #define PRC_ALARM_ACTION_RW_R1_STOP BIT(15) | 588 | #define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15) |
| 589 | #define PRC_ALARM_ACTION_RR_R2_STOP BIT(19) | 589 | #define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19) |
| 590 | #define PRC_ALARM_ACTION_RW_R2_STOP BIT(23) | 590 | #define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23) |
| 591 | #define PRC_ALARM_ACTION_RR_R3_STOP BIT(27) | 591 | #define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27) |
| 592 | #define PRC_ALARM_ACTION_RW_R3_STOP BIT(31) | 592 | #define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31) |
| 593 | #define PRC_ALARM_ACTION_RR_R4_STOP BIT(35) | 593 | #define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35) |
| 594 | #define PRC_ALARM_ACTION_RW_R4_STOP BIT(39) | 594 | #define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39) |
| 595 | #define PRC_ALARM_ACTION_RR_R5_STOP BIT(43) | 595 | #define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43) |
| 596 | #define PRC_ALARM_ACTION_RW_R5_STOP BIT(47) | 596 | #define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47) |
| 597 | #define PRC_ALARM_ACTION_RR_R6_STOP BIT(51) | 597 | #define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51) |
| 598 | #define PRC_ALARM_ACTION_RW_R6_STOP BIT(55) | 598 | #define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55) |
| 599 | #define PRC_ALARM_ACTION_RR_R7_STOP BIT(59) | 599 | #define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59) |
| 600 | #define PRC_ALARM_ACTION_RW_R7_STOP BIT(63) | 600 | #define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63) |
| 601 | 601 | ||
| 602 | /* Receive traffic interrupts */ | 602 | /* Receive traffic interrupts */ |
| 603 | u64 rti_command_mem; | 603 | u64 rti_command_mem; |
| 604 | #define RTI_CMD_MEM_WE BIT(7) | 604 | #define RTI_CMD_MEM_WE s2BIT(7) |
| 605 | #define RTI_CMD_MEM_STROBE BIT(15) | 605 | #define RTI_CMD_MEM_STROBE s2BIT(15) |
| 606 | #define RTI_CMD_MEM_STROBE_NEW_CMD BIT(15) | 606 | #define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15) |
| 607 | #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED BIT(15) | 607 | #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15) |
| 608 | #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) | 608 | #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) |
| 609 | 609 | ||
| 610 | u64 rti_data1_mem; | 610 | u64 rti_data1_mem; |
| 611 | #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) | 611 | #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) |
| 612 | #define RTI_DATA1_MEM_RX_TIMER_AC_EN BIT(38) | 612 | #define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38) |
| 613 | #define RTI_DATA1_MEM_RX_TIMER_CI_EN BIT(39) | 613 | #define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39) |
| 614 | #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) | 614 | #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) |
| 615 | #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) | 615 | #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) |
| 616 | #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) | 616 | #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) |
| @@ -622,10 +622,10 @@ struct XENA_dev_config { | |||
| 622 | #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) | 622 | #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) |
| 623 | 623 | ||
| 624 | u64 rx_pa_cfg; | 624 | u64 rx_pa_cfg; |
| 625 | #define RX_PA_CFG_IGNORE_FRM_ERR BIT(1) | 625 | #define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1) |
| 626 | #define RX_PA_CFG_IGNORE_SNAP_OUI BIT(2) | 626 | #define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2) |
| 627 | #define RX_PA_CFG_IGNORE_LLC_CTRL BIT(3) | 627 | #define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3) |
| 628 | #define RX_PA_CFG_IGNORE_L2_ERR BIT(6) | 628 | #define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6) |
| 629 | 629 | ||
| 630 | u64 unused_11_1; | 630 | u64 unused_11_1; |
| 631 | 631 | ||
| @@ -641,64 +641,64 @@ struct XENA_dev_config { | |||
| 641 | /* Media Access Controller Register */ | 641 | /* Media Access Controller Register */ |
| 642 | u64 mac_int_status; | 642 | u64 mac_int_status; |
| 643 | u64 mac_int_mask; | 643 | u64 mac_int_mask; |
| 644 | #define MAC_INT_STATUS_TMAC_INT BIT(0) | 644 | #define MAC_INT_STATUS_TMAC_INT s2BIT(0) |
| 645 | #define MAC_INT_STATUS_RMAC_INT BIT(1) | 645 | #define MAC_INT_STATUS_RMAC_INT s2BIT(1) |
| 646 | 646 | ||
| 647 | u64 mac_tmac_err_reg; | 647 | u64 mac_tmac_err_reg; |
| 648 | #define TMAC_ECC_SG_ERR BIT(7) | 648 | #define TMAC_ECC_SG_ERR s2BIT(7) |
| 649 | #define TMAC_ECC_DB_ERR BIT(15) | 649 | #define TMAC_ECC_DB_ERR s2BIT(15) |
| 650 | #define TMAC_TX_BUF_OVRN BIT(23) | 650 | #define TMAC_TX_BUF_OVRN s2BIT(23) |
| 651 | #define TMAC_TX_CRI_ERR BIT(31) | 651 | #define TMAC_TX_CRI_ERR s2BIT(31) |
| 652 | #define TMAC_TX_SM_ERR BIT(39) | 652 | #define TMAC_TX_SM_ERR s2BIT(39) |
| 653 | #define TMAC_DESC_ECC_SG_ERR BIT(47) | 653 | #define TMAC_DESC_ECC_SG_ERR s2BIT(47) |
| 654 | #define TMAC_DESC_ECC_DB_ERR BIT(55) | 654 | #define TMAC_DESC_ECC_DB_ERR s2BIT(55) |
| 655 | 655 | ||
| 656 | u64 mac_tmac_err_mask; | 656 | u64 mac_tmac_err_mask; |
| 657 | u64 mac_tmac_err_alarm; | 657 | u64 mac_tmac_err_alarm; |
| 658 | 658 | ||
| 659 | u64 mac_rmac_err_reg; | 659 | u64 mac_rmac_err_reg; |
| 660 | #define RMAC_RX_BUFF_OVRN BIT(0) | 660 | #define RMAC_RX_BUFF_OVRN s2BIT(0) |
| 661 | #define RMAC_FRM_RCVD_INT BIT(1) | 661 | #define RMAC_FRM_RCVD_INT s2BIT(1) |
| 662 | #define RMAC_UNUSED_INT BIT(2) | 662 | #define RMAC_UNUSED_INT s2BIT(2) |
| 663 | #define RMAC_RTS_PNUM_ECC_SG_ERR BIT(5) | 663 | #define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5) |
| 664 | #define RMAC_RTS_DS_ECC_SG_ERR BIT(6) | 664 | #define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6) |
| 665 | #define RMAC_RD_BUF_ECC_SG_ERR BIT(7) | 665 | #define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7) |
| 666 | #define RMAC_RTH_MAP_ECC_SG_ERR BIT(8) | 666 | #define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8) |
| 667 | #define RMAC_RTH_SPDM_ECC_SG_ERR BIT(9) | 667 | #define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9) |
| 668 | #define RMAC_RTS_VID_ECC_SG_ERR BIT(10) | 668 | #define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10) |
| 669 | #define RMAC_DA_SHADOW_ECC_SG_ERR BIT(11) | 669 | #define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11) |
| 670 | #define RMAC_RTS_PNUM_ECC_DB_ERR BIT(13) | 670 | #define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13) |
| 671 | #define RMAC_RTS_DS_ECC_DB_ERR BIT(14) | 671 | #define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14) |
| 672 | #define RMAC_RD_BUF_ECC_DB_ERR BIT(15) | 672 | #define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15) |
| 673 | #define RMAC_RTH_MAP_ECC_DB_ERR BIT(16) | 673 | #define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16) |
| 674 | #define RMAC_RTH_SPDM_ECC_DB_ERR BIT(17) | 674 | #define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17) |
| 675 | #define RMAC_RTS_VID_ECC_DB_ERR BIT(18) | 675 | #define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18) |
| 676 | #define RMAC_DA_SHADOW_ECC_DB_ERR BIT(19) | 676 | #define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19) |
| 677 | #define RMAC_LINK_STATE_CHANGE_INT BIT(31) | 677 | #define RMAC_LINK_STATE_CHANGE_INT s2BIT(31) |
| 678 | #define RMAC_RX_SM_ERR BIT(39) | 678 | #define RMAC_RX_SM_ERR s2BIT(39) |
| 679 | #define RMAC_SINGLE_ECC_ERR (BIT(5) | BIT(6) | BIT(7) |\ | 679 | #define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\ |
| 680 | BIT(8) | BIT(9) | BIT(10)|\ | 680 | s2BIT(8) | s2BIT(9) | s2BIT(10)|\ |
| 681 | BIT(11)) | 681 | s2BIT(11)) |
| 682 | #define RMAC_DOUBLE_ECC_ERR (BIT(13) | BIT(14) | BIT(15) |\ | 682 | #define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\ |
| 683 | BIT(16) | BIT(17) | BIT(18)|\ | 683 | s2BIT(16) | s2BIT(17) | s2BIT(18)|\ |
| 684 | BIT(19)) | 684 | s2BIT(19)) |
| 685 | u64 mac_rmac_err_mask; | 685 | u64 mac_rmac_err_mask; |
| 686 | u64 mac_rmac_err_alarm; | 686 | u64 mac_rmac_err_alarm; |
| 687 | 687 | ||
| 688 | u8 unused14[0x100 - 0x40]; | 688 | u8 unused14[0x100 - 0x40]; |
| 689 | 689 | ||
| 690 | u64 mac_cfg; | 690 | u64 mac_cfg; |
| 691 | #define MAC_CFG_TMAC_ENABLE BIT(0) | 691 | #define MAC_CFG_TMAC_ENABLE s2BIT(0) |
| 692 | #define MAC_CFG_RMAC_ENABLE BIT(1) | 692 | #define MAC_CFG_RMAC_ENABLE s2BIT(1) |
| 693 | #define MAC_CFG_LAN_NOT_WAN BIT(2) | 693 | #define MAC_CFG_LAN_NOT_WAN s2BIT(2) |
| 694 | #define MAC_CFG_TMAC_LOOPBACK BIT(3) | 694 | #define MAC_CFG_TMAC_LOOPBACK s2BIT(3) |
| 695 | #define MAC_CFG_TMAC_APPEND_PAD BIT(4) | 695 | #define MAC_CFG_TMAC_APPEND_PAD s2BIT(4) |
| 696 | #define MAC_CFG_RMAC_STRIP_FCS BIT(5) | 696 | #define MAC_CFG_RMAC_STRIP_FCS s2BIT(5) |
| 697 | #define MAC_CFG_RMAC_STRIP_PAD BIT(6) | 697 | #define MAC_CFG_RMAC_STRIP_PAD s2BIT(6) |
| 698 | #define MAC_CFG_RMAC_PROM_ENABLE BIT(7) | 698 | #define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7) |
| 699 | #define MAC_RMAC_DISCARD_PFRM BIT(8) | 699 | #define MAC_RMAC_DISCARD_PFRM s2BIT(8) |
| 700 | #define MAC_RMAC_BCAST_ENABLE BIT(9) | 700 | #define MAC_RMAC_BCAST_ENABLE s2BIT(9) |
| 701 | #define MAC_RMAC_ALL_ADDR_ENABLE BIT(10) | 701 | #define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10) |
| 702 | #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) | 702 | #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) |
| 703 | 703 | ||
| 704 | u64 tmac_avg_ipg; | 704 | u64 tmac_avg_ipg; |
| @@ -710,14 +710,14 @@ struct XENA_dev_config { | |||
| 710 | #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14) | 710 | #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14) |
| 711 | 711 | ||
| 712 | u64 rmac_err_cfg; | 712 | u64 rmac_err_cfg; |
| 713 | #define RMAC_ERR_FCS BIT(0) | 713 | #define RMAC_ERR_FCS s2BIT(0) |
| 714 | #define RMAC_ERR_FCS_ACCEPT BIT(1) | 714 | #define RMAC_ERR_FCS_ACCEPT s2BIT(1) |
| 715 | #define RMAC_ERR_TOO_LONG BIT(1) | 715 | #define RMAC_ERR_TOO_LONG s2BIT(1) |
| 716 | #define RMAC_ERR_TOO_LONG_ACCEPT BIT(1) | 716 | #define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1) |
| 717 | #define RMAC_ERR_RUNT BIT(2) | 717 | #define RMAC_ERR_RUNT s2BIT(2) |
| 718 | #define RMAC_ERR_RUNT_ACCEPT BIT(2) | 718 | #define RMAC_ERR_RUNT_ACCEPT s2BIT(2) |
| 719 | #define RMAC_ERR_LEN_MISMATCH BIT(3) | 719 | #define RMAC_ERR_LEN_MISMATCH s2BIT(3) |
| 720 | #define RMAC_ERR_LEN_MISMATCH_ACCEPT BIT(3) | 720 | #define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3) |
| 721 | 721 | ||
| 722 | u64 rmac_cfg_key; | 722 | u64 rmac_cfg_key; |
| 723 | #define RMAC_CFG_KEY(val) vBIT(val,0,16) | 723 | #define RMAC_CFG_KEY(val) vBIT(val,0,16) |
| @@ -728,15 +728,15 @@ struct XENA_dev_config { | |||
| 728 | #define MAC_MC_ADDR_START_OFFSET 16 | 728 | #define MAC_MC_ADDR_START_OFFSET 16 |
| 729 | #define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */ | 729 | #define MAC_MC_ALL_MC_ADDR_OFFSET 63 /* enables all multicast pkts */ |
| 730 | u64 rmac_addr_cmd_mem; | 730 | u64 rmac_addr_cmd_mem; |
| 731 | #define RMAC_ADDR_CMD_MEM_WE BIT(7) | 731 | #define RMAC_ADDR_CMD_MEM_WE s2BIT(7) |
| 732 | #define RMAC_ADDR_CMD_MEM_RD 0 | 732 | #define RMAC_ADDR_CMD_MEM_RD 0 |
| 733 | #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD BIT(15) | 733 | #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15) |
| 734 | #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING BIT(15) | 734 | #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15) |
| 735 | #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) | 735 | #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) |
| 736 | 736 | ||
| 737 | u64 rmac_addr_data0_mem; | 737 | u64 rmac_addr_data0_mem; |
| 738 | #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) | 738 | #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) |
| 739 | #define RMAC_ADDR_DATA0_MEM_USER BIT(48) | 739 | #define RMAC_ADDR_DATA0_MEM_USER s2BIT(48) |
| 740 | 740 | ||
| 741 | u64 rmac_addr_data1_mem; | 741 | u64 rmac_addr_data1_mem; |
| 742 | #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) | 742 | #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) |
| @@ -753,10 +753,10 @@ struct XENA_dev_config { | |||
| 753 | u64 tmac_ipg_cfg; | 753 | u64 tmac_ipg_cfg; |
| 754 | 754 | ||
| 755 | u64 rmac_pause_cfg; | 755 | u64 rmac_pause_cfg; |
| 756 | #define RMAC_PAUSE_GEN BIT(0) | 756 | #define RMAC_PAUSE_GEN s2BIT(0) |
| 757 | #define RMAC_PAUSE_GEN_ENABLE BIT(0) | 757 | #define RMAC_PAUSE_GEN_ENABLE s2BIT(0) |
| 758 | #define RMAC_PAUSE_RX BIT(1) | 758 | #define RMAC_PAUSE_RX s2BIT(1) |
| 759 | #define RMAC_PAUSE_RX_ENABLE BIT(1) | 759 | #define RMAC_PAUSE_RX_ENABLE s2BIT(1) |
| 760 | #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) | 760 | #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) |
| 761 | #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) | 761 | #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) |
| 762 | 762 | ||
| @@ -787,29 +787,29 @@ struct XENA_dev_config { | |||
| 787 | #define MAX_DIX_MAP 4 | 787 | #define MAX_DIX_MAP 4 |
| 788 | u64 rts_dix_map_n[MAX_DIX_MAP]; | 788 | u64 rts_dix_map_n[MAX_DIX_MAP]; |
| 789 | #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) | 789 | #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) |
| 790 | #define RTS_DIX_MAP_SCW(val) BIT(val,21) | 790 | #define RTS_DIX_MAP_SCW(val) s2BIT(val,21) |
| 791 | 791 | ||
| 792 | u64 rts_q_alternates; | 792 | u64 rts_q_alternates; |
| 793 | u64 rts_default_q; | 793 | u64 rts_default_q; |
| 794 | 794 | ||
| 795 | u64 rts_ctrl; | 795 | u64 rts_ctrl; |
| 796 | #define RTS_CTRL_IGNORE_SNAP_OUI BIT(2) | 796 | #define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2) |
| 797 | #define RTS_CTRL_IGNORE_LLC_CTRL BIT(3) | 797 | #define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3) |
| 798 | 798 | ||
| 799 | u64 rts_pn_cam_ctrl; | 799 | u64 rts_pn_cam_ctrl; |
| 800 | #define RTS_PN_CAM_CTRL_WE BIT(7) | 800 | #define RTS_PN_CAM_CTRL_WE s2BIT(7) |
| 801 | #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD BIT(15) | 801 | #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15) |
| 802 | #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED BIT(15) | 802 | #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15) |
| 803 | #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) | 803 | #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) |
| 804 | u64 rts_pn_cam_data; | 804 | u64 rts_pn_cam_data; |
| 805 | #define RTS_PN_CAM_DATA_TCP_SELECT BIT(7) | 805 | #define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7) |
| 806 | #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) | 806 | #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) |
| 807 | #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) | 807 | #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) |
| 808 | 808 | ||
| 809 | u64 rts_ds_mem_ctrl; | 809 | u64 rts_ds_mem_ctrl; |
| 810 | #define RTS_DS_MEM_CTRL_WE BIT(7) | 810 | #define RTS_DS_MEM_CTRL_WE s2BIT(7) |
| 811 | #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD BIT(15) | 811 | #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15) |
| 812 | #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED BIT(15) | 812 | #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15) |
| 813 | #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) | 813 | #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) |
| 814 | u64 rts_ds_mem_data; | 814 | u64 rts_ds_mem_data; |
| 815 | #define RTS_DS_MEM_DATA(n) vBIT(n,0,8) | 815 | #define RTS_DS_MEM_DATA(n) vBIT(n,0,8) |
| @@ -823,23 +823,23 @@ struct XENA_dev_config { | |||
| 823 | 823 | ||
| 824 | /* memory controller registers */ | 824 | /* memory controller registers */ |
| 825 | u64 mc_int_status; | 825 | u64 mc_int_status; |
| 826 | #define MC_INT_STATUS_MC_INT BIT(0) | 826 | #define MC_INT_STATUS_MC_INT s2BIT(0) |
| 827 | u64 mc_int_mask; | 827 | u64 mc_int_mask; |
| 828 | #define MC_INT_MASK_MC_INT BIT(0) | 828 | #define MC_INT_MASK_MC_INT s2BIT(0) |
| 829 | 829 | ||
| 830 | u64 mc_err_reg; | 830 | u64 mc_err_reg; |
| 831 | #define MC_ERR_REG_ECC_DB_ERR_L BIT(14) | 831 | #define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14) |
| 832 | #define MC_ERR_REG_ECC_DB_ERR_U BIT(15) | 832 | #define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15) |
| 833 | #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 BIT(18) | 833 | #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18) |
| 834 | #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 BIT(20) | 834 | #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20) |
| 835 | #define MC_ERR_REG_MIRI_CRI_ERR_0 BIT(22) | 835 | #define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22) |
| 836 | #define MC_ERR_REG_MIRI_CRI_ERR_1 BIT(23) | 836 | #define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23) |
| 837 | #define MC_ERR_REG_SM_ERR BIT(31) | 837 | #define MC_ERR_REG_SM_ERR s2BIT(31) |
| 838 | #define MC_ERR_REG_ECC_ALL_SNG (BIT(2) | BIT(3) | BIT(4) | BIT(5) |\ | 838 | #define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\ |
| 839 | BIT(17) | BIT(19)) | 839 | s2BIT(17) | s2BIT(19)) |
| 840 | #define MC_ERR_REG_ECC_ALL_DBL (BIT(10) | BIT(11) | BIT(12) |\ | 840 | #define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\ |
| 841 | BIT(13) | BIT(18) | BIT(20)) | 841 | s2BIT(13) | s2BIT(18) | s2BIT(20)) |
| 842 | #define PLL_LOCK_N BIT(39) | 842 | #define PLL_LOCK_N s2BIT(39) |
| 843 | u64 mc_err_mask; | 843 | u64 mc_err_mask; |
| 844 | u64 mc_err_alarm; | 844 | u64 mc_err_alarm; |
| 845 | 845 | ||
| @@ -857,8 +857,8 @@ struct XENA_dev_config { | |||
| 857 | #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) | 857 | #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) |
| 858 | 858 | ||
| 859 | u64 mc_rldram_mrs; | 859 | u64 mc_rldram_mrs; |
| 860 | #define MC_RLDRAM_QUEUE_SIZE_ENABLE BIT(39) | 860 | #define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39) |
| 861 | #define MC_RLDRAM_MRS_ENABLE BIT(47) | 861 | #define MC_RLDRAM_MRS_ENABLE s2BIT(47) |
| 862 | 862 | ||
| 863 | u64 mc_rldram_interleave; | 863 | u64 mc_rldram_interleave; |
| 864 | 864 | ||
| @@ -871,11 +871,11 @@ struct XENA_dev_config { | |||
| 871 | u64 mc_rldram_ref_per; | 871 | u64 mc_rldram_ref_per; |
| 872 | u8 unused20[0x220 - 0x208]; | 872 | u8 unused20[0x220 - 0x208]; |
| 873 | u64 mc_rldram_test_ctrl; | 873 | u64 mc_rldram_test_ctrl; |
| 874 | #define MC_RLDRAM_TEST_MODE BIT(47) | 874 | #define MC_RLDRAM_TEST_MODE s2BIT(47) |
| 875 | #define MC_RLDRAM_TEST_WRITE BIT(7) | 875 | #define MC_RLDRAM_TEST_WRITE s2BIT(7) |
| 876 | #define MC_RLDRAM_TEST_GO BIT(15) | 876 | #define MC_RLDRAM_TEST_GO s2BIT(15) |
| 877 | #define MC_RLDRAM_TEST_DONE BIT(23) | 877 | #define MC_RLDRAM_TEST_DONE s2BIT(23) |
| 878 | #define MC_RLDRAM_TEST_PASS BIT(31) | 878 | #define MC_RLDRAM_TEST_PASS s2BIT(31) |
| 879 | 879 | ||
| 880 | u8 unused21[0x240 - 0x228]; | 880 | u8 unused21[0x240 - 0x228]; |
| 881 | u64 mc_rldram_test_add; | 881 | u64 mc_rldram_test_add; |
| @@ -888,7 +888,7 @@ struct XENA_dev_config { | |||
| 888 | 888 | ||
| 889 | u8 unused24_1[0x360 - 0x308]; | 889 | u8 unused24_1[0x360 - 0x308]; |
| 890 | u64 mc_rldram_ctrl; | 890 | u64 mc_rldram_ctrl; |
| 891 | #define MC_RLDRAM_ENABLE_ODT BIT(7) | 891 | #define MC_RLDRAM_ENABLE_ODT s2BIT(7) |
| 892 | 892 | ||
| 893 | u8 unused24_2[0x640 - 0x368]; | 893 | u8 unused24_2[0x640 - 0x368]; |
| 894 | u64 mc_rldram_ref_per_herc; | 894 | u64 mc_rldram_ref_per_herc; |
| @@ -906,24 +906,24 @@ struct XENA_dev_config { | |||
| 906 | /* XGXS control registers */ | 906 | /* XGXS control registers */ |
| 907 | 907 | ||
| 908 | u64 xgxs_int_status; | 908 | u64 xgxs_int_status; |
| 909 | #define XGXS_INT_STATUS_TXGXS BIT(0) | 909 | #define XGXS_INT_STATUS_TXGXS s2BIT(0) |
| 910 | #define XGXS_INT_STATUS_RXGXS BIT(1) | 910 | #define XGXS_INT_STATUS_RXGXS s2BIT(1) |
| 911 | u64 xgxs_int_mask; | 911 | u64 xgxs_int_mask; |
| 912 | #define XGXS_INT_MASK_TXGXS BIT(0) | 912 | #define XGXS_INT_MASK_TXGXS s2BIT(0) |
| 913 | #define XGXS_INT_MASK_RXGXS BIT(1) | 913 | #define XGXS_INT_MASK_RXGXS s2BIT(1) |
| 914 | 914 | ||
| 915 | u64 xgxs_txgxs_err_reg; | 915 | u64 xgxs_txgxs_err_reg; |
| 916 | #define TXGXS_ECC_SG_ERR BIT(7) | 916 | #define TXGXS_ECC_SG_ERR s2BIT(7) |
| 917 | #define TXGXS_ECC_DB_ERR BIT(15) | 917 | #define TXGXS_ECC_DB_ERR s2BIT(15) |
| 918 | #define TXGXS_ESTORE_UFLOW BIT(31) | 918 | #define TXGXS_ESTORE_UFLOW s2BIT(31) |
| 919 | #define TXGXS_TX_SM_ERR BIT(39) | 919 | #define TXGXS_TX_SM_ERR s2BIT(39) |
| 920 | 920 | ||
| 921 | u64 xgxs_txgxs_err_mask; | 921 | u64 xgxs_txgxs_err_mask; |
| 922 | u64 xgxs_txgxs_err_alarm; | 922 | u64 xgxs_txgxs_err_alarm; |
| 923 | 923 | ||
| 924 | u64 xgxs_rxgxs_err_reg; | 924 | u64 xgxs_rxgxs_err_reg; |
| 925 | #define RXGXS_ESTORE_OFLOW BIT(7) | 925 | #define RXGXS_ESTORE_OFLOW s2BIT(7) |
| 926 | #define RXGXS_RX_SM_ERR BIT(39) | 926 | #define RXGXS_RX_SM_ERR s2BIT(39) |
| 927 | u64 xgxs_rxgxs_err_mask; | 927 | u64 xgxs_rxgxs_err_mask; |
| 928 | u64 xgxs_rxgxs_err_alarm; | 928 | u64 xgxs_rxgxs_err_alarm; |
| 929 | 929 | ||
| @@ -942,10 +942,10 @@ struct XENA_dev_config { | |||
| 942 | #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3) | 942 | #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3) |
| 943 | #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8) | 943 | #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8) |
| 944 | #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24) | 944 | #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24) |
| 945 | #define SPI_CONTROL_SEL1 BIT(4) | 945 | #define SPI_CONTROL_SEL1 s2BIT(4) |
| 946 | #define SPI_CONTROL_REQ BIT(7) | 946 | #define SPI_CONTROL_REQ s2BIT(7) |
| 947 | #define SPI_CONTROL_NACK BIT(5) | 947 | #define SPI_CONTROL_NACK s2BIT(5) |
| 948 | #define SPI_CONTROL_DONE BIT(6) | 948 | #define SPI_CONTROL_DONE s2BIT(6) |
| 949 | u64 spi_data; | 949 | u64 spi_data; |
| 950 | #define SPI_DATA_WRITE(data,len) vBIT(data,0,len) | 950 | #define SPI_DATA_WRITE(data,len) vBIT(data,0,len) |
| 951 | }; | 951 | }; |