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authorFrancois Romieu <romieu@fr.zoreil.com>2008-07-04 18:21:15 -0400
committerFrancois Romieu <romieu@fr.zoreil.com>2008-08-17 09:53:04 -0400
commit9c14ceafa5ca7f57225a43fb0785c56ddc7f1823 (patch)
tree0c930fe3ca9110ba31b39e651e0b71a819738c0d /drivers/net/r8169.c
parent458a9f617adfb2fc5f38e7673339115c4ba3290f (diff)
r8169: use pci_find_capability for the PCI-E features
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Cc: Edward Hsu <edward_hsu@realtek.com.tw>
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c32
1 files changed, 24 insertions, 8 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 26fa6e0c6d96..ae149a930620 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -61,6 +61,7 @@ static const int multicast_filter_limit = 32;
61/* MAC address length */ 61/* MAC address length */
62#define MAC_ADDR_LEN 6 62#define MAC_ADDR_LEN 6
63 63
64#define MAX_READ_REQUEST_SHIFT 12
64#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
65#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
@@ -412,6 +413,7 @@ struct rtl8169_private {
412 void (*hw_start)(struct net_device *); 413 void (*hw_start)(struct net_device *);
413 unsigned int (*phy_reset_pending)(void __iomem *); 414 unsigned int (*phy_reset_pending)(void __iomem *);
414 unsigned int (*link_ok)(void __iomem *); 415 unsigned int (*link_ok)(void __iomem *);
416 int pcie_cap;
415 struct delayed_work task; 417 struct delayed_work task;
416 unsigned features; 418 unsigned features;
417 419
@@ -1663,6 +1665,10 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1663 goto err_out_free_res_4; 1665 goto err_out_free_res_4;
1664 } 1666 }
1665 1667
1668 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1669 if (!tp->pcie_cap && netif_msg_probe(tp))
1670 dev_info(&pdev->dev, "no PCI Express capability\n");
1671
1666 /* Unneeded ? Don't mess with Mrs. Murphy. */ 1672 /* Unneeded ? Don't mess with Mrs. Murphy. */
1667 rtl8169_irq_mask_and_ack(ioaddr); 1673 rtl8169_irq_mask_and_ack(ioaddr);
1668 1674
@@ -2054,13 +2060,19 @@ static void rtl_hw_start_8169(struct net_device *dev)
2054 RTL_W16(IntrMask, tp->intr_event); 2060 RTL_W16(IntrMask, tp->intr_event);
2055} 2061}
2056 2062
2057static void rtl_tx_performance_tweak(struct pci_dev *pdev, u8 force) 2063static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2058{ 2064{
2059 u8 ctl; 2065 struct net_device *dev = pci_get_drvdata(pdev);
2066 struct rtl8169_private *tp = netdev_priv(dev);
2067 int cap = tp->pcie_cap;
2068
2069 if (cap) {
2070 u16 ctl;
2060 2071
2061 pci_read_config_byte(pdev, 0x69, &ctl); 2072 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2062 ctl = (ctl & ~0x70) | force; 2073 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2063 pci_write_config_byte(pdev, 0x69, ctl); 2074 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2075 }
2064} 2076}
2065 2077
2066static void rtl_hw_start_8168(struct net_device *dev) 2078static void rtl_hw_start_8168(struct net_device *dev)
@@ -2081,7 +2093,7 @@ static void rtl_hw_start_8168(struct net_device *dev)
2081 2093
2082 RTL_W16(CPlusCmd, tp->cp_cmd); 2094 RTL_W16(CPlusCmd, tp->cp_cmd);
2083 2095
2084 rtl_tx_performance_tweak(pdev, 0x50); 2096 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2085 2097
2086 RTL_W16(IntrMitigate, 0x5151); 2098 RTL_W16(IntrMitigate, 0x5151);
2087 2099
@@ -2116,8 +2128,12 @@ static void rtl_hw_start_8101(struct net_device *dev)
2116 2128
2117 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || 2129 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2118 (tp->mac_version == RTL_GIGA_MAC_VER_16)) { 2130 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2119 pci_write_config_word(pdev, 0x68, 0x00); 2131 int cap = tp->pcie_cap;
2120 pci_write_config_word(pdev, 0x69, 0x08); 2132
2133 if (cap) {
2134 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2135 PCI_EXP_DEVCTL_NOSNOOP_EN);
2136 }
2121 } 2137 }
2122 2138
2123 RTL_W8(Cfg9346, Cfg9346_Unlock); 2139 RTL_W8(Cfg9346, Cfg9346_Unlock);