diff options
author | Francois Romieu <romieu@fr.zoreil.com> | 2008-06-29 06:24:30 -0400 |
---|---|---|
committer | Francois Romieu <romieu@fr.zoreil.com> | 2008-10-10 17:08:55 -0400 |
commit | ef3386f00fcd18a40343047329ec7ed2eb98bbe8 (patch) | |
tree | b2eab47d7a462267270a376f4bf41280677f9fb3 /drivers/net/r8169.c | |
parent | 6fb07058d2b6c748c308e4ee453035433d34ca93 (diff) |
r8169: add a new 8168cp flavor
Taken from Realtek's 8.006.00 r8168 driver.
I have left some bits related to jumbo frame aside for now.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Cc: Edward Hsu <edward_hsu@realtek.com.tw>
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r-- | drivers/net/r8169.c | 49 |
1 files changed, 43 insertions, 6 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 9a0d4e631afe..775dc84336bb 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c | |||
@@ -111,7 +111,8 @@ enum mac_version { | |||
111 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | 111 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C |
112 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C | 112 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
113 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C | 113 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
114 | RTL_GIGA_MAC_VER_22 = 0x16 // 8168C | 114 | RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
115 | RTL_GIGA_MAC_VER_23 = 0x17 // 8168CP | ||
115 | }; | 116 | }; |
116 | 117 | ||
117 | #define _R(NAME,MAC,MASK) \ | 118 | #define _R(NAME,MAC,MASK) \ |
@@ -143,7 +144,8 @@ static const struct { | |||
143 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | 144 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E |
144 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E | 145 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
145 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E | 146 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
146 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880) // PCI-E | 147 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
148 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880) // PCI-E | ||
147 | }; | 149 | }; |
148 | #undef _R | 150 | #undef _R |
149 | 151 | ||
@@ -1221,6 +1223,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp, | |||
1221 | int mac_version; | 1223 | int mac_version; |
1222 | } mac_info[] = { | 1224 | } mac_info[] = { |
1223 | /* 8168B family. */ | 1225 | /* 8168B family. */ |
1226 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, | ||
1224 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, | 1227 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
1225 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, | 1228 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1226 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | 1229 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, |
@@ -1380,7 +1383,7 @@ static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) | |||
1380 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | 1383 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1381 | } | 1384 | } |
1382 | 1385 | ||
1383 | static void rtl8168cp_hw_phy_config(void __iomem *ioaddr) | 1386 | static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) |
1384 | { | 1387 | { |
1385 | struct phy_reg phy_reg_init[] = { | 1388 | struct phy_reg phy_reg_init[] = { |
1386 | { 0x1f, 0x0000 }, | 1389 | { 0x1f, 0x0000 }, |
@@ -1393,6 +1396,21 @@ static void rtl8168cp_hw_phy_config(void __iomem *ioaddr) | |||
1393 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | 1396 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1394 | } | 1397 | } |
1395 | 1398 | ||
1399 | static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) | ||
1400 | { | ||
1401 | struct phy_reg phy_reg_init[] = { | ||
1402 | { 0x1f, 0x0001 }, | ||
1403 | { 0x1d, 0x3d98 }, | ||
1404 | { 0x1f, 0x0000 } | ||
1405 | }; | ||
1406 | |||
1407 | mdio_write(ioaddr, 0x1f, 0x0000); | ||
1408 | mdio_patch(ioaddr, 0x14, 1 << 5); | ||
1409 | mdio_patch(ioaddr, 0x0d, 1 << 5); | ||
1410 | |||
1411 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | ||
1412 | } | ||
1413 | |||
1396 | static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) | 1414 | static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) |
1397 | { | 1415 | { |
1398 | struct phy_reg phy_reg_init[] = { | 1416 | struct phy_reg phy_reg_init[] = { |
@@ -1525,7 +1543,7 @@ static void rtl_hw_phy_config(struct net_device *dev) | |||
1525 | rtl8168bef_hw_phy_config(ioaddr); | 1543 | rtl8168bef_hw_phy_config(ioaddr); |
1526 | break; | 1544 | break; |
1527 | case RTL_GIGA_MAC_VER_18: | 1545 | case RTL_GIGA_MAC_VER_18: |
1528 | rtl8168cp_hw_phy_config(ioaddr); | 1546 | rtl8168cp_1_hw_phy_config(ioaddr); |
1529 | break; | 1547 | break; |
1530 | case RTL_GIGA_MAC_VER_19: | 1548 | case RTL_GIGA_MAC_VER_19: |
1531 | rtl8168c_1_hw_phy_config(ioaddr); | 1549 | rtl8168c_1_hw_phy_config(ioaddr); |
@@ -1539,6 +1557,10 @@ static void rtl_hw_phy_config(struct net_device *dev) | |||
1539 | case RTL_GIGA_MAC_VER_22: | 1557 | case RTL_GIGA_MAC_VER_22: |
1540 | rtl8168c_4_hw_phy_config(ioaddr); | 1558 | rtl8168c_4_hw_phy_config(ioaddr); |
1541 | break; | 1559 | break; |
1560 | case RTL_GIGA_MAC_VER_23: | ||
1561 | rtl8168cp_2_hw_phy_config(ioaddr); | ||
1562 | break; | ||
1563 | |||
1542 | default: | 1564 | default: |
1543 | break; | 1565 | break; |
1544 | } | 1566 | } |
@@ -2481,7 +2503,7 @@ static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |||
2481 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | 2503 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); |
2482 | } | 2504 | } |
2483 | 2505 | ||
2484 | static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | 2506 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
2485 | { | 2507 | { |
2486 | static struct ephy_info e_info_8168cp[] = { | 2508 | static struct ephy_info e_info_8168cp[] = { |
2487 | { 0x01, 0, 0x0001 }, | 2509 | { 0x01, 0, 0x0001 }, |
@@ -2498,6 +2520,17 @@ static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |||
2498 | __rtl_hw_start_8168cp(ioaddr, pdev); | 2520 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2499 | } | 2521 | } |
2500 | 2522 | ||
2523 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) | ||
2524 | { | ||
2525 | rtl_csi_access_enable(ioaddr); | ||
2526 | |||
2527 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | ||
2528 | |||
2529 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | ||
2530 | |||
2531 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | ||
2532 | } | ||
2533 | |||
2501 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) | 2534 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
2502 | { | 2535 | { |
2503 | static struct ephy_info e_info_8168c_1[] = { | 2536 | static struct ephy_info e_info_8168c_1[] = { |
@@ -2585,7 +2618,7 @@ static void rtl_hw_start_8168(struct net_device *dev) | |||
2585 | break; | 2618 | break; |
2586 | 2619 | ||
2587 | case RTL_GIGA_MAC_VER_18: | 2620 | case RTL_GIGA_MAC_VER_18: |
2588 | rtl_hw_start_8168cp(ioaddr, pdev); | 2621 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
2589 | break; | 2622 | break; |
2590 | 2623 | ||
2591 | case RTL_GIGA_MAC_VER_19: | 2624 | case RTL_GIGA_MAC_VER_19: |
@@ -2604,6 +2637,10 @@ static void rtl_hw_start_8168(struct net_device *dev) | |||
2604 | rtl_hw_start_8168c_4(ioaddr, pdev); | 2637 | rtl_hw_start_8168c_4(ioaddr, pdev); |
2605 | break; | 2638 | break; |
2606 | 2639 | ||
2640 | case RTL_GIGA_MAC_VER_23: | ||
2641 | rtl_hw_start_8168cp_2(ioaddr, pdev); | ||
2642 | break; | ||
2643 | |||
2607 | default: | 2644 | default: |
2608 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | 2645 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", |
2609 | dev->name, tp->mac_version); | 2646 | dev->name, tp->mac_version); |