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authorMarcus Sundberg <marcus@ingate.com>2008-07-10 15:28:08 -0400
committerFrancois Romieu <romieu@fr.zoreil.com>2008-07-20 13:49:30 -0400
commit77332894c21165404496c56763d7df6c15c4bb09 (patch)
tree84f2a9557d8680085fc5120e0f581469eafe1fa6 /drivers/net/r8169.c
parentf887cce8de019bb32917789379af89ae4c0294ee (diff)
r8169: avoid thrashing PCI conf space above RTL_GIGA_MAC_VER_06
The magic write to register 0x82 will often cause PCI config space on my 8168 (PCI ID 10ec:8168, revision 2. mounted in an LG P300 laptop) to be filled with ones during driver load, and thus breaking NIC operation until reboot. If it does not happen on first driver load it can easily be reproduced by unloading and loading the driver a few times. The magic write was added long ago by this commit: Author: François Romieu <romieu@fr.zoreil.com> Date: Sat Jan 10 06:00:46 2004 -0500 [netdrvr r8169] Merge of changes done by Realtek to rtl8169_init_one(): - phy capability settings allows lower or equal capability as suggested in Realtek's changes; - I/O voodoo; - no need to s/mdio_write/RTL8169_WRITE_GMII_REG/; - s/rtl8169_hw_PHY_config/rtl8169_hw_phy_config/; - rtl8169_hw_phy_config(): ad-hoc struct "phy_magic" to limit duplication of code (yep, the u16 -> int conversions should work as expected); - variable renames and whitepace changes ignored. As the 8168 wasn't supported by that version this patch simply removes the bogus write from mac versions <= RTL_GIGA_MAC_VER_06. [The change above makes sense for the 8101/8102 too -- Ueimor] Signed-off-by: Marcus Sundberg <marcus@ingate.com> Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 2a5486ffe5c4..a3e3895e5032 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -1418,8 +1418,10 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1418 1418
1419 rtl_hw_phy_config(dev); 1419 rtl_hw_phy_config(dev);
1420 1420
1421 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); 1421 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1422 RTL_W8(0x82, 0x01); 1422 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1423 RTL_W8(0x82, 0x01);
1424 }
1423 1425
1424 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 1426 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1425 1427