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authorFrancois Romieu <romieu@fr.zoreil.com>2006-11-01 18:10:16 -0500
committerFrancois Romieu <romieu@electric-eye.fr.zoreil.com>2006-12-03 18:42:31 -0500
commit9cb427b6ff0b3e235c518acf5c1fcbbfc95f0ae2 (patch)
tree168c69aa173ca62da045f7a1e9a0a9b102f5a2d3 /drivers/net/r8169.c
parentaae343d493df965ac3abec1bd97cccfe44a7d920 (diff)
r8169: more magic during initialization of the hardware
Mostly taken from Realtek's driver. It's a bit yucky but the original is even worse. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Signed-off-by: Darren Salt <linux@youmustbejoking.demon.co.uk>
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c58
1 files changed, 44 insertions, 14 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 45d3ca431957..c8fa9b1b2290 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -1815,12 +1815,25 @@ static void rtl8169_hw_reset(void __iomem *ioaddr)
1815 RTL_R8(ChipCmd); 1815 RTL_R8(ChipCmd);
1816} 1816}
1817 1817
1818static void 1818static void rtl8169_set_rx_tx_config_registers(struct rtl8169_private *tp)
1819rtl8169_hw_start(struct net_device *dev) 1819{
1820 void __iomem *ioaddr = tp->mmio_addr;
1821 u32 cfg = rtl8169_rx_config;
1822
1823 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1824 RTL_W32(RxConfig, cfg);
1825
1826 /* Set DMA burst size and Interframe Gap Time */
1827 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1828 (InterFrameGap << TxInterFrameGapShift));
1829}
1830
1831static void rtl8169_hw_start(struct net_device *dev)
1820{ 1832{
1821 struct rtl8169_private *tp = netdev_priv(dev); 1833 struct rtl8169_private *tp = netdev_priv(dev);
1822 void __iomem *ioaddr = tp->mmio_addr; 1834 void __iomem *ioaddr = tp->mmio_addr;
1823 struct pci_dev *pdev = tp->pci_dev; 1835 struct pci_dev *pdev = tp->pci_dev;
1836 u16 cmd;
1824 u32 i; 1837 u32 i;
1825 1838
1826 /* Soft reset the chip. */ 1839 /* Soft reset the chip. */
@@ -1833,6 +1846,11 @@ rtl8169_hw_start(struct net_device *dev)
1833 msleep_interruptible(1); 1846 msleep_interruptible(1);
1834 } 1847 }
1835 1848
1849 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1850 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1851 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1852 }
1853
1836 if (tp->mac_version == RTL_GIGA_MAC_VER_13) { 1854 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1837 pci_write_config_word(pdev, 0x68, 0x00); 1855 pci_write_config_word(pdev, 0x68, 0x00);
1838 pci_write_config_word(pdev, 0x69, 0x08); 1856 pci_write_config_word(pdev, 0x69, 0x08);
@@ -1840,8 +1858,6 @@ rtl8169_hw_start(struct net_device *dev)
1840 1858
1841 /* Undocumented stuff. */ 1859 /* Undocumented stuff. */
1842 if (tp->mac_version == RTL_GIGA_MAC_VER_05) { 1860 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1843 u16 cmd;
1844
1845 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */ 1861 /* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */
1846 if ((RTL_R8(Config2) & 0x07) & 0x01) 1862 if ((RTL_R8(Config2) & 0x07) & 0x01)
1847 RTL_W32(0x7c, 0x0007ffff); 1863 RTL_W32(0x7c, 0x0007ffff);
@@ -1853,23 +1869,29 @@ rtl8169_hw_start(struct net_device *dev)
1853 pci_write_config_word(pdev, PCI_COMMAND, cmd); 1869 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1854 } 1870 }
1855 1871
1856
1857 RTL_W8(Cfg9346, Cfg9346_Unlock); 1872 RTL_W8(Cfg9346, Cfg9346_Unlock);
1873 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1874 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1875 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1876 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1877 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1878
1858 RTL_W8(EarlyTxThres, EarlyTxThld); 1879 RTL_W8(EarlyTxThres, EarlyTxThld);
1859 1880
1860 /* Low hurts. Let's disable the filtering. */ 1881 /* Low hurts. Let's disable the filtering. */
1861 RTL_W16(RxMaxSize, 16383); 1882 RTL_W16(RxMaxSize, 16383);
1862 1883
1863 /* Set Rx Config register */ 1884 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1864 i = rtl8169_rx_config | 1885 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1865 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); 1886 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1866 RTL_W32(RxConfig, i); 1887 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1888 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1889 rtl8169_set_rx_tx_config_registers(tp);
1867 1890
1868 /* Set DMA burst size and Interframe Gap Time */ 1891 cmd = RTL_R16(CPlusCmd);
1869 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 1892 RTL_W16(CPlusCmd, cmd);
1870 (InterFrameGap << TxInterFrameGapShift));
1871 1893
1872 tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW; 1894 tp->cp_cmd |= cmd | PCIMulRW;
1873 1895
1874 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || 1896 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1875 (tp->mac_version == RTL_GIGA_MAC_VER_03)) { 1897 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
@@ -1895,7 +1917,15 @@ rtl8169_hw_start(struct net_device *dev)
1895 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK)); 1917 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1896 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); 1918 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1897 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); 1919 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1898 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 1920
1921 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1922 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1923 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1924 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1925 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1926 rtl8169_set_rx_tx_config_registers(tp);
1927 }
1928
1899 RTL_W8(Cfg9346, Cfg9346_Lock); 1929 RTL_W8(Cfg9346, Cfg9346_Lock);
1900 1930
1901 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 1931 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */