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authorHayes Wang <hayeswang@realtek.com>2011-02-22 04:26:19 -0500
committerFrancois Romieu <romieu@fr.zoreil.com>2011-02-23 17:31:03 -0500
commitd24e9aafe5d5dfdf6d114b29e67f8afd5fae5ef0 (patch)
tree437911c88d0094e4334eb7f4ff913eac739a29ae /drivers/net/r8169.c
parentfac5b3caa1f5bc07ecfb4f5ce98f8112638dc8fb (diff)
r8169: correct settings of rtl8102e.
Adjust and remove certain settings of RTL8102E which are for previous chips. Signed-off-by: Hayes Wang <hayeswang@realtek.com> Acked-off-by: Francois Romieu <romieu@fr.zoreil.com>
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c20
1 files changed, 6 insertions, 14 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 550c86589649..336ba9480e18 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -3043,7 +3043,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3043 goto err_out_mwi_2; 3043 goto err_out_mwi_2;
3044 } 3044 }
3045 3045
3046 tp->cp_cmd = PCIMulRW | RxChkSum; 3046 tp->cp_cmd = RxChkSum;
3047 3047
3048 if ((sizeof(dma_addr_t) > 4) && 3048 if ((sizeof(dma_addr_t) > 4) &&
3049 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { 3049 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
@@ -3848,8 +3848,7 @@ static void rtl_hw_start_8168(struct net_device *dev)
3848 Cxpl_dbg_sel | \ 3848 Cxpl_dbg_sel | \
3849 ASF | \ 3849 ASF | \
3850 PktCntrDisable | \ 3850 PktCntrDisable | \
3851 PCIDAC | \ 3851 Mac_dbgo_sel)
3852 PCIMulRW)
3853 3852
3854static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) 3853static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3855{ 3854{
@@ -3879,8 +3878,6 @@ static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3879 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3878 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3880 RTL_W8(Config1, cfg1 & ~LEDS0); 3879 RTL_W8(Config1, cfg1 & ~LEDS0);
3881 3880
3882 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3883
3884 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); 3881 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3885} 3882}
3886 3883
@@ -3892,8 +3889,6 @@ static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3892 3889
3893 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); 3890 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3894 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); 3891 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3895
3896 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3897} 3892}
3898 3893
3899static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) 3894static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
@@ -3919,6 +3914,8 @@ static void rtl_hw_start_8101(struct net_device *dev)
3919 } 3914 }
3920 } 3915 }
3921 3916
3917 RTL_W8(Cfg9346, Cfg9346_Unlock);
3918
3922 switch (tp->mac_version) { 3919 switch (tp->mac_version) {
3923 case RTL_GIGA_MAC_VER_07: 3920 case RTL_GIGA_MAC_VER_07:
3924 rtl_hw_start_8102e_1(ioaddr, pdev); 3921 rtl_hw_start_8102e_1(ioaddr, pdev);
@@ -3933,14 +3930,13 @@ static void rtl_hw_start_8101(struct net_device *dev)
3933 break; 3930 break;
3934 } 3931 }
3935 3932
3936 RTL_W8(Cfg9346, Cfg9346_Unlock); 3933 RTL_W8(Cfg9346, Cfg9346_Lock);
3937 3934
3938 RTL_W8(MaxTxPacketSize, TxPacketMax); 3935 RTL_W8(MaxTxPacketSize, TxPacketMax);
3939 3936
3940 rtl_set_rx_max_size(ioaddr, rx_buf_sz); 3937 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3941 3938
3942 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; 3939 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
3943
3944 RTL_W16(CPlusCmd, tp->cp_cmd); 3940 RTL_W16(CPlusCmd, tp->cp_cmd);
3945 3941
3946 RTL_W16(IntrMitigate, 0x0000); 3942 RTL_W16(IntrMitigate, 0x0000);
@@ -3950,14 +3946,10 @@ static void rtl_hw_start_8101(struct net_device *dev)
3950 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 3946 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3951 rtl_set_rx_tx_config_registers(tp); 3947 rtl_set_rx_tx_config_registers(tp);
3952 3948
3953 RTL_W8(Cfg9346, Cfg9346_Lock);
3954
3955 RTL_R8(IntrMask); 3949 RTL_R8(IntrMask);
3956 3950
3957 rtl_set_rx_mode(dev); 3951 rtl_set_rx_mode(dev);
3958 3952
3959 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3960
3961 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); 3953 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3962 3954
3963 RTL_W16(IntrMask, tp->intr_event); 3955 RTL_W16(IntrMask, tp->intr_event);