diff options
author | Masakazu Mokuno <mokuno@sm.sony.co.jp> | 2008-02-07 05:58:08 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2008-02-11 10:29:45 -0500 |
commit | 59e973277cf942a1eac6d83802d6c9d1f397566b (patch) | |
tree | 7762b444c7721edd3240c3ec66d60ab07e72bec1 /drivers/net/ps3_gelic_net.h | |
parent | 100e1d891902e432951e88bffba0dc49005a216c (diff) |
PS3: gelic: code cleanup
Code cleanup:
- Use appropriate prefixes for names instead of fixed 'gelic_net'
so that objects of the functions, variables and constants can be estimated.
- Remove definitions for IPSec offload to the gelic hardware. This
functionality is never supported on PS3.
- Group constants with enum.
- Use bitwise constants for interrupt status, instead of bit numbers to
eliminate shift operations.
- Style fixes.
Signed-off-by: Masakazu Mokuno <mokuno@sm.sony.co.jp>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/ps3_gelic_net.h')
-rw-r--r-- | drivers/net/ps3_gelic_net.h | 285 |
1 files changed, 162 insertions, 123 deletions
diff --git a/drivers/net/ps3_gelic_net.h b/drivers/net/ps3_gelic_net.h index 80b0a3db7479..49695a5c0df6 100644 --- a/drivers/net/ps3_gelic_net.h +++ b/drivers/net/ps3_gelic_net.h | |||
@@ -43,131 +43,170 @@ | |||
43 | #define GELIC_NET_VLAN_MAX 4 | 43 | #define GELIC_NET_VLAN_MAX 4 |
44 | #define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */ | 44 | #define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */ |
45 | 45 | ||
46 | enum gelic_net_int0_status { | 46 | /* virtual interrupt status register bits */ |
47 | GELIC_NET_GDTDCEINT = 24, | 47 | /* INT1 */ |
48 | GELIC_NET_GRFANMINT = 28, | 48 | #define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L |
49 | }; | 49 | #define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L |
50 | #define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L | ||
51 | #define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L | ||
52 | #define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L | ||
53 | #define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L | ||
54 | #define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L | ||
55 | #define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L | ||
56 | #define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L | ||
57 | #define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L | ||
58 | #define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L | ||
59 | #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L | ||
60 | #define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L | ||
61 | /* INT 0 */ | ||
62 | #define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L | ||
63 | #define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L | ||
64 | #define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L | ||
65 | #define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L | ||
66 | #define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L | ||
67 | #define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L | ||
68 | #define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L | ||
69 | |||
70 | /* initial interrupt mask */ | ||
71 | #define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END | ||
72 | |||
73 | #define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \ | ||
74 | GELIC_CARD_NUMBER_OF_RX_FRAME) | ||
50 | 75 | ||
51 | /* GHIINT1STS bits */ | 76 | /* RX descriptor data_status bits */ |
52 | enum gelic_net_int1_status { | 77 | enum gelic_descr_rx_status { |
53 | GELIC_NET_GDADCEINT = 14, | 78 | GELIC_DESCR_RXDMADU = 0x80000000, /* destination MAC addr unknown */ |
79 | GELIC_DESCR_RXLSTFBF = 0x40000000, /* last frame buffer */ | ||
80 | GELIC_DESCR_RXIPCHK = 0x20000000, /* IP checksum performed */ | ||
81 | GELIC_DESCR_RXTCPCHK = 0x10000000, /* TCP/UDP checksup performed */ | ||
82 | GELIC_DESCR_RXWTPKT = 0x00C00000, /* | ||
83 | * wakeup trigger packet | ||
84 | * 01: Magic Packet (TM) | ||
85 | * 10: ARP packet | ||
86 | * 11: Multicast MAC addr | ||
87 | */ | ||
88 | GELIC_DESCR_RXVLNPKT = 0x00200000, /* VLAN packet */ | ||
89 | /* bit 20..16 reserved */ | ||
90 | GELIC_DESCR_RXRRECNUM = 0x0000ff00, /* reception receipt number */ | ||
91 | /* bit 7..0 reserved */ | ||
54 | }; | 92 | }; |
55 | 93 | ||
56 | /* interrupt mask */ | 94 | #define GELIC_DESCR_DATA_STATUS_CHK_MASK \ |
57 | #define GELIC_NET_TXINT (1L << (GELIC_NET_GDTDCEINT + 32)) | 95 | (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK) |
58 | 96 | ||
59 | #define GELIC_NET_RXINT0 (1L << (GELIC_NET_GRFANMINT + 32)) | 97 | /* TX descriptor data_status bits */ |
60 | #define GELIC_NET_RXINT1 (1L << GELIC_NET_GDADCEINT) | 98 | enum gelic_descr_tx_status { |
61 | #define GELIC_NET_RXINT (GELIC_NET_RXINT0 | GELIC_NET_RXINT1) | 99 | GELIC_DESCR_TX_TAIL = 0x00000001, /* gelic treated this |
100 | * descriptor was end of | ||
101 | * a tx frame | ||
102 | */ | ||
103 | }; | ||
62 | 104 | ||
63 | /* RX descriptor data_status bits */ | 105 | /* RX descriptor data error bits */ |
64 | #define GELIC_NET_RXDMADU 0x80000000 /* destination MAC addr unknown */ | 106 | enum gelic_descr_rx_error { |
65 | #define GELIC_NET_RXLSTFBF 0x40000000 /* last frame buffer */ | 107 | /* bit 31 reserved */ |
66 | #define GELIC_NET_RXIPCHK 0x20000000 /* IP checksum performed */ | 108 | GELIC_DESCR_RXALNERR = 0x40000000, /* alignement error 10/100M */ |
67 | #define GELIC_NET_RXTCPCHK 0x10000000 /* TCP/UDP checksup performed */ | 109 | GELIC_DESCR_RXOVERERR = 0x20000000, /* oversize error */ |
68 | #define GELIC_NET_RXIPSPKT 0x08000000 /* IPsec packet */ | 110 | GELIC_DESCR_RXRNTERR = 0x10000000, /* Runt error */ |
69 | #define GELIC_NET_RXIPSAHPRT 0x04000000 /* IPsec AH protocol performed */ | 111 | GELIC_DESCR_RXIPCHKERR = 0x08000000, /* IP checksum error */ |
70 | #define GELIC_NET_RXIPSESPPRT 0x02000000 /* IPsec ESP protocol performed */ | 112 | GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum error */ |
71 | #define GELIC_NET_RXSESPAH 0x01000000 /* | 113 | GELIC_DESCR_RXDRPPKT = 0x00100000, /* drop packet */ |
72 | * IPsec ESP protocol auth | 114 | GELIC_DESCR_RXIPFMTERR = 0x00080000, /* IP packet format error */ |
73 | * performed | 115 | /* bit 18 reserved */ |
74 | */ | 116 | GELIC_DESCR_RXDATAERR = 0x00020000, /* IP packet format error */ |
75 | 117 | GELIC_DESCR_RXCALERR = 0x00010000, /* cariier extension length | |
76 | #define GELIC_NET_RXWTPKT 0x00C00000 /* | 118 | * error */ |
77 | * wakeup trigger packet | 119 | GELIC_DESCR_RXCREXERR = 0x00008000, /* carrier extention error */ |
78 | * 01: Magic Packet (TM) | 120 | GELIC_DESCR_RXMLTCST = 0x00004000, /* multicast address frame */ |
79 | * 10: ARP packet | 121 | /* bit 13..0 reserved */ |
80 | * 11: Multicast MAC addr | 122 | }; |
81 | */ | 123 | #define GELIC_DESCR_DATA_ERROR_CHK_MASK \ |
82 | #define GELIC_NET_RXVLNPKT 0x00200000 /* VLAN packet */ | 124 | (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR) |
83 | /* bit 20..16 reserved */ | 125 | |
84 | #define GELIC_NET_RXRRECNUM 0x0000ff00 /* reception receipt number */ | 126 | /* DMA command and status (RX and TX)*/ |
85 | #define GELIC_NET_RXRRECNUM_SHIFT 8 | 127 | enum gelic_descr_dma_status { |
86 | /* bit 7..0 reserved */ | 128 | GELIC_DESCR_DMA_COMPLETE = 0x00000000, /* used in tx */ |
87 | 129 | GELIC_DESCR_DMA_BUFFER_FULL = 0x00000000, /* used in rx */ | |
88 | #define GELIC_NET_TXDESC_TAIL 0 | 130 | GELIC_DESCR_DMA_RESPONSE_ERROR = 0x10000000, /* used in rx, tx */ |
89 | #define GELIC_NET_DATA_STATUS_CHK_MASK (GELIC_NET_RXIPCHK | GELIC_NET_RXTCPCHK) | 131 | GELIC_DESCR_DMA_PROTECTION_ERROR = 0x20000000, /* used in rx, tx */ |
90 | 132 | GELIC_DESCR_DMA_FRAME_END = 0x40000000, /* used in rx */ | |
91 | /* RX descriptor data_error bits */ | 133 | GELIC_DESCR_DMA_FORCE_END = 0x50000000, /* used in rx, tx */ |
92 | /* bit 31 reserved */ | 134 | GELIC_DESCR_DMA_CARDOWNED = 0xa0000000, /* used in rx, tx */ |
93 | #define GELIC_NET_RXALNERR 0x40000000 /* alignement error 10/100M */ | 135 | GELIC_DESCR_DMA_NOT_IN_USE = 0xb0000000, /* any other value */ |
94 | #define GELIC_NET_RXOVERERR 0x20000000 /* oversize error */ | 136 | }; |
95 | #define GELIC_NET_RXRNTERR 0x10000000 /* Runt error */ | ||
96 | #define GELIC_NET_RXIPCHKERR 0x08000000 /* IP checksum error */ | ||
97 | #define GELIC_NET_RXTCPCHKERR 0x04000000 /* TCP/UDP checksum error */ | ||
98 | #define GELIC_NET_RXUMCHSP 0x02000000 /* unmatched sp on sp */ | ||
99 | #define GELIC_NET_RXUMCHSPI 0x01000000 /* unmatched SPI on SAD */ | ||
100 | #define GELIC_NET_RXUMCHSAD 0x00800000 /* unmatched SAD */ | ||
101 | #define GELIC_NET_RXIPSAHERR 0x00400000 /* auth error on AH protocol | ||
102 | * processing */ | ||
103 | #define GELIC_NET_RXIPSESPAHERR 0x00200000 /* auth error on ESP protocol | ||
104 | * processing */ | ||
105 | #define GELIC_NET_RXDRPPKT 0x00100000 /* drop packet */ | ||
106 | #define GELIC_NET_RXIPFMTERR 0x00080000 /* IP packet format error */ | ||
107 | /* bit 18 reserved */ | ||
108 | #define GELIC_NET_RXDATAERR 0x00020000 /* IP packet format error */ | ||
109 | #define GELIC_NET_RXCALERR 0x00010000 /* cariier extension length | ||
110 | * error */ | ||
111 | #define GELIC_NET_RXCREXERR 0x00008000 /* carrier extention error */ | ||
112 | #define GELIC_NET_RXMLTCST 0x00004000 /* multicast address frame */ | ||
113 | /* bit 13..0 reserved */ | ||
114 | #define GELIC_NET_DATA_ERROR_CHK_MASK \ | ||
115 | (GELIC_NET_RXIPCHKERR | GELIC_NET_RXTCPCHKERR) | ||
116 | 137 | ||
138 | #define GELIC_DESCR_DMA_STAT_MASK (0xf0000000) | ||
117 | 139 | ||
118 | /* tx descriptor command and status */ | 140 | /* tx descriptor command and status */ |
119 | #define GELIC_NET_DMAC_CMDSTAT_NOCS 0xa0080000 /* middle of frame */ | 141 | enum gelic_descr_tx_dma_status { |
120 | #define GELIC_NET_DMAC_CMDSTAT_TCPCS 0xa00a0000 | 142 | /* [19] */ |
121 | #define GELIC_NET_DMAC_CMDSTAT_UDPCS 0xa00b0000 | 143 | GELIC_DESCR_TX_DMA_IKE = 0x00080000, /* IPSEC off */ |
122 | #define GELIC_NET_DMAC_CMDSTAT_END_FRAME 0x00040000 /* end of frame */ | 144 | /* [18] */ |
123 | 145 | GELIC_DESCR_TX_DMA_FRAME_TAIL = 0x00040000, /* last descriptor of | |
124 | #define GELIC_NET_DMAC_CMDSTAT_RXDCEIS 0x00000002 /* descriptor chain end | 146 | * the packet |
125 | * interrupt status */ | 147 | */ |
126 | 148 | /* [17..16] */ | |
127 | #define GELIC_NET_DMAC_CMDSTAT_CHAIN_END 0x00000002 /* RXDCEIS:DMA stopped */ | 149 | GELIC_DESCR_TX_DMA_TCP_CHKSUM = 0x00020000, /* TCP packet */ |
128 | #define GELIC_NET_DESCR_IND_PROC_SHIFT 28 | 150 | GELIC_DESCR_TX_DMA_UDP_CHKSUM = 0x00030000, /* UDP packet */ |
129 | #define GELIC_NET_DESCR_IND_PROC_MASKO 0x0fffffff | 151 | GELIC_DESCR_TX_DMA_NO_CHKSUM = 0x00000000, /* no checksum */ |
130 | 152 | ||
131 | 153 | /* [1] */ | |
132 | enum gelic_net_descr_status { | 154 | GELIC_DESCR_TX_DMA_CHAIN_END = 0x00000002, /* DMA terminated |
133 | GELIC_NET_DESCR_COMPLETE = 0x00, /* used in tx */ | 155 | * due to chain end |
134 | GELIC_NET_DESCR_BUFFER_FULL = 0x00, /* used in rx */ | 156 | */ |
135 | GELIC_NET_DESCR_RESPONSE_ERROR = 0x01, /* used in rx and tx */ | 157 | }; |
136 | GELIC_NET_DESCR_PROTECTION_ERROR = 0x02, /* used in rx and tx */ | 158 | |
137 | GELIC_NET_DESCR_FRAME_END = 0x04, /* used in rx */ | 159 | #define GELIC_DESCR_DMA_CMD_NO_CHKSUM \ |
138 | GELIC_NET_DESCR_FORCE_END = 0x05, /* used in rx and tx */ | 160 | (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \ |
139 | GELIC_NET_DESCR_CARDOWNED = 0x0a, /* used in rx and tx */ | 161 | GELIC_DESCR_TX_DMA_NO_CHKSUM) |
140 | GELIC_NET_DESCR_NOT_IN_USE = 0x0b /* any other value */ | 162 | |
163 | #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \ | ||
164 | (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \ | ||
165 | GELIC_DESCR_TX_DMA_TCP_CHKSUM) | ||
166 | |||
167 | #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \ | ||
168 | (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \ | ||
169 | GELIC_DESCR_TX_DMA_UDP_CHKSUM) | ||
170 | |||
171 | enum gelic_descr_rx_dma_status { | ||
172 | /* [ 1 ] */ | ||
173 | GELIC_DESCR_RX_DMA_CHAIN_END = 0x00000002, /* DMA terminated | ||
174 | * due to chain end | ||
175 | */ | ||
141 | }; | 176 | }; |
177 | |||
142 | /* for lv1_net_control */ | 178 | /* for lv1_net_control */ |
143 | #define GELIC_NET_GET_MAC_ADDRESS 0x0000000000000001 | 179 | enum gelic_lv1_net_control_code { |
144 | #define GELIC_NET_GET_ETH_PORT_STATUS 0x0000000000000002 | 180 | GELIC_LV1_GET_MAC_ADDRESS = 1, |
145 | #define GELIC_NET_SET_NEGOTIATION_MODE 0x0000000000000003 | 181 | GELIC_LV1_GET_ETH_PORT_STATUS = 2, |
146 | #define GELIC_NET_GET_VLAN_ID 0x0000000000000004 | 182 | GELIC_LV1_SET_NEGOTIATION_MODE = 3, |
147 | 183 | GELIC_LV1_GET_VLAN_ID = 4, | |
148 | #define GELIC_NET_LINK_UP 0x0000000000000001 | 184 | }; |
149 | #define GELIC_NET_FULL_DUPLEX 0x0000000000000002 | 185 | |
150 | #define GELIC_NET_AUTO_NEG 0x0000000000000004 | 186 | /* status returened from GET_ETH_PORT_STATUS */ |
151 | #define GELIC_NET_SPEED_10 0x0000000000000010 | 187 | enum gelic_lv1_ether_port_status { |
152 | #define GELIC_NET_SPEED_100 0x0000000000000020 | 188 | GELIC_LV1_ETHER_LINK_UP = 0x0000000000000001L, |
153 | #define GELIC_NET_SPEED_1000 0x0000000000000040 | 189 | GELIC_LV1_ETHER_FULL_DUPLEX = 0x0000000000000002L, |
154 | 190 | GELIC_LV1_ETHER_AUTO_NEG = 0x0000000000000004L, | |
155 | #define GELIC_NET_VLAN_ALL 0x0000000000000001 | 191 | |
156 | #define GELIC_NET_VLAN_WIRED 0x0000000000000002 | 192 | GELIC_LV1_ETHER_SPEED_10 = 0x0000000000000010L, |
157 | #define GELIC_NET_VLAN_WIRELESS 0x0000000000000003 | 193 | GELIC_LV1_ETHER_SPEED_100 = 0x0000000000000020L, |
158 | #define GELIC_NET_VLAN_PSP 0x0000000000000004 | 194 | GELIC_LV1_ETHER_SPEED_1000 = 0x0000000000000040L, |
159 | #define GELIC_NET_VLAN_PORT0 0x0000000000000010 | 195 | GELIC_LV1_ETHER_SPEED_MASK = 0x0000000000000070L |
160 | #define GELIC_NET_VLAN_PORT1 0x0000000000000011 | 196 | }; |
161 | #define GELIC_NET_VLAN_PORT2 0x0000000000000012 | 197 | |
162 | #define GELIC_NET_VLAN_DAEMON_CLIENT_BSS 0x0000000000000013 | 198 | enum gelic_lv1_vlan_index { |
163 | #define GELIC_NET_VLAN_LIBERO_CLIENT_BSS 0x0000000000000014 | 199 | /* for outgoing packets */ |
164 | #define GELIC_NET_VLAN_NO_ENTRY -6 | 200 | GELIC_LV1_VLAN_TX_ETHERNET = 0x0000000000000002L, |
165 | 201 | GELIC_LV1_VLAN_TX_WIRELESS = 0x0000000000000003L, | |
166 | #define GELIC_NET_PORT 2 /* for port status */ | 202 | /* for incoming packets */ |
203 | GELIC_LV1_VLAN_RX_ETHERNET = 0x0000000000000012L, | ||
204 | GELIC_LV1_VLAN_RX_WIRELESS = 0x0000000000000013L | ||
205 | }; | ||
167 | 206 | ||
168 | /* size of hardware part of gelic descriptor */ | 207 | /* size of hardware part of gelic descriptor */ |
169 | #define GELIC_NET_DESCR_SIZE (32) | 208 | #define GELIC_DESCR_SIZE (32) |
170 | struct gelic_net_descr { | 209 | struct gelic_descr { |
171 | /* as defined by the hardware */ | 210 | /* as defined by the hardware */ |
172 | __be32 buf_addr; | 211 | __be32 buf_addr; |
173 | __be32 buf_size; | 212 | __be32 buf_size; |
@@ -181,18 +220,18 @@ struct gelic_net_descr { | |||
181 | /* used in the driver */ | 220 | /* used in the driver */ |
182 | struct sk_buff *skb; | 221 | struct sk_buff *skb; |
183 | dma_addr_t bus_addr; | 222 | dma_addr_t bus_addr; |
184 | struct gelic_net_descr *next; | 223 | struct gelic_descr *next; |
185 | struct gelic_net_descr *prev; | 224 | struct gelic_descr *prev; |
186 | struct vlan_ethhdr vlan; | 225 | struct vlan_ethhdr vlan; |
187 | } __attribute__((aligned(32))); | 226 | } __attribute__((aligned(32))); |
188 | 227 | ||
189 | struct gelic_net_descr_chain { | 228 | struct gelic_descr_chain { |
190 | /* we walk from tail to head */ | 229 | /* we walk from tail to head */ |
191 | struct gelic_net_descr *head; | 230 | struct gelic_descr *head; |
192 | struct gelic_net_descr *tail; | 231 | struct gelic_descr *tail; |
193 | }; | 232 | }; |
194 | 233 | ||
195 | struct gelic_net_card { | 234 | struct gelic_card { |
196 | struct net_device *netdev; | 235 | struct net_device *netdev; |
197 | struct napi_struct napi; | 236 | struct napi_struct napi; |
198 | /* | 237 | /* |
@@ -207,8 +246,8 @@ struct gelic_net_card { | |||
207 | u32 vlan_id[GELIC_NET_VLAN_MAX]; | 246 | u32 vlan_id[GELIC_NET_VLAN_MAX]; |
208 | int vlan_index; | 247 | int vlan_index; |
209 | 248 | ||
210 | struct gelic_net_descr_chain tx_chain; | 249 | struct gelic_descr_chain tx_chain; |
211 | struct gelic_net_descr_chain rx_chain; | 250 | struct gelic_descr_chain rx_chain; |
212 | int rx_dma_restart_required; | 251 | int rx_dma_restart_required; |
213 | /* gurad dmac descriptor chain*/ | 252 | /* gurad dmac descriptor chain*/ |
214 | spinlock_t chain_lock; | 253 | spinlock_t chain_lock; |
@@ -222,8 +261,8 @@ struct gelic_net_card { | |||
222 | atomic_t tx_timeout_task_counter; | 261 | atomic_t tx_timeout_task_counter; |
223 | wait_queue_head_t waitq; | 262 | wait_queue_head_t waitq; |
224 | 263 | ||
225 | struct gelic_net_descr *tx_top, *rx_top; | 264 | struct gelic_descr *tx_top, *rx_top; |
226 | struct gelic_net_descr descr[0]; | 265 | struct gelic_descr descr[0]; |
227 | }; | 266 | }; |
228 | 267 | ||
229 | 268 | ||