diff options
author | Giuseppe CAVALLARO <peppe.cavallaro@st.com> | 2011-08-22 17:07:14 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-08-26 12:48:24 -0400 |
commit | 6e6f400f5381e08dc80e1b5a37ed02a081c179d9 (patch) | |
tree | 40eb251b991f078a62dd1b73b606956446c7db62 /drivers/net/phy | |
parent | e2e6be56df37c371f564e127c154036b0c2211a1 (diff) |
net/phy: fix DP83865 phy interrupt handler
According to the DP83865 datasheet we need to clear
the interrupt status bit by writing a 1 to the
corresponding bit in INT_CLEAR (2:0 are reserved).
Proposed and tested by Thorsten.
Signed-off-by: Thorsten Schubert <tshu@msc-ge.com>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/phy')
-rw-r--r-- | drivers/net/phy/national.c | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/net/phy/national.c b/drivers/net/phy/national.c index 0620ba963508..04bb8fcc0cb5 100644 --- a/drivers/net/phy/national.c +++ b/drivers/net/phy/national.c | |||
@@ -25,8 +25,9 @@ | |||
25 | /* DP83865 phy identifier values */ | 25 | /* DP83865 phy identifier values */ |
26 | #define DP83865_PHY_ID 0x20005c7a | 26 | #define DP83865_PHY_ID 0x20005c7a |
27 | 27 | ||
28 | #define DP83865_INT_MASK_REG 0x15 | 28 | #define DP83865_INT_STATUS 0x14 |
29 | #define DP83865_INT_MASK_STATUS 0x14 | 29 | #define DP83865_INT_MASK 0x15 |
30 | #define DP83865_INT_CLEAR 0x17 | ||
30 | 31 | ||
31 | #define DP83865_INT_REMOTE_FAULT 0x0008 | 32 | #define DP83865_INT_REMOTE_FAULT 0x0008 |
32 | #define DP83865_INT_ANE_COMPLETED 0x0010 | 33 | #define DP83865_INT_ANE_COMPLETED 0x0010 |
@@ -68,21 +69,25 @@ static int ns_config_intr(struct phy_device *phydev) | |||
68 | int err; | 69 | int err; |
69 | 70 | ||
70 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | 71 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
71 | err = phy_write(phydev, DP83865_INT_MASK_REG, | 72 | err = phy_write(phydev, DP83865_INT_MASK, |
72 | DP83865_INT_MASK_DEFAULT); | 73 | DP83865_INT_MASK_DEFAULT); |
73 | else | 74 | else |
74 | err = phy_write(phydev, DP83865_INT_MASK_REG, 0); | 75 | err = phy_write(phydev, DP83865_INT_MASK, 0); |
75 | 76 | ||
76 | return err; | 77 | return err; |
77 | } | 78 | } |
78 | 79 | ||
79 | static int ns_ack_interrupt(struct phy_device *phydev) | 80 | static int ns_ack_interrupt(struct phy_device *phydev) |
80 | { | 81 | { |
81 | int ret = phy_read(phydev, DP83865_INT_MASK_STATUS); | 82 | int ret = phy_read(phydev, DP83865_INT_STATUS); |
82 | if (ret < 0) | 83 | if (ret < 0) |
83 | return ret; | 84 | return ret; |
84 | 85 | ||
85 | return 0; | 86 | /* Clear the interrupt status bit by writing a “1” |
87 | * to the corresponding bit in INT_CLEAR (2:0 are reserved) */ | ||
88 | ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); | ||
89 | |||
90 | return ret; | ||
86 | } | 91 | } |
87 | 92 | ||
88 | static void ns_giga_speed_fallback(struct phy_device *phydev, int mode) | 93 | static void ns_giga_speed_fallback(struct phy_device *phydev, int mode) |