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authorArnd Bergmann <arnd@arndb.de>2012-05-11 11:15:31 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-11 11:15:31 -0400
commit93c6d8927fa692faef3d7d945bd4fe84b0185ad4 (patch)
tree0a971c86114656ec4e39f7789d9faeb70432c36a /drivers/net/phy/icplus.c
parentea01d31a07ae182028d2398380948f5a4ee09953 (diff)
parent50260924afd4b745bfb6e5f1caee381a1875fc31 (diff)
Merge branch 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/clock
Shawn Guo <shawn.guo@linaro.org> writes: mxs common clk porting for v3.5. It depends on the following two branches. [1] git://git.linaro.org/people/mturquette/linux.git clk-next [2] http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-arm.git clkdev As the mxs device tree conversion will constantly touch clock files, to save the conflicts, the updated mxs/dt branch coming later will based on this pull-request. * 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: mxs: remove now unused timer_clk argument from mxs_timer_init ARM: mxs: remove old clock support ARM: mxs: switch to common clk framework ARM: mxs: change the lookup name for fec phy clock ARM: mxs: request clock for timer clk: mxs: add clock support for imx28 clk: mxs: add clock support for imx23 clk: mxs: add mxs specific clocks Includes an update to Linux 3.4-rc6 Conflicts: drivers/clk/Makefile Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'drivers/net/phy/icplus.c')
-rw-r--r--drivers/net/phy/icplus.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
index f08c85acf761..5ac46f5226f3 100644
--- a/drivers/net/phy/icplus.c
+++ b/drivers/net/phy/icplus.c
@@ -40,6 +40,7 @@ MODULE_LICENSE("GPL");
40#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */ 40#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
41#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */ 41#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
42#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */ 42#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
43#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
43 44
44static int ip175c_config_init(struct phy_device *phydev) 45static int ip175c_config_init(struct phy_device *phydev)
45{ 46{
@@ -185,6 +186,15 @@ static int ip175c_config_aneg(struct phy_device *phydev)
185 return 0; 186 return 0;
186} 187}
187 188
189static int ip101a_g_ack_interrupt(struct phy_device *phydev)
190{
191 int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
192 if (err < 0)
193 return err;
194
195 return 0;
196}
197
188static struct phy_driver ip175c_driver = { 198static struct phy_driver ip175c_driver = {
189 .phy_id = 0x02430d80, 199 .phy_id = 0x02430d80,
190 .name = "ICPlus IP175C", 200 .name = "ICPlus IP175C",
@@ -204,7 +214,6 @@ static struct phy_driver ip1001_driver = {
204 .phy_id_mask = 0x0ffffff0, 214 .phy_id_mask = 0x0ffffff0,
205 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | 215 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
206 SUPPORTED_Asym_Pause, 216 SUPPORTED_Asym_Pause,
207 .flags = PHY_HAS_INTERRUPT,
208 .config_init = &ip1001_config_init, 217 .config_init = &ip1001_config_init,
209 .config_aneg = &genphy_config_aneg, 218 .config_aneg = &genphy_config_aneg,
210 .read_status = &genphy_read_status, 219 .read_status = &genphy_read_status,
@@ -220,6 +229,7 @@ static struct phy_driver ip101a_g_driver = {
220 .features = PHY_BASIC_FEATURES | SUPPORTED_Pause | 229 .features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
221 SUPPORTED_Asym_Pause, 230 SUPPORTED_Asym_Pause,
222 .flags = PHY_HAS_INTERRUPT, 231 .flags = PHY_HAS_INTERRUPT,
232 .ack_interrupt = ip101a_g_ack_interrupt,
223 .config_init = &ip101a_g_config_init, 233 .config_init = &ip101a_g_config_init,
224 .config_aneg = &genphy_config_aneg, 234 .config_aneg = &genphy_config_aneg,
225 .read_status = &genphy_read_status, 235 .read_status = &genphy_read_status,