diff options
author | Olof Johansson <olof@lixom.net> | 2007-09-15 16:40:59 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-10 19:50:55 -0400 |
commit | a85b94222d8b95e184941183f28b06b637cc4dee (patch) | |
tree | b83e26302446e28f63af90bbcd838ef74deea1e9 /drivers/net/pasemi_mac.c | |
parent | ced13330bb687780ce1d46f5404521cc0ea40481 (diff) |
pasemi_mac: Abstract out register access
Abstract out the PCI config read/write accesses into reg read/write ones,
still calling the pci accessors on the back end.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/pasemi_mac.c')
-rw-r--r-- | drivers/net/pasemi_mac.c | 195 |
1 files changed, 101 insertions, 94 deletions
diff --git a/drivers/net/pasemi_mac.c b/drivers/net/pasemi_mac.c index e63cc335a4ba..c3a0fc64de0c 100644 --- a/drivers/net/pasemi_mac.c +++ b/drivers/net/pasemi_mac.c | |||
@@ -81,6 +81,48 @@ MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value"); | |||
81 | 81 | ||
82 | static struct pasdma_status *dma_status; | 82 | static struct pasdma_status *dma_status; |
83 | 83 | ||
84 | static unsigned int read_iob_reg(struct pasemi_mac *mac, unsigned int reg) | ||
85 | { | ||
86 | unsigned int val; | ||
87 | |||
88 | pci_read_config_dword(mac->iob_pdev, reg, &val); | ||
89 | return val; | ||
90 | } | ||
91 | |||
92 | static void write_iob_reg(struct pasemi_mac *mac, unsigned int reg, | ||
93 | unsigned int val) | ||
94 | { | ||
95 | pci_write_config_dword(mac->iob_pdev, reg, val); | ||
96 | } | ||
97 | |||
98 | static unsigned int read_mac_reg(struct pasemi_mac *mac, unsigned int reg) | ||
99 | { | ||
100 | unsigned int val; | ||
101 | |||
102 | pci_read_config_dword(mac->pdev, reg, &val); | ||
103 | return val; | ||
104 | } | ||
105 | |||
106 | static void write_mac_reg(struct pasemi_mac *mac, unsigned int reg, | ||
107 | unsigned int val) | ||
108 | { | ||
109 | pci_write_config_dword(mac->pdev, reg, val); | ||
110 | } | ||
111 | |||
112 | static unsigned int read_dma_reg(struct pasemi_mac *mac, unsigned int reg) | ||
113 | { | ||
114 | unsigned int val; | ||
115 | |||
116 | pci_read_config_dword(mac->dma_pdev, reg, &val); | ||
117 | return val; | ||
118 | } | ||
119 | |||
120 | static void write_dma_reg(struct pasemi_mac *mac, unsigned int reg, | ||
121 | unsigned int val) | ||
122 | { | ||
123 | pci_write_config_dword(mac->dma_pdev, reg, val); | ||
124 | } | ||
125 | |||
84 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) | 126 | static int pasemi_get_mac_addr(struct pasemi_mac *mac) |
85 | { | 127 | { |
86 | struct pci_dev *pdev = mac->pdev; | 128 | struct pci_dev *pdev = mac->pdev; |
@@ -166,22 +208,21 @@ static int pasemi_mac_setup_rx_resources(struct net_device *dev) | |||
166 | 208 | ||
167 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); | 209 | memset(ring->buffers, 0, RX_RING_SIZE * sizeof(u64)); |
168 | 210 | ||
169 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEL(chan_id), | 211 | write_dma_reg(mac, PAS_DMA_RXCHAN_BASEL(chan_id), PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma)); |
170 | PAS_DMA_RXCHAN_BASEL_BRBL(ring->dma)); | ||
171 | 212 | ||
172 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_BASEU(chan_id), | 213 | write_dma_reg(mac, PAS_DMA_RXCHAN_BASEU(chan_id), |
173 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) | | 214 | PAS_DMA_RXCHAN_BASEU_BRBH(ring->dma >> 32) | |
174 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2)); | 215 | PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 2)); |
175 | 216 | ||
176 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXCHAN_CFG(chan_id), | 217 | write_dma_reg(mac, PAS_DMA_RXCHAN_CFG(chan_id), |
177 | PAS_DMA_RXCHAN_CFG_HBU(1)); | 218 | PAS_DMA_RXCHAN_CFG_HBU(1)); |
178 | 219 | ||
179 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEL(mac->dma_if), | 220 | write_dma_reg(mac, PAS_DMA_RXINT_BASEL(mac->dma_if), |
180 | PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers))); | 221 | PAS_DMA_RXINT_BASEL_BRBL(__pa(ring->buffers))); |
181 | 222 | ||
182 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_RXINT_BASEU(mac->dma_if), | 223 | write_dma_reg(mac, PAS_DMA_RXINT_BASEU(mac->dma_if), |
183 | PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) | | 224 | PAS_DMA_RXINT_BASEU_BRBH(__pa(ring->buffers) >> 32) | |
184 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); | 225 | PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3)); |
185 | 226 | ||
186 | ring->next_to_fill = 0; | 227 | ring->next_to_fill = 0; |
187 | ring->next_to_clean = 0; | 228 | ring->next_to_clean = 0; |
@@ -233,18 +274,18 @@ static int pasemi_mac_setup_tx_resources(struct net_device *dev) | |||
233 | 274 | ||
234 | memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr)); | 275 | memset(ring->desc, 0, TX_RING_SIZE * sizeof(struct pas_dma_xct_descr)); |
235 | 276 | ||
236 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEL(chan_id), | 277 | write_dma_reg(mac, PAS_DMA_TXCHAN_BASEL(chan_id), |
237 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); | 278 | PAS_DMA_TXCHAN_BASEL_BRBL(ring->dma)); |
238 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); | 279 | val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->dma >> 32); |
239 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); | 280 | val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 2); |
240 | 281 | ||
241 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_BASEU(chan_id), val); | 282 | write_dma_reg(mac, PAS_DMA_TXCHAN_BASEU(chan_id), val); |
242 | 283 | ||
243 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_TXCHAN_CFG(chan_id), | 284 | write_dma_reg(mac, PAS_DMA_TXCHAN_CFG(chan_id), |
244 | PAS_DMA_TXCHAN_CFG_TY_IFACE | | 285 | PAS_DMA_TXCHAN_CFG_TY_IFACE | |
245 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | | 286 | PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) | |
246 | PAS_DMA_TXCHAN_CFG_UP | | 287 | PAS_DMA_TXCHAN_CFG_UP | |
247 | PAS_DMA_TXCHAN_CFG_WT(2)); | 288 | PAS_DMA_TXCHAN_CFG_WT(2)); |
248 | 289 | ||
249 | ring->next_to_use = 0; | 290 | ring->next_to_use = 0; |
250 | ring->next_to_clean = 0; | 291 | ring->next_to_clean = 0; |
@@ -383,12 +424,8 @@ static void pasemi_mac_replenish_rx_ring(struct net_device *dev) | |||
383 | 424 | ||
384 | wmb(); | 425 | wmb(); |
385 | 426 | ||
386 | pci_write_config_dword(mac->dma_pdev, | 427 | write_dma_reg(mac, PAS_DMA_RXCHAN_INCR(mac->dma_rxch), limit - count); |
387 | PAS_DMA_RXCHAN_INCR(mac->dma_rxch), | 428 | write_dma_reg(mac, PAS_DMA_RXINT_INCR(mac->dma_if), limit - count); |
388 | limit - count); | ||
389 | pci_write_config_dword(mac->dma_pdev, | ||
390 | PAS_DMA_RXINT_INCR(mac->dma_if), | ||
391 | limit - count); | ||
392 | 429 | ||
393 | mac->rx->next_to_fill += limit - count; | 430 | mac->rx->next_to_fill += limit - count; |
394 | } | 431 | } |
@@ -404,9 +441,7 @@ static void pasemi_mac_restart_rx_intr(struct pasemi_mac *mac) | |||
404 | 441 | ||
405 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; | 442 | reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC; |
406 | 443 | ||
407 | pci_write_config_dword(mac->iob_pdev, | 444 | write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg); |
408 | PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), | ||
409 | reg); | ||
410 | } | 445 | } |
411 | 446 | ||
412 | static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac) | 447 | static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac) |
@@ -418,8 +453,7 @@ static void pasemi_mac_restart_tx_intr(struct pasemi_mac *mac) | |||
418 | 453 | ||
419 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; | 454 | reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC; |
420 | 455 | ||
421 | pci_write_config_dword(mac->iob_pdev, | 456 | write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg); |
422 | PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg); | ||
423 | } | 457 | } |
424 | 458 | ||
425 | 459 | ||
@@ -574,8 +608,6 @@ static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |||
574 | * all others. | 608 | * all others. |
575 | */ | 609 | */ |
576 | 610 | ||
577 | pci_read_config_dword(mac->dma_pdev, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), ®); | ||
578 | |||
579 | reg = 0; | 611 | reg = 0; |
580 | if (*mac->rx_status & PAS_STATUS_SOFT) | 612 | if (*mac->rx_status & PAS_STATUS_SOFT) |
581 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; | 613 | reg |= PAS_IOB_DMA_RXCH_RESET_SINTC; |
@@ -586,9 +618,7 @@ static irqreturn_t pasemi_mac_rx_intr(int irq, void *data) | |||
586 | 618 | ||
587 | netif_rx_schedule(dev, &mac->napi); | 619 | netif_rx_schedule(dev, &mac->napi); |
588 | 620 | ||
589 | pci_write_config_dword(mac->iob_pdev, | 621 | write_iob_reg(mac, PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg); |
590 | PAS_IOB_DMA_RXCH_RESET(mac->dma_rxch), reg); | ||
591 | |||
592 | 622 | ||
593 | return IRQ_HANDLED; | 623 | return IRQ_HANDLED; |
594 | } | 624 | } |
@@ -613,9 +643,7 @@ static irqreturn_t pasemi_mac_tx_intr(int irq, void *data) | |||
613 | if (*mac->tx_status & PAS_STATUS_ERROR) | 643 | if (*mac->tx_status & PAS_STATUS_ERROR) |
614 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; | 644 | reg |= PAS_IOB_DMA_TXCH_RESET_DINTC; |
615 | 645 | ||
616 | pci_write_config_dword(mac->iob_pdev, | 646 | write_iob_reg(mac, PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), reg); |
617 | PAS_IOB_DMA_TXCH_RESET(mac->dma_txch), | ||
618 | reg); | ||
619 | 647 | ||
620 | return IRQ_HANDLED; | 648 | return IRQ_HANDLED; |
621 | } | 649 | } |
@@ -641,7 +669,7 @@ static void pasemi_adjust_link(struct net_device *dev) | |||
641 | } else | 669 | } else |
642 | netif_carrier_on(dev); | 670 | netif_carrier_on(dev); |
643 | 671 | ||
644 | pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags); | 672 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
645 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | | 673 | new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M | |
646 | PAS_MAC_CFG_PCFG_TSR_M); | 674 | PAS_MAC_CFG_PCFG_TSR_M); |
647 | 675 | ||
@@ -673,7 +701,7 @@ static void pasemi_adjust_link(struct net_device *dev) | |||
673 | mac->link = mac->phydev->link; | 701 | mac->link = mac->phydev->link; |
674 | 702 | ||
675 | if (new_flags != flags) | 703 | if (new_flags != flags) |
676 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, new_flags); | 704 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags); |
677 | 705 | ||
678 | if (msg && netif_msg_link(mac)) | 706 | if (msg && netif_msg_link(mac)) |
679 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", | 707 | printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n", |
@@ -736,39 +764,37 @@ static int pasemi_mac_open(struct net_device *dev) | |||
736 | int ret; | 764 | int ret; |
737 | 765 | ||
738 | /* enable rx section */ | 766 | /* enable rx section */ |
739 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_RXCMD, | 767 | write_dma_reg(mac, PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN); |
740 | PAS_DMA_COM_RXCMD_EN); | ||
741 | 768 | ||
742 | /* enable tx section */ | 769 | /* enable tx section */ |
743 | pci_write_config_dword(mac->dma_pdev, PAS_DMA_COM_TXCMD, | 770 | write_dma_reg(mac, PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); |
744 | PAS_DMA_COM_TXCMD_EN); | ||
745 | 771 | ||
746 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | | 772 | flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) | |
747 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | | 773 | PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) | |
748 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); | 774 | PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12); |
749 | 775 | ||
750 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_TXP, flags); | 776 | write_mac_reg(mac, PAS_MAC_CFG_TXP, flags); |
751 | 777 | ||
752 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE | | 778 | flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PE | |
753 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; | 779 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE; |
754 | 780 | ||
755 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; | 781 | flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G; |
756 | 782 | ||
757 | pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch), | 783 | write_iob_reg(mac, PAS_IOB_DMA_RXCH_CFG(mac->dma_rxch), |
758 | PAS_IOB_DMA_RXCH_CFG_CNTTH(0)); | 784 | PAS_IOB_DMA_RXCH_CFG_CNTTH(0)); |
759 | 785 | ||
760 | pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch), | 786 | write_iob_reg(mac, PAS_IOB_DMA_TXCH_CFG(mac->dma_txch), |
761 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); | 787 | PAS_IOB_DMA_TXCH_CFG_CNTTH(32)); |
762 | 788 | ||
763 | /* Clear out any residual packet count state from firmware */ | 789 | /* Clear out any residual packet count state from firmware */ |
764 | pasemi_mac_restart_rx_intr(mac); | 790 | pasemi_mac_restart_rx_intr(mac); |
765 | pasemi_mac_restart_tx_intr(mac); | 791 | pasemi_mac_restart_tx_intr(mac); |
766 | 792 | ||
767 | /* 0xffffff is max value, about 16ms */ | 793 | /* 0xffffff is max value, about 16ms */ |
768 | pci_write_config_dword(mac->iob_pdev, PAS_IOB_DMA_COM_TIMEOUTCFG, | 794 | write_iob_reg(mac, PAS_IOB_DMA_COM_TIMEOUTCFG, |
769 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff)); | 795 | PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0xffffff)); |
770 | 796 | ||
771 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags); | 797 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
772 | 798 | ||
773 | ret = pasemi_mac_setup_rx_resources(dev); | 799 | ret = pasemi_mac_setup_rx_resources(dev); |
774 | if (ret) | 800 | if (ret) |
@@ -778,25 +804,22 @@ static int pasemi_mac_open(struct net_device *dev) | |||
778 | if (ret) | 804 | if (ret) |
779 | goto out_tx_resources; | 805 | goto out_tx_resources; |
780 | 806 | ||
781 | pci_write_config_dword(mac->pdev, PAS_MAC_IPC_CHNL, | 807 | write_mac_reg(mac, PAS_MAC_IPC_CHNL, |
782 | PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) | | 808 | PAS_MAC_IPC_CHNL_DCHNO(mac->dma_rxch) | |
783 | PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch)); | 809 | PAS_MAC_IPC_CHNL_BCH(mac->dma_rxch)); |
784 | 810 | ||
785 | /* enable rx if */ | 811 | /* enable rx if */ |
786 | pci_write_config_dword(mac->dma_pdev, | 812 | write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), |
787 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | 813 | PAS_DMA_RXINT_RCMDSTA_EN); |
788 | PAS_DMA_RXINT_RCMDSTA_EN); | ||
789 | 814 | ||
790 | /* enable rx channel */ | 815 | /* enable rx channel */ |
791 | pci_write_config_dword(mac->dma_pdev, | 816 | write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), |
792 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), | 817 | PAS_DMA_RXCHAN_CCMDSTA_EN | |
793 | PAS_DMA_RXCHAN_CCMDSTA_EN | | 818 | PAS_DMA_RXCHAN_CCMDSTA_DU); |
794 | PAS_DMA_RXCHAN_CCMDSTA_DU); | ||
795 | 819 | ||
796 | /* enable tx channel */ | 820 | /* enable tx channel */ |
797 | pci_write_config_dword(mac->dma_pdev, | 821 | write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), |
798 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), | 822 | PAS_DMA_TXCHAN_TCMDSTA_EN); |
799 | PAS_DMA_TXCHAN_TCMDSTA_EN); | ||
800 | 823 | ||
801 | pasemi_mac_replenish_rx_ring(dev); | 824 | pasemi_mac_replenish_rx_ring(dev); |
802 | 825 | ||
@@ -876,20 +899,12 @@ static int pasemi_mac_close(struct net_device *dev) | |||
876 | pasemi_mac_clean_rx(mac, RX_RING_SIZE); | 899 | pasemi_mac_clean_rx(mac, RX_RING_SIZE); |
877 | 900 | ||
878 | /* Disable interface */ | 901 | /* Disable interface */ |
879 | pci_write_config_dword(mac->dma_pdev, | 902 | write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), PAS_DMA_TXCHAN_TCMDSTA_ST); |
880 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), | 903 | write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), PAS_DMA_RXINT_RCMDSTA_ST); |
881 | PAS_DMA_TXCHAN_TCMDSTA_ST); | 904 | write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), PAS_DMA_RXCHAN_CCMDSTA_ST); |
882 | pci_write_config_dword(mac->dma_pdev, | ||
883 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | ||
884 | PAS_DMA_RXINT_RCMDSTA_ST); | ||
885 | pci_write_config_dword(mac->dma_pdev, | ||
886 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), | ||
887 | PAS_DMA_RXCHAN_CCMDSTA_ST); | ||
888 | 905 | ||
889 | for (retries = 0; retries < MAX_RETRIES; retries++) { | 906 | for (retries = 0; retries < MAX_RETRIES; retries++) { |
890 | pci_read_config_dword(mac->dma_pdev, | 907 | stat = read_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch)); |
891 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), | ||
892 | &stat); | ||
893 | if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) | 908 | if (!(stat & PAS_DMA_TXCHAN_TCMDSTA_ACT)) |
894 | break; | 909 | break; |
895 | cond_resched(); | 910 | cond_resched(); |
@@ -899,9 +914,7 @@ static int pasemi_mac_close(struct net_device *dev) | |||
899 | dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n"); | 914 | dev_err(&mac->dma_pdev->dev, "Failed to stop tx channel\n"); |
900 | 915 | ||
901 | for (retries = 0; retries < MAX_RETRIES; retries++) { | 916 | for (retries = 0; retries < MAX_RETRIES; retries++) { |
902 | pci_read_config_dword(mac->dma_pdev, | 917 | stat = read_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch)); |
903 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), | ||
904 | &stat); | ||
905 | if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)) | 918 | if (!(stat & PAS_DMA_RXCHAN_CCMDSTA_ACT)) |
906 | break; | 919 | break; |
907 | cond_resched(); | 920 | cond_resched(); |
@@ -911,9 +924,7 @@ static int pasemi_mac_close(struct net_device *dev) | |||
911 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n"); | 924 | dev_err(&mac->dma_pdev->dev, "Failed to stop rx channel\n"); |
912 | 925 | ||
913 | for (retries = 0; retries < MAX_RETRIES; retries++) { | 926 | for (retries = 0; retries < MAX_RETRIES; retries++) { |
914 | pci_read_config_dword(mac->dma_pdev, | 927 | stat = read_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if)); |
915 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), | ||
916 | &stat); | ||
917 | if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT)) | 928 | if (!(stat & PAS_DMA_RXINT_RCMDSTA_ACT)) |
918 | break; | 929 | break; |
919 | cond_resched(); | 930 | cond_resched(); |
@@ -926,12 +937,9 @@ static int pasemi_mac_close(struct net_device *dev) | |||
926 | * stopping, since you can't disable when active. | 937 | * stopping, since you can't disable when active. |
927 | */ | 938 | */ |
928 | 939 | ||
929 | pci_write_config_dword(mac->dma_pdev, | 940 | write_dma_reg(mac, PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0); |
930 | PAS_DMA_TXCHAN_TCMDSTA(mac->dma_txch), 0); | 941 | write_dma_reg(mac, PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0); |
931 | pci_write_config_dword(mac->dma_pdev, | 942 | write_dma_reg(mac, PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); |
932 | PAS_DMA_RXCHAN_CCMDSTA(mac->dma_rxch), 0); | ||
933 | pci_write_config_dword(mac->dma_pdev, | ||
934 | PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0); | ||
935 | 943 | ||
936 | free_irq(mac->tx_irq, dev); | 944 | free_irq(mac->tx_irq, dev); |
937 | free_irq(mac->rx_irq, dev); | 945 | free_irq(mac->rx_irq, dev); |
@@ -1012,8 +1020,7 @@ static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) | |||
1012 | 1020 | ||
1013 | spin_unlock_irqrestore(&txring->lock, flags); | 1021 | spin_unlock_irqrestore(&txring->lock, flags); |
1014 | 1022 | ||
1015 | pci_write_config_dword(mac->dma_pdev, | 1023 | write_dma_reg(mac, PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1); |
1016 | PAS_DMA_TXCHAN_INCR(mac->dma_txch), 1); | ||
1017 | 1024 | ||
1018 | return NETDEV_TX_OK; | 1025 | return NETDEV_TX_OK; |
1019 | 1026 | ||
@@ -1036,7 +1043,7 @@ static void pasemi_mac_set_rx_mode(struct net_device *dev) | |||
1036 | struct pasemi_mac *mac = netdev_priv(dev); | 1043 | struct pasemi_mac *mac = netdev_priv(dev); |
1037 | unsigned int flags; | 1044 | unsigned int flags; |
1038 | 1045 | ||
1039 | pci_read_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, &flags); | 1046 | flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG); |
1040 | 1047 | ||
1041 | /* Set promiscuous */ | 1048 | /* Set promiscuous */ |
1042 | if (dev->flags & IFF_PROMISC) | 1049 | if (dev->flags & IFF_PROMISC) |
@@ -1044,7 +1051,7 @@ static void pasemi_mac_set_rx_mode(struct net_device *dev) | |||
1044 | else | 1051 | else |
1045 | flags &= ~PAS_MAC_CFG_PCFG_PR; | 1052 | flags &= ~PAS_MAC_CFG_PCFG_PR; |
1046 | 1053 | ||
1047 | pci_write_config_dword(mac->pdev, PAS_MAC_CFG_PCFG, flags); | 1054 | write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags); |
1048 | } | 1055 | } |
1049 | 1056 | ||
1050 | 1057 | ||