NIU: Add Sun CP3260 ATCA blade support

This patch adds support for the Sun CP3260 ATCA blade which is
a N2 based ATCA blade with 2 NIU ports. The NIU ports do not
have on-board PHY.

Signed-off-by: Santwona Behera <santwona.behera@sun.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 13 insertions, 0 deletions

diff --git a/drivers/net/niu.h b/drivers/net/niu.h
index c6fa883daa22..180ca8ae93de 100644
--- a/drivers/net/niu.h
+++ b/drivers/net/niu.h
@@ -1048,6 +1048,13 @@
 #define  PLL_CFG_LD_SHIFT               8
 #define  PLL_CFG_MPY                    0x0000001e
 #define  PLL_CFG_MPY_SHIFT              1
+#define  PLL_CFG_MPY_4X         0x0
+#define  PLL_CFG_MPY_5X         0x00000002
+#define  PLL_CFG_MPY_6X         0x00000004
+#define  PLL_CFG_MPY_8X         0x00000008
+#define  PLL_CFG_MPY_10X                0x0000000a
+#define  PLL_CFG_MPY_12X                0x0000000c
+#define  PLL_CFG_MPY_12P5X              0x0000000e
 #define  PLL_CFG_ENPLL                  0x00000001
 
 #define ESR2_TI_PLL_STS_L               (ESR2_BASE + 0x002)
@@ -1093,6 +1100,9 @@
 #define  PLL_TX_CFG_INVPAIR             0x00000080
 #define  PLL_TX_CFG_RATE                0x00000060
 #define  PLL_TX_CFG_RATE_SHIFT          5
+#define  PLL_TX_CFG_RATE_FULL           0x0
+#define  PLL_TX_CFG_RATE_HALF           0x20
+#define  PLL_TX_CFG_RATE_QUAD           0x40
 #define  PLL_TX_CFG_BUSWIDTH            0x0000001c
 #define  PLL_TX_CFG_BUSWIDTH_SHIFT      2
 #define  PLL_TX_CFG_ENTEST              0x00000002
@@ -1132,6 +1142,9 @@
 #define  PLL_RX_CFG_INVPAIR             0x00000080
 #define  PLL_RX_CFG_RATE                0x00000060
 #define  PLL_RX_CFG_RATE_SHIFT          5
+#define  PLL_RX_CFG_RATE_FULL           0x0
+#define  PLL_RX_CFG_RATE_HALF           0x20
+#define  PLL_RX_CFG_RATE_QUAD           0x40
 #define  PLL_RX_CFG_BUSWIDTH            0x0000001c
 #define  PLL_RX_CFG_BUSWIDTH_SHIFT      2
 #define  PLL_RX_CFG_ENTEST              0x00000002